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From: Timur Tabi <timur@codeaurora.org>
To: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Andy Gross <andy.gross@linaro.org>,
	Stephen Boyd <sboyd@codeaurora.org>,
	linux-gpio@vger.kernel.org
Subject: Re: Sparse GPIO maps with pinctrl-msm.c?
Date: Fri, 16 Jun 2017 14:07:59 -0500	[thread overview]
Message-ID: <5dcca3bd-7a14-271c-ab5e-0eea3e0a575c@codeaurora.org> (raw)
In-Reply-To: <20170616185001.GD17640@tuxbook>

On 06/16/2017 01:50 PM, Bjorn Andersson wrote:
> So what you're saying is that it's decided that you're not going to use
> "qdss_tracedata" and in some document it's described that these 32 TLMM
> pins are available for customers to utilize as GPIOs?

Well, nothing is "decided" just yet, but that is the idea.

> If so I think the GPIOs should still be numbered based on their
> numbering in the datasheet (i.e. gpio116), but that you should be using
> "line-names" to define the logical naming of these 32 gpios based on
> your customer documentation.

That's what I was hoping on doing, but that requires a sparse GPIO map. 
gpio116 is valid, but gpio1 is not.  Any attempt to access that gpio 
causes an XPU violation.

>>> I think that it would be nice to come up with a solution that works for
>>> the other users of pinctrl-msm as well.
>> I agree. It's hard for me to wrap my head around it, though, because the
>> whole groups vs pins things keeps confusing me.  The driver pretends that
>> you can have more than one pin per group, but that's just not true, and
>> instead it only works if each group represents a single TLMM block.
>>
> A pin represents a pad on the chip and a group represents a
> "configurable entity" in TLMM.

Fair enough, but each TLMM entry only maps to 0 or 1 pins.

> For GPIOs this doesn't make a difference, but rather than naming the
> pins "sdc2_data" there should be pins named "SDC2_DATA_0" ...
> "SDC2_DATA_3". But the configurable entity is "sdc2_data", so that's
> what should go in the "group".

I don't understand the SDC_PINGROUP() macro.  Most of the values are set 
to -1:

		.intr_cfg_reg = 0,			\
		.intr_status_reg = 0,			\
		.intr_target_reg = 0,			\
		.mux_bit = -1,				\
		.pull_bit = pull,			\
		.drv_bit = drv,				\
		.oe_bit = -1,				\
		.in_bit = -1,				\
		.out_bit = -1,				\

I'm not familiar with that SOC, but this looks to me like it's a 
non-TLMM GPIO. In that case, what's the point of including it?  What 
does this actually do?  It's a "configurable entity", but there doesn't 
appear any way to configure it.

> According to the pinctrl documentation we should actually have called
> the pins of the sdc2_data group "P3", "R6", "T7" and "P7" (for
> APQ8016E). If nothing else this would probably have made things less
> confusing.

Not for me.

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

  reply	other threads:[~2017-06-16 19:08 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-13 23:35 Sparse GPIO maps with pinctrl-msm.c? Timur Tabi
2017-06-14 18:59 ` Timur Tabi
2017-06-16 15:07 ` Stephen Boyd
2017-06-16 15:15   ` Timur Tabi
2017-06-16 15:41     ` Stephen Boyd
2017-06-16 15:49       ` Timur Tabi
2017-06-16 16:06         ` Bjorn Andersson
2017-06-16 16:17           ` Timur Tabi
2017-06-16 16:21             ` Andy Gross
2017-06-16 16:26               ` Timur Tabi
2017-06-16 17:44                 ` Bjorn Andersson
2017-06-16 18:10                   ` Timur Tabi
2017-06-16 18:50                     ` Bjorn Andersson
2017-06-16 19:07                       ` Timur Tabi [this message]
2017-06-29  4:59                         ` Bjorn Andersson
2017-06-20 23:10                   ` Timur Tabi
2017-06-16 15:55     ` Bjorn Andersson
2017-06-16 16:07       ` Timur Tabi
2017-06-16 16:35         ` Bjorn Andersson
2017-06-16 18:42           ` Timur Tabi

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