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charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <7267f37b-4f80-97e3-7a8e-bc1a9a28b995@linaro.org> Content-Language: en-US Content-ID: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: daniel.lezcano@linaro.org, alexandre.belloni@bootlin.com Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ludovic.Desroches@microchip.com, robh+dt@kernel.org, tglx@linutronix.de, arnd.bergmann@linaro.org, linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org Hi Daniel, On 31.05.2019 13:41, Daniel Lezcano wrote: > > Hi Claudiu, > > > On 30/05/2019 09:46, Claudiu.Beznea@microchip.com wrote: >> Hi Daniel, >> >> Taking into account the discussion on this tread and the fact that we have >> no answer from Rob on this topic (I'm talking about [1]), what do you think >> it would be best for this driver to be accepted the soonest? Would it be OK >> for you to mimic the approach done by: >> >> drivers/clocksource/timer-integrator-ap.c >> >> with the following bindings in DT: >> >> aliases { >> arm,timer-primary = &timer2; >> arm,timer-secondary = &timer1; >> }; >> >> also in PIT64B driver? >> >> Or do you think re-spinning the Alexandre's patches at [2] (which seems to >> me like the generic way to do it) would be better? > > This hardware / OS connection problem is getting really annoying for > everyone and this pattern is repeating itself since several years. It is > time we fix it properly. > > The first solution looks hackish from my POV. The second approach looks > nicer and generic as you say. So I would vote for [2] > flagging approach proposed by Mark [3]. With this flagging approach this would mean a kind unification of clocksource and clockevent functionalities under a single one, right? So that the driver would register to the above layers only one device w/ 2 functionalities (clocksource and clockevent)? Please correct me if I'm wrong? If so, from my point of view this would require major re-working of clocksource and clockevent subsystems. Correctly if I wrongly understood, please. At the moment we register different functionalities (clocksource and clockevent) to the above layers for hardware blocks (e.g. with clocksource_register_hz() or clockevents_config_and_register()). If hardware can support clocksource and clockevent we register both these functionalities, if only one is supported we register only one of these. The above layers would choose the best clocksource/clockevent device from the available ones based on rating field for each clocksource/clockevent we register. In all this current behavior I don't see how these flags would interact with clocksource/clockevent subsystem. Could you please let me know how do you see these and the way these new flags would interact with the layers above the drivers? Thank you, Claudiu Beznea > > I added Arnd in Cc in order to have its opinion. > > [3] > https://lore.kernel.org/lkml/20171215113242.skmh5nzr7wqdmvnw@lakrids.cambridge.arm.com/ > >> [1] >> https://lore.kernel.org/lkml/20190408151155.20279-1-alexandre.belloni@bootlin.com/#t >> [2] >> https://lore.kernel.org/lkml/20171213185313.20017-1-alexandre.belloni@free-electrons.com/ >> > > > > > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.7 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1752BC31E45 for ; Thu, 13 Jun 2019 14:13:14 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DE09C20B7C for ; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Daniel, On 31.05.2019 13:41, Daniel Lezcano wrote: > > Hi Claudiu, > > > On 30/05/2019 09:46, Claudiu.Beznea@microchip.com wrote: >> Hi Daniel, >> >> Taking into account the discussion on this tread and the fact that we have >> no answer from Rob on this topic (I'm talking about [1]), what do you think >> it would be best for this driver to be accepted the soonest? Would it be OK >> for you to mimic the approach done by: >> >> drivers/clocksource/timer-integrator-ap.c >> >> with the following bindings in DT: >> >> aliases { >> arm,timer-primary = &timer2; >> arm,timer-secondary = &timer1; >> }; >> >> also in PIT64B driver? >> >> Or do you think re-spinning the Alexandre's patches at [2] (which seems to >> me like the generic way to do it) would be better? > > This hardware / OS connection problem is getting really annoying for > everyone and this pattern is repeating itself since several years. It is > time we fix it properly. > > The first solution looks hackish from my POV. The second approach looks > nicer and generic as you say. So I would vote for [2] > flagging approach proposed by Mark [3]. With this flagging approach this would mean a kind unification of clocksource and clockevent functionalities under a single one, right? So that the driver would register to the above layers only one device w/ 2 functionalities (clocksource and clockevent)? Please correct me if I'm wrong? If so, from my point of view this would require major re-working of clocksource and clockevent subsystems. Correctly if I wrongly understood, please. At the moment we register different functionalities (clocksource and clockevent) to the above layers for hardware blocks (e.g. with clocksource_register_hz() or clockevents_config_and_register()). If hardware can support clocksource and clockevent we register both these functionalities, if only one is supported we register only one of these. The above layers would choose the best clocksource/clockevent device from the available ones based on rating field for each clocksource/clockevent we register. In all this current behavior I don't see how these flags would interact with clocksource/clockevent subsystem. Could you please let me know how do you see these and the way these new flags would interact with the layers above the drivers? Thank you, Claudiu Beznea > > I added Arnd in Cc in order to have its opinion. > > [3] > https://lore.kernel.org/lkml/20171215113242.skmh5nzr7wqdmvnw@lakrids.cambridge.arm.com/ > >> [1] >> https://lore.kernel.org/lkml/20190408151155.20279-1-alexandre.belloni@bootlin.com/#t >> [2] >> https://lore.kernel.org/lkml/20171213185313.20017-1-alexandre.belloni@free-electrons.com/ >> > > > > > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel