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diff for duplicates of <5e7e155483dfbf590be9b05e53ae954dced73253.1424849129.git.horms+renesas@verge.net.au>

diff --git a/a/1.txt b/N1/1.txt
index 932576e..aaf76ea 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -23,8 +23,8 @@ index 63b918b..fff9497 100644
  					     "lb", "qspi", "sdh", "sd0", "z";
  		};
  		/* Variable factor clocks */
--		sd1_clk: sd2_clk@e6150078 {
-+		sd2_clk: sd2_clk@e6150078 {
+-		sd1_clk: sd2_clk at e6150078 {
++		sd2_clk: sd2_clk at e6150078 {
  			compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
  			reg = <0 0xe6150078 0 4>;
  			clocks = <&pll1_div2_clk>;
@@ -32,8 +32,8 @@ index 63b918b..fff9497 100644
 -			clock-output-names = "sd1";
 +			clock-output-names = "sd2";
  		};
--		sd2_clk: sd3_clk@e615007c {
-+		sd3_clk: sd3_clk@e615026c {
+-		sd2_clk: sd3_clk at e615007c {
++		sd3_clk: sd3_clk at e615026c {
  			compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
 -			reg = <0 0xe615007c 0 4>;
 +			reg = <0 0xe615026c 0 4>;
@@ -42,10 +42,10 @@ index 63b918b..fff9497 100644
 -			clock-output-names = "sd2";
 +			clock-output-names = "sd3";
  		};
- 		mmc0_clk: mmc0_clk@e6150240 {
+ 		mmc0_clk: mmc0_clk at e6150240 {
  			compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
 @@ -589,7 +589,7 @@
- 		mstp3_clks: mstp3_clks@e615013c {
+ 		mstp3_clks: mstp3_clks at e615013c {
  			compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
  			reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 -			clocks = <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
diff --git a/a/content_digest b/N1/content_digest
index 1e88420..f5ed78c 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -2,13 +2,13 @@
   "ref\0cover.1424849129.git.horms+renesas\@verge.net.au\0"
 ]
 [
-  "From\0Simon Horman <horms+renesas\@verge.net.au>\0"
+  "From\0horms+renesas\@verge.net.au (Simon Horman)\0"
 ]
 [
   "Subject\0[PATCH 18/32] ARM: shmobile: r8a7794: Correct SDHI clock base address, labels and output-names\0"
 ]
 [
-  "Date\0Thu, 26 Feb 2015 06:21:15 +0000\0"
+  "Date\0Thu, 26 Feb 2015 15:21:15 +0900\0"
 ]
 [
   "To\0linux-arm-kernel\@lists.infradead.org\0"
@@ -45,8 +45,8 @@
   " \t\t\t\t\t     \"lb\", \"qspi\", \"sdh\", \"sd0\", \"z\";\n",
   " \t\t};\n",
   " \t\t/* Variable factor clocks */\n",
-  "-\t\tsd1_clk: sd2_clk\@e6150078 {\n",
-  "+\t\tsd2_clk: sd2_clk\@e6150078 {\n",
+  "-\t\tsd1_clk: sd2_clk at e6150078 {\n",
+  "+\t\tsd2_clk: sd2_clk at e6150078 {\n",
   " \t\t\tcompatible = \"renesas,r8a7794-div6-clock\", \"renesas,cpg-div6-clock\";\n",
   " \t\t\treg = <0 0xe6150078 0 4>;\n",
   " \t\t\tclocks = <&pll1_div2_clk>;\n",
@@ -54,8 +54,8 @@
   "-\t\t\tclock-output-names = \"sd1\";\n",
   "+\t\t\tclock-output-names = \"sd2\";\n",
   " \t\t};\n",
-  "-\t\tsd2_clk: sd3_clk\@e615007c {\n",
-  "+\t\tsd3_clk: sd3_clk\@e615026c {\n",
+  "-\t\tsd2_clk: sd3_clk at e615007c {\n",
+  "+\t\tsd3_clk: sd3_clk at e615026c {\n",
   " \t\t\tcompatible = \"renesas,r8a7794-div6-clock\", \"renesas,cpg-div6-clock\";\n",
   "-\t\t\treg = <0 0xe615007c 0 4>;\n",
   "+\t\t\treg = <0 0xe615026c 0 4>;\n",
@@ -64,10 +64,10 @@
   "-\t\t\tclock-output-names = \"sd2\";\n",
   "+\t\t\tclock-output-names = \"sd3\";\n",
   " \t\t};\n",
-  " \t\tmmc0_clk: mmc0_clk\@e6150240 {\n",
+  " \t\tmmc0_clk: mmc0_clk at e6150240 {\n",
   " \t\t\tcompatible = \"renesas,r8a7794-div6-clock\", \"renesas,cpg-div6-clock\";\n",
   "\@\@ -589,7 +589,7 \@\@\n",
-  " \t\tmstp3_clks: mstp3_clks\@e615013c {\n",
+  " \t\tmstp3_clks: mstp3_clks at e615013c {\n",
   " \t\t\tcompatible = \"renesas,r8a7794-mstp-clocks\", \"renesas,cpg-mstp-clocks\";\n",
   " \t\t\treg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;\n",
   "-\t\t\tclocks = <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7794_CLK_SD0>,\n",
@@ -79,4 +79,4 @@
   "2.1.4"
 ]
 
-3f8637475dc6e3bf4b804f22aa747f7a9676ba4016e7a8ce7e15379c4f391e55
+fea0612ece69cbfd010c6c9f9e16454bd706720d94eb80011db30c3da2072661
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