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[84.118.157.2]) by smtp.gmail.com with ESMTPSA id k5-20020a05600c1c8500b003a5f3de6fddsm6392341wms.25.2022.08.25.11.36.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 25 Aug 2022 11:36:51 -0700 (PDT) Message-ID: <5f00ab85-d5ac-728d-2157-e70f2a46cc90@canonical.com> Date: Thu, 25 Aug 2022 20:36:49 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.2.0 Subject: Re: [PATCH 1/2] dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible To: Conor Dooley Cc: Sagar Kadam , Atish Patra , Paul Walmsley , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Albert Ou , Daire McNamara , Palmer Dabbelt , Rob Herring , Conor Dooley References: <20220825180417.1259360-1-mail@conchuod.ie> <20220825180417.1259360-2-mail@conchuod.ie> Content-Language: en-US From: Heinrich Schuchardt In-Reply-To: <20220825180417.1259360-2-mail@conchuod.ie> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 8/25/22 20:04, Conor Dooley wrote: > From: Conor Dooley > > The l2 cache on PolarFire SoC is cross between that of the fu540 and > the fu740. It has the extra interrupt from the fu740 but the lower > number of cache-sets. Add a specific compatible to avoid the likes > of: > > mpfs-polarberry.dtb: cache-controller@2010000: interrupts: [[1], [3], [4], [2]] is too long Where is such a message written? I couldn't find the string in next-20220825 (git grep -n 'is too long"'). Why should a different number of cache sets require an extra compatible string. cache-size is simply a parameter going with the existing compatible strings. I would assume that you only need an extra compatible string if there is a functional difference that can not be expressed with the existing parameters. > > Fixes: 34fc9cc3aebe ("riscv: dts: microchip: correct L2 cache interrupts") > Signed-off-by: Conor Dooley > --- > .../bindings/riscv/sifive-l2-cache.yaml | 79 ++++++++++++------- > 1 file changed, 49 insertions(+), 30 deletions(-) > > diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > index 69cdab18d629..ca3b9be58058 100644 > --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > @@ -17,9 +17,6 @@ description: > acts as directory-based coherency manager. > All the properties in ePAPR/DeviceTree specification applies for this platform. > > -allOf: > - - $ref: /schemas/cache-controller.yaml# > - > select: > properties: > compatible: > @@ -33,11 +30,16 @@ select: > > properties: > compatible: > - items: > - - enum: > - - sifive,fu540-c000-ccache > - - sifive,fu740-c000-ccache Why can't you simply add microchip,mpfs-ccache here? > - - const: cache > + oneOf: > + - items: > + - enum: > + - sifive,fu540-c000-ccache > + - sifive,fu740-c000-ccache > + - const: cache > + - items: > + - const: microchip,mpfs-ccache > + - const: sifive,fu540-c000-ccache Why do we need 'sifive,fu540-c000-ccache' twice? Best regards Heinrich > + - const: cache > > cache-block-size: > const: 64 > @@ -72,29 +74,46 @@ properties: > The reference to the reserved-memory for the L2 Loosely Integrated Memory region. > The reserved memory node should be defined as per the bindings in reserved-memory.txt. > > -if: > - properties: > - compatible: > - contains: > - const: sifive,fu540-c000-ccache > +allOf: > + - $ref: /schemas/cache-controller.yaml# > > -then: > - properties: > - interrupts: > - description: | > - Must contain entries for DirError, DataError and DataFail signals. > - maxItems: 3 > - cache-sets: > - const: 1024 > - > -else: > - properties: > - interrupts: > - description: | > - Must contain entries for DirError, DataError, DataFail, DirFail signals. > - minItems: 4 > - cache-sets: > - const: 2048 > + - if: > + properties: > + compatible: > + contains: > + enum: > + - sifive,fu740-c000-ccache > + - microchip,mpfs-ccache > + > + then: > + properties: > + interrupts: > + description: | > + Must contain entries for DirError, DataError, DataFail, DirFail signals. > + minItems: 4 > + > + else: > + properties: > + interrupts: > + description: | > + Must contain entries for DirError, DataError and DataFail signals. > + maxItems: 3 > + > + - if: > + properties: > + compatible: > + contains: > + const: sifive,fu740-c000-ccache > + > + then: > + properties: > + cache-sets: > + const: 2048 > + > + else: > + properties: > + cache-sets: > + const: 1024 > > additionalProperties: false > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C87D4ECAA24 for ; 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[84.118.157.2]) by smtp.gmail.com with ESMTPSA id k5-20020a05600c1c8500b003a5f3de6fddsm6392341wms.25.2022.08.25.11.36.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 25 Aug 2022 11:36:51 -0700 (PDT) Message-ID: <5f00ab85-d5ac-728d-2157-e70f2a46cc90@canonical.com> Date: Thu, 25 Aug 2022 20:36:49 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.2.0 Subject: Re: [PATCH 1/2] dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible To: Conor Dooley Cc: Sagar Kadam , Atish Patra , Paul Walmsley , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Albert Ou , Daire McNamara , Palmer Dabbelt , Rob Herring , Conor Dooley References: <20220825180417.1259360-1-mail@conchuod.ie> <20220825180417.1259360-2-mail@conchuod.ie> Content-Language: en-US From: Heinrich Schuchardt In-Reply-To: <20220825180417.1259360-2-mail@conchuod.ie> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220825_113703_112062_5BB6CFF1 X-CRM114-Status: GOOD ( 20.87 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 8/25/22 20:04, Conor Dooley wrote: > From: Conor Dooley > > The l2 cache on PolarFire SoC is cross between that of the fu540 and > the fu740. It has the extra interrupt from the fu740 but the lower > number of cache-sets. Add a specific compatible to avoid the likes > of: > > mpfs-polarberry.dtb: cache-controller@2010000: interrupts: [[1], [3], [4], [2]] is too long Where is such a message written? I couldn't find the string in next-20220825 (git grep -n 'is too long"'). Why should a different number of cache sets require an extra compatible string. cache-size is simply a parameter going with the existing compatible strings. I would assume that you only need an extra compatible string if there is a functional difference that can not be expressed with the existing parameters. > > Fixes: 34fc9cc3aebe ("riscv: dts: microchip: correct L2 cache interrupts") > Signed-off-by: Conor Dooley > --- > .../bindings/riscv/sifive-l2-cache.yaml | 79 ++++++++++++------- > 1 file changed, 49 insertions(+), 30 deletions(-) > > diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > index 69cdab18d629..ca3b9be58058 100644 > --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > @@ -17,9 +17,6 @@ description: > acts as directory-based coherency manager. > All the properties in ePAPR/DeviceTree specification applies for this platform. > > -allOf: > - - $ref: /schemas/cache-controller.yaml# > - > select: > properties: > compatible: > @@ -33,11 +30,16 @@ select: > > properties: > compatible: > - items: > - - enum: > - - sifive,fu540-c000-ccache > - - sifive,fu740-c000-ccache Why can't you simply add microchip,mpfs-ccache here? > - - const: cache > + oneOf: > + - items: > + - enum: > + - sifive,fu540-c000-ccache > + - sifive,fu740-c000-ccache > + - const: cache > + - items: > + - const: microchip,mpfs-ccache > + - const: sifive,fu540-c000-ccache Why do we need 'sifive,fu540-c000-ccache' twice? Best regards Heinrich > + - const: cache > > cache-block-size: > const: 64 > @@ -72,29 +74,46 @@ properties: > The reference to the reserved-memory for the L2 Loosely Integrated Memory region. > The reserved memory node should be defined as per the bindings in reserved-memory.txt. > > -if: > - properties: > - compatible: > - contains: > - const: sifive,fu540-c000-ccache > +allOf: > + - $ref: /schemas/cache-controller.yaml# > > -then: > - properties: > - interrupts: > - description: | > - Must contain entries for DirError, DataError and DataFail signals. > - maxItems: 3 > - cache-sets: > - const: 1024 > - > -else: > - properties: > - interrupts: > - description: | > - Must contain entries for DirError, DataError, DataFail, DirFail signals. > - minItems: 4 > - cache-sets: > - const: 2048 > + - if: > + properties: > + compatible: > + contains: > + enum: > + - sifive,fu740-c000-ccache > + - microchip,mpfs-ccache > + > + then: > + properties: > + interrupts: > + description: | > + Must contain entries for DirError, DataError, DataFail, DirFail signals. > + minItems: 4 > + > + else: > + properties: > + interrupts: > + description: | > + Must contain entries for DirError, DataError and DataFail signals. > + maxItems: 3 > + > + - if: > + properties: > + compatible: > + contains: > + const: sifive,fu740-c000-ccache > + > + then: > + properties: > + cache-sets: > + const: 2048 > + > + else: > + properties: > + cache-sets: > + const: 1024 > > additionalProperties: false > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv