From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B980C433F5 for ; Sat, 16 Apr 2022 10:37:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231468AbiDPKkO (ORCPT ); Sat, 16 Apr 2022 06:40:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37906 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231469AbiDPKkK (ORCPT ); Sat, 16 Apr 2022 06:40:10 -0400 Received: from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7FDF5381BE for ; Sat, 16 Apr 2022 03:37:35 -0700 (PDT) Received: from kwepemi500022.china.huawei.com (unknown [172.30.72.56]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4KgV4P67M3z1HBb7; Sat, 16 Apr 2022 18:36:53 +0800 (CST) Received: from kwepemm600016.china.huawei.com (7.193.23.20) by kwepemi500022.china.huawei.com (7.221.188.64) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Sat, 16 Apr 2022 18:37:33 +0800 Received: from [10.67.102.67] (10.67.102.67) by kwepemm600016.china.huawei.com (7.193.23.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Sat, 16 Apr 2022 18:37:32 +0800 Subject: Re: [PATCH V3 2/2] drivers/perf: hisi: add driver for HNS3 PMU To: John Garry , "will@kernel.org" , "mark.rutland@arm.com" CC: "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Linuxarm , "liuqi (BA)" , Zhangshaokun , "Fangjian (Jay)" , "lipeng (Y)" , "shenjian (K)" , moyufeng References: <20220329113930.37631-1-huangguangbin2@huawei.com> <20220329113930.37631-3-huangguangbin2@huawei.com> <2a66d1d7-cf85-1ce0-1adf-f72a27243fe1@huawei.com> From: "huangguangbin (A)" Message-ID: <5f23529e-0ddf-57bf-9bc3-5246fbec92c2@huawei.com> Date: Sat, 16 Apr 2022 18:37:32 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <2a66d1d7-cf85-1ce0-1adf-f72a27243fe1@huawei.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.67.102.67] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To kwepemm600016.china.huawei.com (7.193.23.20) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2022/4/14 19:45, John Garry wrote: > On 29/03/2022 12:39, Guangbin Huang wrote: >> HNS3(HiSilicon Network System 3) PMU is RCiEP device in HiSilicon SoC NIC, >> supports collection of performance statistics such as bandwidth, latency, >> packet rate and interrupt rate. >> >> NIC of each SICL has one PMU device for it. Driver registers each PMU >> device to perf, and exports information of supported events, filter mode of >> each event, bdf range, hardware clock frequency, identifier and so on via >> sysfs. >> >> Each PMU device has its own registers of control, counters and interrupt, >> and it supports 8 hardware events, each hardward event has its own >> registers for configuration, counters and interrupt. >> >> Filter options contains: >> config       - select event >> port         - select physical port of nic >> tc           - select tc(must be used with port) >> func         - select PF/VF >> queue        - select queue of PF/VF(must be used with func) >> intr         - select interrupt number(must be used with func) >> global       - select all functions of IO DIE >> > > Generally looks ok, Just a few more comments. > >> Signed-off-by: Guangbin Huang >> --- >>   MAINTAINERS                       |    6 + >>   drivers/perf/hisilicon/Kconfig    |   10 + >>   drivers/perf/hisilicon/Makefile   |    1 + >>   drivers/perf/hisilicon/hns3_pmu.c | 1640 +++++++++++++++++++++++++++++ >>   include/linux/cpuhotplug.h        |    1 + >>   5 files changed, 1658 insertions(+) >>   create mode 100644 drivers/perf/hisilicon/hns3_pmu.c >> >> diff --git a/MAINTAINERS b/MAINTAINERS >> index 69a2935daf6c..34b87348503a 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -8691,6 +8691,12 @@ F:    Documentation/admin-guide/perf/hisi-pcie-pmu.rst >>   F:    Documentation/admin-guide/perf/hisi-pmu.rst >>   F:    drivers/perf/hisilicon >> +HISILICON HNS3 PMU DRIVER >> +M:    Guangbin Huang >> +S:    Supported >> +F:    Documentation/admin-guide/perf/hns3-pmu.rst >> +F:    drivers/perf/hisilicon/hns3_pmu.c >> + >>   HISILICON QM AND ZIP Controller DRIVER >>   M:    Zhou Wang >>   L:    linux-crypto@vger.kernel.org >> diff --git a/drivers/perf/hisilicon/Kconfig b/drivers/perf/hisilicon/Kconfig >> index 5546218b5598..171bfc1b6bc2 100644 >> --- a/drivers/perf/hisilicon/Kconfig >> +++ b/drivers/perf/hisilicon/Kconfig >> @@ -14,3 +14,13 @@ config HISI_PCIE_PMU >>         RCiEP devices. >>         Adds the PCIe PMU into perf events system for monitoring latency, >>         bandwidth etc. >> + >> +config HNS3_PMU >> +    tristate "HNS3 PERF PMU" >> +    depends on ARM64 || COMPILE_TEST > > is see hns3_pmu_readq() below, so you need to ensure the arch supports readq - so I think that you need to depend on 64b. I assume that you never built this for a 32b arch > Our CPU arch is just arm64, so I set it to depend on ARM64. Yeah, I never built this for a 32b arch because we would never run this driver on 32b CPU. Are you mean that hns3_pmu_readq() will be compiled failed for 32b arch? So I think that I need to delete COMPILE_TEST to prevent from this case. >> +    depends on PCI >> +    help >> +      Provide support for HNS3 performance monitoring unit (PMU) RCiEP >> +      devices. >> +      Adds the HNS3 PMU into perf events system for monitoring latency, >> +      bandwidth etc. >> diff --git a/drivers/perf/hisilicon/Makefile b/drivers/perf/hisilicon/Makefile >> index 506ed39e3266..13297ec2798f 100644 >> --- a/drivers/perf/hisilicon/Makefile >> +++ b/drivers/perf/hisilicon/Makefile >> @@ -4,3 +4,4 @@ obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o hisi_uncore_l3c_pmu.o \ >>                 hisi_uncore_pa_pmu.o >>   obj-$(CONFIG_HISI_PCIE_PMU) += hisi_pcie_pmu.o >> +obj-$(CONFIG_HNS3_PMU) += hns3_pmu.o >> diff --git a/drivers/perf/hisilicon/hns3_pmu.c b/drivers/perf/hisilicon/hns3_pmu.c >> new file mode 100644 >> index 000000000000..2ecd8f299a86 >> --- /dev/null >> +++ b/drivers/perf/hisilicon/hns3_pmu.c >> @@ -0,0 +1,1640 @@ >> +// SPDX-License-Identifier: GPL-2.0-only >> +/* >> + * This driver adds support for HNS3 PMU iEP device. Related perf events are >> + * bandwidth, latency, packet rate, interrupt rate etc. >> + * >> + * Copyright (C) 2022 HiSilicon Limited >> + */ >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +/* registers offset address */ >> +#define HNS3_PMU_REG_GLOBAL_CTRL        0x0000 >> +#define HNS3_PMU_REG_CLOCK_FREQ            0x0020 >> +#define HNS3_PMU_REG_BDF            0x0fe0 >> +#define HNS3_PMU_REG_VERSION            0x0fe4 >> +#define HNS3_PMU_REG_DEVICE_ID            0x0fe8 >> + >> +#define HNS3_PMU_REG_EVENT_OFFSET        0x1000 >> +#define HNS3_PMU_REG_EVENT_SIZE            0x1000 >> +#define HNS3_PMU_REG_EVENT_CTRL_LOW        0x00 >> +#define HNS3_PMU_REG_EVENT_CTRL_HIGH        0x04 >> +#define HNS3_PMU_REG_EVENT_INTR_STATUS        0x08 >> +#define HNS3_PMU_REG_EVENT_INTR_MASK        0x0c >> +#define HNS3_PMU_REG_EVENT_COUNTER        0x10 >> +#define HNS3_PMU_REG_EVENT_EXT_COUNTER        0x18 >> +#define HNS3_PMU_REG_EVENT_QID_CTRL        0x28 >> +#define HNS3_PMU_REG_EVENT_QID_PARA        0x2c >> + >> +#define HNS3_PMU_FILTER_SUPPORT_GLOBAL        BIT(0) >> +#define HNS3_PMU_FILTER_SUPPORT_PORT        BIT(1) >> +#define HNS3_PMU_FILTER_SUPPORT_PORT_TC        BIT(2) >> +#define HNS3_PMU_FILTER_SUPPORT_FUNC        BIT(3) >> +#define HNS3_PMU_FILTER_SUPPORT_FUNC_QUEUE    BIT(4) >> +#define HNS3_PMU_FILTER_SUPPORT_FUNC_INTR    BIT(5) >> + >> +#define HNS3_PMU_FILTER_ALL_TC            0xf >> +#define HNS3_PMU_FILTER_ALL_QUEUE        0xffff >> + >> +#define HNS3_PMU_CTRL_SUBEVENT_S        4 >> +#define HNS3_PMU_CTRL_FILTER_MODE_S        24 >> + >> +#define HNS3_PMU_GLOBAL_START            BIT(0) >> + >> +#define HNS3_PMU_EVENT_STATUS_RESET        BIT(11) >> +#define HNS3_PMU_EVENT_EN            BIT(12) >> +#define HNS3_PMU_EVENT_OVERFLOW_RESTART        BIT(15) >> + >> +#define HNS3_PMU_QID_PARA_FUNC_S        0 >> +#define HNS3_PMU_QID_PARA_QUEUE_S        16 >> + >> +#define HNS3_PMU_QID_CTRL_REQ_ENABLE        BIT(0) >> +#define HNS3_PMU_QID_CTRL_DONE            BIT(1) >> +#define HNS3_PMU_QID_CTRL_MISS            BIT(2) >> + >> +#define HNS3_PMU_INTR_MASK_OVERFLOW        BIT(1) >> + >> +#define HNS3_PMU_MAX_HW_EVENTS            8 >> + >> +/* >> + * Each hardware event contains two registers (counter and ext_counter) for >> + * bandwidth, packet rate, latency and interrupt rate. These two registers will >> + * be triggered to run at the same when a hardware event is enabled. >> + * >> + * Performance of each hardware event is calculated by: counter / ext_counter. >> + * >> + * As process of performance data is not recommended put in driver, we expose > > /s/As process of performance data is not recommended put in driver/Since processing of data is preferred to be done in userspace/ > Ok. >> + * ext_counter as a separate event for userspace and use bit 16 to indicate it. >> + * For example, event 0x00001 and 0x10001 are actually one event for hardware >> + * because bit 0-15 are same. If the bit 16 of one event is 0 means to get >> + * counter, otherwise means to get ext_counter. > > > I am not sure what you mean by "get ext_counter" or "get counter" - please make this a bit more clear > Ok. >> + */ >> +/* bandwidth events */ >> +#define HNS3_PMU_EVT_BW_SSU_EGU_BYTE_NUM        0x00001 >> +#define HNS3_PMU_EVT_BW_SSU_EGU_TIME            0x10001 >> +#define HNS3_PMU_EVT_BW_SSU_RPU_BYTE_NUM        0x00002 >> +#define HNS3_PMU_EVT_BW_SSU_RPU_TIME            0x10002 >> +#define HNS3_PMU_EVT_BW_SSU_ROCE_BYTE_NUM        0x00003 >> +#define HNS3_PMU_EVT_BW_SSU_ROCE_TIME            0x10003 >> +#define HNS3_PMU_EVT_BW_ROCE_SSU_BYTE_NUM        0x00004 >> +#define HNS3_PMU_EVT_BW_ROCE_SSU_TIME            0x10004 >> +#define HNS3_PMU_EVT_BW_TPU_SSU_BYTE_NUM        0x00005 >> +#define HNS3_PMU_EVT_BW_TPU_SSU_TIME            0x10005 >> +#define HNS3_PMU_EVT_BW_RPU_RCBRX_BYTE_NUM        0x00006 >> +#define HNS3_PMU_EVT_BW_RPU_RCBRX_TIME            0x10006 >> +#define HNS3_PMU_EVT_BW_RCBTX_TXSCH_BYTE_NUM        0x00008 >> +#define HNS3_PMU_EVT_BW_RCBTX_TXSCH_TIME        0x10008 >> +#define HNS3_PMU_EVT_BW_WR_FBD_BYTE_NUM            0x00009 >> +#define HNS3_PMU_EVT_BW_WR_FBD_TIME            0x10009 >> +#define HNS3_PMU_EVT_BW_WR_EBD_BYTE_NUM            0x0000a >> +#define HNS3_PMU_EVT_BW_WR_EBD_TIME            0x1000a >> +#define HNS3_PMU_EVT_BW_RD_FBD_BYTE_NUM            0x0000b >> +#define HNS3_PMU_EVT_BW_RD_FBD_TIME            0x1000b >> +#define HNS3_PMU_EVT_BW_RD_EBD_BYTE_NUM            0x0000c >> +#define HNS3_PMU_EVT_BW_RD_EBD_TIME            0x1000c >> +#define HNS3_PMU_EVT_BW_RD_PAY_M0_BYTE_NUM        0x0000d >> +#define HNS3_PMU_EVT_BW_RD_PAY_M0_TIME            0x1000d >> +#define HNS3_PMU_EVT_BW_RD_PAY_M1_BYTE_NUM        0x0000e >> +#define HNS3_PMU_EVT_BW_RD_PAY_M1_TIME            0x1000e >> +#define HNS3_PMU_EVT_BW_WR_PAY_M0_BYTE_NUM        0x0000f >> +#define HNS3_PMU_EVT_BW_WR_PAY_M0_TIME            0x1000f >> +#define HNS3_PMU_EVT_BW_WR_PAY_M1_BYTE_NUM        0x00010 >> +#define HNS3_PMU_EVT_BW_WR_PAY_M1_TIME            0x10010 >> + >> +/* packet rate events */ >> +#define HNS3_PMU_EVT_PPS_IGU_SSU_PACKET_NUM        0x00100 >> +#define HNS3_PMU_EVT_PPS_IGU_SSU_TIME            0x10100 >> +#define HNS3_PMU_EVT_PPS_SSU_EGU_PACKET_NUM        0x00101 >> +#define HNS3_PMU_EVT_PPS_SSU_EGU_TIME            0x10101 >> +#define HNS3_PMU_EVT_PPS_SSU_RPU_PACKET_NUM        0x00102 >> +#define HNS3_PMU_EVT_PPS_SSU_RPU_TIME            0x10102 >> +#define HNS3_PMU_EVT_PPS_SSU_ROCE_PACKET_NUM        0x00103 >> +#define HNS3_PMU_EVT_PPS_SSU_ROCE_TIME            0x10103 >> +#define HNS3_PMU_EVT_PPS_ROCE_SSU_PACKET_NUM        0x00104 >> +#define HNS3_PMU_EVT_PPS_ROCE_SSU_TIME            0x10104 >> +#define HNS3_PMU_EVT_PPS_TPU_SSU_PACKET_NUM        0x00105 >> +#define HNS3_PMU_EVT_PPS_TPU_SSU_TIME            0x10105 >> +#define HNS3_PMU_EVT_PPS_RPU_RCBRX_PACKET_NUM        0x00106 >> +#define HNS3_PMU_EVT_PPS_RPU_RCBRX_TIME            0x10106 >> +#define HNS3_PMU_EVT_PPS_RCBTX_TPU_PACKET_NUM        0x00107 >> +#define HNS3_PMU_EVT_PPS_RCBTX_TPU_TIME            0x10107 >> +#define HNS3_PMU_EVT_PPS_RCBTX_TXSCH_PACKET_NUM        0x00108 >> +#define HNS3_PMU_EVT_PPS_RCBTX_TXSCH_TIME        0x10108 >> +#define HNS3_PMU_EVT_PPS_WR_FBD_PACKET_NUM        0x00109 >> +#define HNS3_PMU_EVT_PPS_WR_FBD_TIME            0x10109 >> +#define HNS3_PMU_EVT_PPS_WR_EBD_PACKET_NUM        0x0010a >> +#define HNS3_PMU_EVT_PPS_WR_EBD_TIME            0x1010a >> +#define HNS3_PMU_EVT_PPS_RD_FBD_PACKET_NUM        0x0010b >> +#define HNS3_PMU_EVT_PPS_RD_FBD_TIME            0x1010b >> +#define HNS3_PMU_EVT_PPS_RD_EBD_PACKET_NUM        0x0010c >> +#define HNS3_PMU_EVT_PPS_RD_EBD_TIME            0x1010c >> +#define HNS3_PMU_EVT_PPS_RD_PAY_M0_PACKET_NUM        0x0010d >> +#define HNS3_PMU_EVT_PPS_RD_PAY_M0_TIME            0x1010d >> +#define HNS3_PMU_EVT_PPS_RD_PAY_M1_PACKET_NUM        0x0010e >> +#define HNS3_PMU_EVT_PPS_RD_PAY_M1_TIME            0x1010e >> +#define HNS3_PMU_EVT_PPS_WR_PAY_M0_PACKET_NUM        0x0010f >> +#define HNS3_PMU_EVT_PPS_WR_PAY_M0_TIME            0x1010f >> +#define HNS3_PMU_EVT_PPS_WR_PAY_M1_PACKET_NUM        0x00110 >> +#define HNS3_PMU_EVT_PPS_WR_PAY_M1_TIME            0x10110 >> +#define HNS3_PMU_EVT_PPS_NICROH_TX_PRE_PACKET_NUM    0x00111 >> +#define HNS3_PMU_EVT_PPS_NICROH_TX_PRE_TIME        0x10111 >> +#define HNS3_PMU_EVT_PPS_NICROH_RX_PRE_PACKET_NUM    0x00112 >> +#define HNS3_PMU_EVT_PPS_NICROH_RX_PRE_TIME        0x10112 >> + >> +/* latency events */ >> +#define HNS3_PMU_EVT_DLY_TX_PUSH_TIME            0x00202 >> +#define HNS3_PMU_EVT_DLY_TX_PUSH_PACKET_NUM        0x10202 >> +#define HNS3_PMU_EVT_DLY_TX_TIME            0x00204 >> +#define HNS3_PMU_EVT_DLY_TX_PACKET_NUM            0x10204 >> +#define HNS3_PMU_EVT_DLY_SSU_TX_NIC_TIME        0x00206 >> +#define HNS3_PMU_EVT_DLY_SSU_TX_NIC_PACKET_NUM        0x10206 >> +#define HNS3_PMU_EVT_DLY_SSU_TX_ROCE_TIME        0x00207 >> +#define HNS3_PMU_EVT_DLY_SSU_TX_ROCE_PACKET_NUM        0x10207 >> +#define HNS3_PMU_EVT_DLY_SSU_RX_NIC_TIME        0x00208 >> +#define HNS3_PMU_EVT_DLY_SSU_RX_NIC_PACKET_NUM        0x10208 >> +#define HNS3_PMU_EVT_DLY_SSU_RX_ROCE_TIME        0x00209 >> +#define HNS3_PMU_EVT_DLY_SSU_RX_ROCE_PACKET_NUM        0x10209 >> +#define HNS3_PMU_EVT_DLY_RPU_TIME            0x0020e >> +#define HNS3_PMU_EVT_DLY_RPU_PACKET_NUM            0x1020e >> +#define HNS3_PMU_EVT_DLY_TPU_TIME            0x0020f >> +#define HNS3_PMU_EVT_DLY_TPU_PACKET_NUM            0x1020f >> +#define HNS3_PMU_EVT_DLY_RPE_TIME            0x00210 >> +#define HNS3_PMU_EVT_DLY_RPE_PACKET_NUM            0x10210 >> +#define HNS3_PMU_EVT_DLY_TPE_TIME            0x00211 >> +#define HNS3_PMU_EVT_DLY_TPE_PACKET_NUM            0x10211 >> +#define HNS3_PMU_EVT_DLY_TPE_PUSH_TIME            0x00212 >> +#define HNS3_PMU_EVT_DLY_TPE_PUSH_PACKET_NUM        0x10212 >> +#define HNS3_PMU_EVT_DLY_WR_FBD_TIME            0x00213 >> +#define HNS3_PMU_EVT_DLY_WR_FBD_PACKET_NUM        0x10213 >> +#define HNS3_PMU_EVT_DLY_WR_EBD_TIME            0x00214 >> +#define HNS3_PMU_EVT_DLY_WR_EBD_PACKET_NUM        0x10214 >> +#define HNS3_PMU_EVT_DLY_RD_FBD_TIME            0x00215 >> +#define HNS3_PMU_EVT_DLY_RD_FBD_PACKET_NUM        0x10215 >> +#define HNS3_PMU_EVT_DLY_RD_EBD_TIME            0x00216 >> +#define HNS3_PMU_EVT_DLY_RD_EBD_PACKET_NUM        0x10216 >> +#define HNS3_PMU_EVT_DLY_RD_PAY_M0_TIME            0x00217 >> +#define HNS3_PMU_EVT_DLY_RD_PAY_M0_PACKET_NUM        0x10217 >> +#define HNS3_PMU_EVT_DLY_RD_PAY_M1_TIME            0x00218 >> +#define HNS3_PMU_EVT_DLY_RD_PAY_M1_PACKET_NUM        0x10218 >> +#define HNS3_PMU_EVT_DLY_WR_PAY_M0_TIME            0x00219 >> +#define HNS3_PMU_EVT_DLY_WR_PAY_M0_PACKET_NUM        0x10219 >> +#define HNS3_PMU_EVT_DLY_WR_PAY_M1_TIME            0x0021a >> +#define HNS3_PMU_EVT_DLY_WR_PAY_M1_PACKET_NUM        0x1021a >> +#define HNS3_PMU_EVT_DLY_MSIX_WRITE_TIME        0x0021c >> +#define HNS3_PMU_EVT_DLY_MSIX_WRITE_PACKET_NUM        0x1021c >> + >> +/* interrupt rate events */ >> +#define HNS3_PMU_EVT_PPS_MSIX_NIC_INTR_NUM        0x00300 >> +#define HNS3_PMU_EVT_PPS_MSIX_NIC_TIME            0x10300 >> + >> +/* filter mode supported by each bandwidth event */ >> +#define HNS3_PMU_FILTER_BW_SSU_EGU        0x07 >> +#define HNS3_PMU_FILTER_BW_SSU_RPU        0x1f >> +#define HNS3_PMU_FILTER_BW_SSU_ROCE        0x0f >> +#define HNS3_PMU_FILTER_BW_ROCE_SSU        0x0f >> +#define HNS3_PMU_FILTER_BW_TPU_SSU        0x1f >> +#define HNS3_PMU_FILTER_BW_RPU_RCBRX        0x11 >> +#define HNS3_PMU_FILTER_BW_RCBTX_TXSCH        0x11 >> +#define HNS3_PMU_FILTER_BW_WR_FBD        0x1b >> +#define HNS3_PMU_FILTER_BW_WR_EBD        0x11 >> +#define HNS3_PMU_FILTER_BW_RD_FBD        0x01 >> +#define HNS3_PMU_FILTER_BW_RD_EBD        0x1b >> +#define HNS3_PMU_FILTER_BW_RD_PAY_M0        0x01 >> +#define HNS3_PMU_FILTER_BW_RD_PAY_M1        0x01 >> +#define HNS3_PMU_FILTER_BW_WR_PAY_M0        0x01 >> +#define HNS3_PMU_FILTER_BW_WR_PAY_M1        0x01 >> + >> +/* filter mode supported by each packet rate event */ >> +#define HNS3_PMU_FILTER_PPS_IGU_SSU        0x07 >> +#define HNS3_PMU_FILTER_PPS_SSU_EGU        0x07 >> +#define HNS3_PMU_FILTER_PPS_SSU_RPU        0x1f >> +#define HNS3_PMU_FILTER_PPS_SSU_ROCE        0x0f >> +#define HNS3_PMU_FILTER_PPS_ROCE_SSU        0x0f >> +#define HNS3_PMU_FILTER_PPS_TPU_SSU        0x1f >> +#define HNS3_PMU_FILTER_PPS_RPU_RCBRX        0x11 >> +#define HNS3_PMU_FILTER_PPS_RCBTX_TPU        0x1f >> +#define HNS3_PMU_FILTER_PPS_RCBTX_TXSCH        0x11 >> +#define HNS3_PMU_FILTER_PPS_WR_FBD        0x1b >> +#define HNS3_PMU_FILTER_PPS_WR_EBD        0x11 >> +#define HNS3_PMU_FILTER_PPS_RD_FBD        0x01 >> +#define HNS3_PMU_FILTER_PPS_RD_EBD        0x1b >> +#define HNS3_PMU_FILTER_PPS_RD_PAY_M0        0x01 >> +#define HNS3_PMU_FILTER_PPS_RD_PAY_M1        0x01 >> +#define HNS3_PMU_FILTER_PPS_WR_PAY_M0        0x01 >> +#define HNS3_PMU_FILTER_PPS_WR_PAY_M1        0x01 >> +#define HNS3_PMU_FILTER_PPS_NICROH_TX_PRE    0x01 >> +#define HNS3_PMU_FILTER_PPS_NICROH_RX_PRE    0x01 >> + >> +/* filter mode supported by each latency event */ >> +#define HNS3_PMU_FILTER_DLY_TX_PUSH        0x01 >> +#define HNS3_PMU_FILTER_DLY_TX            0x01 >> +#define HNS3_PMU_FILTER_DLY_SSU_TX_NIC        0x07 >> +#define HNS3_PMU_FILTER_DLY_SSU_TX_ROCE        0x07 >> +#define HNS3_PMU_FILTER_DLY_SSU_RX_NIC        0x07 >> +#define HNS3_PMU_FILTER_DLY_SSU_RX_ROCE        0x07 >> +#define HNS3_PMU_FILTER_DLY_RPU            0x11 >> +#define HNS3_PMU_FILTER_DLY_TPU            0x1f >> +#define HNS3_PMU_FILTER_DLY_RPE            0x01 >> +#define HNS3_PMU_FILTER_DLY_TPE            0x0b >> +#define HNS3_PMU_FILTER_DLY_TPE_PUSH        0x1b >> +#define HNS3_PMU_FILTER_DLY_WR_FBD        0x1b >> +#define HNS3_PMU_FILTER_DLY_WR_EBD        0x11 >> +#define HNS3_PMU_FILTER_DLY_RD_FBD        0x01 >> +#define HNS3_PMU_FILTER_DLY_RD_EBD        0x1b >> +#define HNS3_PMU_FILTER_DLY_RD_PAY_M0        0x01 >> +#define HNS3_PMU_FILTER_DLY_RD_PAY_M1        0x01 >> +#define HNS3_PMU_FILTER_DLY_WR_PAY_M0        0x01 >> +#define HNS3_PMU_FILTER_DLY_WR_PAY_M1        0x01 >> +#define HNS3_PMU_FILTER_DLY_MSIX_WRITE        0x01 >> + >> +/* filter mode supported by each interrupt rate event */ >> +#define HNS3_PMU_FILTER_INTR_MSIX_NIC        0x01 >> + >> +enum hns3_pmu_hw_filter_mode { >> +    HNS3_PMU_HW_FILTER_GLOBAL, >> +    HNS3_PMU_HW_FILTER_PORT, >> +    HNS3_PMU_HW_FILTER_PORT_TC, >> +    HNS3_PMU_HW_FILTER_FUNC, >> +    HNS3_PMU_HW_FILTER_FUNC_QUEUE, >> +    HNS3_PMU_HW_FILTER_FUNC_INTR, >> +}; >> + >> +struct hns3_pmu_event_attr { >> +    u32 event; >> +    u16 filter_support; >> +}; >> + >> +struct hns3_pmu { >> +    struct perf_event *hw_events[HNS3_PMU_MAX_HW_EVENTS]; >> +    struct hlist_node node; >> +    struct pci_dev *pdev; >> +    struct pmu pmu; >> +    void __iomem *base; >> +    int irq; >> +    int on_cpu; >> +    u32 identifier; >> +    u32 hw_clk_freq; /* hardware clock frequency of PMU */ >> +    /* maximum and minimun bdf allowed by PMU */ >> +    u16 bdf_min; >> +    u16 bdf_max; >> +}; >> + >> +#define to_hns3_pmu(p)  (container_of((p), struct hns3_pmu, pmu)) >> +#define attr_to_dattr(a) (container_of((a), struct device_attribute, attr)) >> +#define dattr_to_eattr(d) (container_of((d), struct dev_ext_attribute, attr)) >> + >> +#define GET_PCI_DEVFN(bdf)  ((bdf) & 0xff) >> + >> +#define FILTER_CONDITION_PORT(port) ((1 << (port)) & 0xff) >> +#define FILTER_CONDITION_PORT_TC(port, tc) (((port) << 3) | ((tc) & 0x07)) >> +#define FILTER_CONDITION_FUNC_INTR(func, intr) (((intr) << 8) | (func)) >> + >> +#define BYTES_TO_BITS(bytes)        ((bytes) * 8) > > not used > Ok, thanks. >> + >> +#define HNS3_PMU_FILTER_ATTR(_name, _config, _start, _end)            \ >> +    static inline u64 hns3_get_##_name(struct perf_event *event)  \ >> +    {                                                             \ >> +        return FIELD_GET(GENMASK_ULL(_end, _start),           \ >> +                 event->attr._config);                \ >> +    } >> + >> +HNS3_PMU_FILTER_ATTR(event, config, 0, 16); >> +HNS3_PMU_FILTER_ATTR(subevent, config, 0, 7); >> +HNS3_PMU_FILTER_ATTR(event_type, config, 8, 15); >> +HNS3_PMU_FILTER_ATTR(ext_counter_used, config, 16, 16); >> +HNS3_PMU_FILTER_ATTR(real_event, config, 0, 15); >> +HNS3_PMU_FILTER_ATTR(port, config1, 0, 3); >> +HNS3_PMU_FILTER_ATTR(tc, config1, 4, 7); >> +HNS3_PMU_FILTER_ATTR(bdf, config1, 8, 23); >> +HNS3_PMU_FILTER_ATTR(queue, config1, 24, 39); >> +HNS3_PMU_FILTER_ATTR(intr, config1, 40, 51); >> +HNS3_PMU_FILTER_ATTR(global, config1, 52, 52); >> + >> +#define HNS3_BW_EVT_BYTE_NUM(_name)    (&(struct hns3_pmu_event_attr) {\ >> +    HNS3_PMU_EVT_BW_##_name##_BYTE_NUM,                \ >> +    HNS3_PMU_FILTER_BW_##_name}) >> +#define HNS3_BW_EVT_TIME(_name)        (&(struct hns3_pmu_event_attr) {\ >> +    HNS3_PMU_EVT_BW_##_name##_TIME,                    \ >> +    HNS3_PMU_FILTER_BW_##_name}) >> +#define HNS3_PPS_EVT_PACKET_NUM(_name)    (&(struct hns3_pmu_event_attr) {\ >> +    HNS3_PMU_EVT_PPS_##_name##_PACKET_NUM,                \ >> +    HNS3_PMU_FILTER_PPS_##_name}) >> +#define HNS3_PPS_EVT_TIME(_name)    (&(struct hns3_pmu_event_attr) {\ >> +    HNS3_PMU_EVT_PPS_##_name##_TIME,                \ >> +    HNS3_PMU_FILTER_PPS_##_name}) >> +#define HNS3_DLY_EVT_TIME(_name)    (&(struct hns3_pmu_event_attr) {\ >> +    HNS3_PMU_EVT_DLY_##_name##_TIME,                \ >> +    HNS3_PMU_FILTER_DLY_##_name}) >> +#define HNS3_DLY_EVT_PACKET_NUM(_name)    (&(struct hns3_pmu_event_attr) {\ >> +    HNS3_PMU_EVT_DLY_##_name##_PACKET_NUM,                \ >> +    HNS3_PMU_FILTER_DLY_##_name}) >> +#define HNS3_INTR_EVT_INTR_NUM(_name)    (&(struct hns3_pmu_event_attr) {\ >> +    HNS3_PMU_EVT_PPS_##_name##_INTR_NUM,                \ >> +    HNS3_PMU_FILTER_INTR_##_name}) >> +#define HNS3_INTR_EVT_TIME(_name)    (&(struct hns3_pmu_event_attr) {\ >> +    HNS3_PMU_EVT_PPS_##_name##_TIME,                \ >> +    HNS3_PMU_FILTER_INTR_##_name}) >> + >> +static ssize_t hns3_pmu_format_show(struct device *dev, >> +                    struct device_attribute *attr, char *buf) >> +{ >> +    struct dev_ext_attribute *eattr; >> + >> +    eattr = container_of(attr, struct dev_ext_attribute, attr); >> + >> +    return sysfs_emit(buf, "%s\n", (char *)eattr->var); >> +} >> + >> +static ssize_t hns3_pmu_event_show(struct device *dev, >> +                   struct device_attribute *attr, char *buf) >> +{ >> +    struct hns3_pmu_event_attr *event; >> +    struct dev_ext_attribute *eattr; >> + >> +    eattr = container_of(attr, struct dev_ext_attribute, attr); >> +    event = (struct hns3_pmu_event_attr *)eattr->var; > > eattr->var is a void *, so casting not required > Ok, thanks. >> + >> +    return sysfs_emit(buf, "config=0x%05x\n", event->event); >> +} >> + >> +static ssize_t hns3_pmu_filter_mode_show(struct device *dev, >> +                     struct device_attribute *attr, >> +                     char *buf) >> +{ >> +    struct hns3_pmu_event_attr *event; >> +    struct dev_ext_attribute *eattr; >> +    int len; >> + >> +    eattr = container_of(attr, struct dev_ext_attribute, attr); >> +    event = (struct hns3_pmu_event_attr *)eattr->var; >> + >> +    len = sysfs_emit_at(buf, 0, "filter mode supported: "); >> +    if (event->filter_support & HNS3_PMU_FILTER_SUPPORT_GLOBAL) >> +        len += sysfs_emit_at(buf, len, "global "); >> +    if (event->filter_support & HNS3_PMU_FILTER_SUPPORT_PORT) >> +        len += sysfs_emit_at(buf, len, "port "); >> +    if (event->filter_support & HNS3_PMU_FILTER_SUPPORT_PORT_TC) >> +        len += sysfs_emit_at(buf, len, "port-tc "); >> +    if (event->filter_support & HNS3_PMU_FILTER_SUPPORT_FUNC) >> +        len += sysfs_emit_at(buf, len, "func "); >> +    if (event->filter_support & HNS3_PMU_FILTER_SUPPORT_FUNC_QUEUE) >> +        len += sysfs_emit_at(buf, len, "func-queue "); >> +    if (event->filter_support & HNS3_PMU_FILTER_SUPPORT_FUNC_INTR) >> +        len += sysfs_emit_at(buf, len, "func-intr"); >> + >> +    len += sysfs_emit_at(buf, len, "\n"); >> + >> +    return len; >> +} >> + >> +#define HNS3_PMU_ATTR(_name, _func, _config)                \ >> +    (&((struct dev_ext_attribute[]) {                \ >> +        { __ATTR(_name, 0444, _func, NULL), (void *)_config }    \ >> +    })[0].attr.attr) >> + >> +#define HNS3_PMU_FORMAT_ATTR(_name, _format) \ >> +    HNS3_PMU_ATTR(_name, hns3_pmu_format_show, (void *)_format) >> +#define HNS3_PMU_EVENT_ATTR(_name, _event) \ >> +    HNS3_PMU_ATTR(_name, hns3_pmu_event_show, (void *)_event) >> +#define HNS3_PMU_FLT_MODE_ATTR(_name, _event) \ >> +    HNS3_PMU_ATTR(_name, hns3_pmu_filter_mode_show, (void *)_event) >> + >> +#define HNS3_PMU_BW_EVT_PAIR(_name, _macro) \ >> +    HNS3_PMU_EVENT_ATTR(_name##_byte_num, HNS3_BW_EVT_BYTE_NUM(_macro)), \ >> +    HNS3_PMU_EVENT_ATTR(_name##_time, HNS3_BW_EVT_TIME(_macro)) >> +#define HNS3_PMU_PPS_EVT_PAIR(_name, _macro) \ >> +    HNS3_PMU_EVENT_ATTR(_name##_packet_num, HNS3_PPS_EVT_PACKET_NUM(_macro)), \ >> +    HNS3_PMU_EVENT_ATTR(_name##_time, HNS3_PPS_EVT_TIME(_macro)) >> +#define HNS3_PMU_DLY_EVT_PAIR(_name, _macro) \ >> +    HNS3_PMU_EVENT_ATTR(_name##_time, HNS3_DLY_EVT_TIME(_macro)), \ >> +    HNS3_PMU_EVENT_ATTR(_name##_packet_num, HNS3_DLY_EVT_PACKET_NUM(_macro)) >> +#define HNS3_PMU_INTR_EVT_PAIR(_name, _macro) \ >> +    HNS3_PMU_EVENT_ATTR(_name##_intr_num, HNS3_INTR_EVT_INTR_NUM(_macro)), \ >> +    HNS3_PMU_EVENT_ATTR(_name##_time, HNS3_INTR_EVT_TIME(_macro)) >> + >> +#define HNS3_PMU_BW_FLT_MODE_PAIR(_name, _macro) \ >> +    HNS3_PMU_FLT_MODE_ATTR(_name##_byte_num, HNS3_BW_EVT_BYTE_NUM(_macro)), \ >> +    HNS3_PMU_FLT_MODE_ATTR(_name##_time, HNS3_BW_EVT_TIME(_macro)) >> +#define HNS3_PMU_PPS_FLT_MODE_PAIR(_name, _macro) \ >> +    HNS3_PMU_FLT_MODE_ATTR(_name##_packet_num, HNS3_PPS_EVT_PACKET_NUM(_macro)), \ >> +    HNS3_PMU_FLT_MODE_ATTR(_name##_time, HNS3_PPS_EVT_TIME(_macro)) >> +#define HNS3_PMU_DLY_FLT_MODE_PAIR(_name, _macro) \ >> +    HNS3_PMU_FLT_MODE_ATTR(_name##_time, HNS3_DLY_EVT_TIME(_macro)), \ >> +    HNS3_PMU_FLT_MODE_ATTR(_name##_packet_num, HNS3_DLY_EVT_PACKET_NUM(_macro)) >> +#define HNS3_PMU_INTR_FLT_MODE_PAIR(_name, _macro) \ >> +    HNS3_PMU_FLT_MODE_ATTR(_name##_intr_num, HNS3_INTR_EVT_INTR_NUM(_macro)), \ >> +    HNS3_PMU_FLT_MODE_ATTR(_name##_time, HNS3_INTR_EVT_TIME(_macro)) >> + >> +static u8 hns3_pmu_hw_filter_modes[] = { >> +    HNS3_PMU_HW_FILTER_GLOBAL, >> +    HNS3_PMU_HW_FILTER_PORT, >> +    HNS3_PMU_HW_FILTER_PORT_TC, >> +    HNS3_PMU_HW_FILTER_FUNC, >> +    HNS3_PMU_HW_FILTER_FUNC_QUEUE, >> +    HNS3_PMU_HW_FILTER_FUNC_INTR, >> +}; >> + >> +#define HNS3_PMU_SET_HW_FILTER(_hwc, _mode) \ >> +    ((_hwc)->addr_filters = (void *)&hns3_pmu_hw_filter_modes[(_mode)]) >> + >> +static ssize_t identifier_show(struct device *dev, >> +                   struct device_attribute *attr, char *buf) >> +{ >> +    struct hns3_pmu *hns3_pmu = to_hns3_pmu(dev_get_drvdata(dev)); >> + >> +    return sysfs_emit(buf, "0x%x\n", hns3_pmu->identifier); >> +} >> +static DEVICE_ATTR_RO(identifier); >> + >> +static ssize_t cpumask_show(struct device *dev, struct device_attribute *attr, >> +                char *buf) >> +{ >> +    struct hns3_pmu *hns3_pmu = to_hns3_pmu(dev_get_drvdata(dev)); >> + >> +    return sysfs_emit(buf, "%d\n", hns3_pmu->on_cpu); >> +} >> +static DEVICE_ATTR_RO(cpumask); >> + >> +static ssize_t bdf_min_show(struct device *dev, struct device_attribute *attr, >> +                char *buf) >> +{ >> +    struct hns3_pmu *hns3_pmu = to_hns3_pmu(dev_get_drvdata(dev)); >> + >> +    return sysfs_emit(buf, "0x%4x\n", hns3_pmu->bdf_min); >> +} >> +static DEVICE_ATTR_RO(bdf_min); >> + >> +static ssize_t bdf_max_show(struct device *dev, struct device_attribute *attr, >> +                char *buf) >> +{ >> +    struct hns3_pmu *hns3_pmu = to_hns3_pmu(dev_get_drvdata(dev)); >> + >> +    return sysfs_emit(buf, "0x%4x\n", hns3_pmu->bdf_max); >> +} >> +static DEVICE_ATTR_RO(bdf_max); >> + >> +static ssize_t >> +hw_clk_freq_show(struct device *dev, struct device_attribute *attr, char *buf) > > nit: people generally prefer to keep return type on the same line as function name and then spill lines for the arguments > Ok. >> +{ >> +    struct hns3_pmu *hns3_pmu = to_hns3_pmu(dev_get_drvdata(dev)); >> + >> +    return sysfs_emit(buf, "%u\n", hns3_pmu->hw_clk_freq); >> +} >> +static DEVICE_ATTR_RO(hw_clk_freq); >> + >> +static struct attribute *hns3_pmu_events_attr[] = { >> +    /* bandwidth events */ >> +    HNS3_PMU_BW_EVT_PAIR(bw_ssu_egu, SSU_EGU), >> +    HNS3_PMU_BW_EVT_PAIR(bw_ssu_rpu, SSU_RPU), >> +    HNS3_PMU_BW_EVT_PAIR(bw_ssu_roce, SSU_ROCE), >> +    HNS3_PMU_BW_EVT_PAIR(bw_roce_ssu, ROCE_SSU), >> +    HNS3_PMU_BW_EVT_PAIR(bw_tpu_ssu, TPU_SSU), >> +    HNS3_PMU_BW_EVT_PAIR(bw_rpu_rcbrx, RPU_RCBRX), >> +    HNS3_PMU_BW_EVT_PAIR(bw_rcbtx_txsch, RCBTX_TXSCH), >> +    HNS3_PMU_BW_EVT_PAIR(bw_wr_fbd, WR_FBD), >> +    HNS3_PMU_BW_EVT_PAIR(bw_wr_ebd, WR_EBD), >> +    HNS3_PMU_BW_EVT_PAIR(bw_rd_fbd, RD_FBD), >> +    HNS3_PMU_BW_EVT_PAIR(bw_rd_ebd, RD_EBD), >> +    HNS3_PMU_BW_EVT_PAIR(bw_rd_pay_m0, RD_PAY_M0), >> +    HNS3_PMU_BW_EVT_PAIR(bw_rd_pay_m1, RD_PAY_M1), >> +    HNS3_PMU_BW_EVT_PAIR(bw_wr_pay_m0, WR_PAY_M0), >> +    HNS3_PMU_BW_EVT_PAIR(bw_wr_pay_m1, WR_PAY_M1), >> + >> +    /* packet rate events */ >> +    HNS3_PMU_PPS_EVT_PAIR(pps_igu_ssu, IGU_SSU), >> +    HNS3_PMU_PPS_EVT_PAIR(pps_ssu_egu, SSU_EGU), >> +    HNS3_PMU_PPS_EVT_PAIR(pps_ssu_rpu, SSU_RPU), >> +    HNS3_PMU_PPS_EVT_PAIR(pps_ssu_roce, SSU_ROCE), >> +    HNS3_PMU_PPS_EVT_PAIR(pps_roce_ssu, ROCE_SSU), >> +    HNS3_PMU_PPS_EVT_PAIR(pps_tpu_ssu, TPU_SSU), >> +    HNS3_PMU_PPS_EVT_PAIR(pps_rpu_rcbrx, RPU_RCBRX), >> +    HNS3_PMU_PPS_EVT_PAIR(pps_rcbtx_tpu, RCBTX_TPU), >> +    HNS3_PMU_PPS_EVT_PAIR(pps_rcbtx_txsch, RCBTX_TXSCH), >> +    HNS3_PMU_PPS_EVT_PAIR(pps_wr_fbd, WR_FBD), >> +    HNS3_PMU_PPS_EVT_PAIR(pps_wr_ebd, WR_EBD), >> +    HNS3_PMU_PPS_EVT_PAIR(pps_rd_fbd, RD_FBD), >> +    HNS3_PMU_PPS_EVT_PAIR(pps_rd_ebd, RD_EBD), >> +    HNS3_PMU_PPS_EVT_PAIR(pps_rd_pay_m0, RD_PAY_M0), >> +    HNS3_PMU_PPS_EVT_PAIR(pps_rd_pay_m1, RD_PAY_M1), >> +    HNS3_PMU_PPS_EVT_PAIR(pps_wr_pay_m0, WR_PAY_M0), >> +    HNS3_PMU_PPS_EVT_PAIR(pps_wr_pay_m1, WR_PAY_M1), >> +    HNS3_PMU_PPS_EVT_PAIR(pps_intr_nicroh_tx_pre, NICROH_TX_PRE), >> +    HNS3_PMU_PPS_EVT_PAIR(pps_intr_nicroh_rx_pre, NICROH_RX_PRE), >> + >> +    /* latency events */ >> +    HNS3_PMU_DLY_EVT_PAIR(dly_tx_push_to_mac, TX_PUSH), >> +    HNS3_PMU_DLY_EVT_PAIR(dly_tx_normal_to_mac, TX), >> +    HNS3_PMU_DLY_EVT_PAIR(dly_ssu_tx_th_nic, SSU_TX_NIC), >> +    HNS3_PMU_DLY_EVT_PAIR(dly_ssu_tx_th_roce, SSU_TX_ROCE), >> +    HNS3_PMU_DLY_EVT_PAIR(dly_ssu_rx_th_nic, SSU_RX_NIC), >> +    HNS3_PMU_DLY_EVT_PAIR(dly_ssu_rx_th_roce, SSU_RX_ROCE), >> +    HNS3_PMU_DLY_EVT_PAIR(dly_rpu, RPU), >> +    HNS3_PMU_DLY_EVT_PAIR(dly_tpu, TPU), >> +    HNS3_PMU_DLY_EVT_PAIR(dly_rpe, RPE), >> +    HNS3_PMU_DLY_EVT_PAIR(dly_tpe_normal, TPE), >> +    HNS3_PMU_DLY_EVT_PAIR(dly_tpe_push, TPE_PUSH), >> +    HNS3_PMU_DLY_EVT_PAIR(dly_wr_fbd, WR_FBD), >> +    HNS3_PMU_DLY_EVT_PAIR(dly_wr_ebd, WR_EBD), >> +    HNS3_PMU_DLY_EVT_PAIR(dly_rd_fbd, RD_FBD), >> +    HNS3_PMU_DLY_EVT_PAIR(dly_rd_ebd, RD_EBD), >> +    HNS3_PMU_DLY_EVT_PAIR(dly_rd_pay_m0, RD_PAY_M0), >> +    HNS3_PMU_DLY_EVT_PAIR(dly_rd_pay_m1, RD_PAY_M1), >> +    HNS3_PMU_DLY_EVT_PAIR(dly_wr_pay_m0, WR_PAY_M0), >> +    HNS3_PMU_DLY_EVT_PAIR(dly_wr_pay_m1, WR_PAY_M1), >> +    HNS3_PMU_DLY_EVT_PAIR(dly_msix_write, MSIX_WRITE), >> + >> +    /* interrupt rate events */ >> +    HNS3_PMU_INTR_EVT_PAIR(pps_intr_msix_nic, MSIX_NIC), >> + >> +    NULL >> +}; >> + >> +static struct attribute *hns3_pmu_filter_mode_attr[] = { >> +    /* bandwidth events */ >> +    HNS3_PMU_BW_FLT_MODE_PAIR(bw_ssu_egu, SSU_EGU), >> +    HNS3_PMU_BW_FLT_MODE_PAIR(bw_ssu_rpu, SSU_RPU), >> +    HNS3_PMU_BW_FLT_MODE_PAIR(bw_ssu_roce, SSU_ROCE), >> +    HNS3_PMU_BW_FLT_MODE_PAIR(bw_roce_ssu, ROCE_SSU), >> +    HNS3_PMU_BW_FLT_MODE_PAIR(bw_tpu_ssu, TPU_SSU), >> +    HNS3_PMU_BW_FLT_MODE_PAIR(bw_rpu_rcbrx, RPU_RCBRX), >> +    HNS3_PMU_BW_FLT_MODE_PAIR(bw_rcbtx_txsch, RCBTX_TXSCH), >> +    HNS3_PMU_BW_FLT_MODE_PAIR(bw_wr_fbd, WR_FBD), >> +    HNS3_PMU_BW_FLT_MODE_PAIR(bw_wr_ebd, WR_EBD), >> +    HNS3_PMU_BW_FLT_MODE_PAIR(bw_rd_fbd, RD_FBD), >> +    HNS3_PMU_BW_FLT_MODE_PAIR(bw_rd_ebd, RD_EBD), >> +    HNS3_PMU_BW_FLT_MODE_PAIR(bw_rd_pay_m0, RD_PAY_M0), >> +    HNS3_PMU_BW_FLT_MODE_PAIR(bw_rd_pay_m1, RD_PAY_M1), >> +    HNS3_PMU_BW_FLT_MODE_PAIR(bw_wr_pay_m0, WR_PAY_M0), >> +    HNS3_PMU_BW_FLT_MODE_PAIR(bw_wr_pay_m1, WR_PAY_M1), >> + >> +    /* packet rate events */ >> +    HNS3_PMU_PPS_FLT_MODE_PAIR(pps_igu_ssu, IGU_SSU), >> +    HNS3_PMU_PPS_FLT_MODE_PAIR(pps_ssu_egu, SSU_EGU), >> +    HNS3_PMU_PPS_FLT_MODE_PAIR(pps_ssu_rpu, SSU_RPU), >> +    HNS3_PMU_PPS_FLT_MODE_PAIR(pps_ssu_roce, SSU_ROCE), >> +    HNS3_PMU_PPS_FLT_MODE_PAIR(pps_roce_ssu, ROCE_SSU), >> +    HNS3_PMU_PPS_FLT_MODE_PAIR(pps_tpu_ssu, TPU_SSU), >> +    HNS3_PMU_PPS_FLT_MODE_PAIR(pps_rpu_rcbrx, RPU_RCBRX), >> +    HNS3_PMU_PPS_FLT_MODE_PAIR(pps_rcbtx_tpu, RCBTX_TPU), >> +    HNS3_PMU_PPS_FLT_MODE_PAIR(pps_rcbtx_txsch, RCBTX_TXSCH), >> +    HNS3_PMU_PPS_FLT_MODE_PAIR(pps_wr_fbd, WR_FBD), >> +    HNS3_PMU_PPS_FLT_MODE_PAIR(pps_wr_ebd, WR_EBD), >> +    HNS3_PMU_PPS_FLT_MODE_PAIR(pps_rd_fbd, RD_FBD), >> +    HNS3_PMU_PPS_FLT_MODE_PAIR(pps_rd_ebd, RD_EBD), >> +    HNS3_PMU_PPS_FLT_MODE_PAIR(pps_rd_pay_m0, RD_PAY_M0), >> +    HNS3_PMU_PPS_FLT_MODE_PAIR(pps_rd_pay_m1, RD_PAY_M1), >> +    HNS3_PMU_PPS_FLT_MODE_PAIR(pps_wr_pay_m0, WR_PAY_M0), >> +    HNS3_PMU_PPS_FLT_MODE_PAIR(pps_wr_pay_m1, WR_PAY_M1), >> +    HNS3_PMU_PPS_FLT_MODE_PAIR(pps_intr_nicroh_tx_pre, NICROH_TX_PRE), >> +    HNS3_PMU_PPS_FLT_MODE_PAIR(pps_intr_nicroh_rx_pre, NICROH_RX_PRE), >> + >> +    /* latency events */ >> +    HNS3_PMU_DLY_FLT_MODE_PAIR(dly_tx_push_to_mac, TX_PUSH), >> +    HNS3_PMU_DLY_FLT_MODE_PAIR(dly_tx_normal_to_mac, TX), >> +    HNS3_PMU_DLY_FLT_MODE_PAIR(dly_ssu_tx_th_nic, SSU_TX_NIC), >> +    HNS3_PMU_DLY_FLT_MODE_PAIR(dly_ssu_tx_th_roce, SSU_TX_ROCE), >> +    HNS3_PMU_DLY_FLT_MODE_PAIR(dly_ssu_rx_th_nic, SSU_RX_NIC), >> +    HNS3_PMU_DLY_FLT_MODE_PAIR(dly_ssu_rx_th_roce, SSU_RX_ROCE), >> +    HNS3_PMU_DLY_FLT_MODE_PAIR(dly_rpu, RPU), >> +    HNS3_PMU_DLY_FLT_MODE_PAIR(dly_tpu, TPU), >> +    HNS3_PMU_DLY_FLT_MODE_PAIR(dly_rpe, RPE), >> +    HNS3_PMU_DLY_FLT_MODE_PAIR(dly_tpe_normal, TPE), >> +    HNS3_PMU_DLY_FLT_MODE_PAIR(dly_tpe_push, TPE_PUSH), >> +    HNS3_PMU_DLY_FLT_MODE_PAIR(dly_wr_fbd, WR_FBD), >> +    HNS3_PMU_DLY_FLT_MODE_PAIR(dly_wr_ebd, WR_EBD), >> +    HNS3_PMU_DLY_FLT_MODE_PAIR(dly_rd_fbd, RD_FBD), >> +    HNS3_PMU_DLY_FLT_MODE_PAIR(dly_rd_ebd, RD_EBD), >> +    HNS3_PMU_DLY_FLT_MODE_PAIR(dly_rd_pay_m0, RD_PAY_M0), >> +    HNS3_PMU_DLY_FLT_MODE_PAIR(dly_rd_pay_m1, RD_PAY_M1), >> +    HNS3_PMU_DLY_FLT_MODE_PAIR(dly_wr_pay_m0, WR_PAY_M0), >> +    HNS3_PMU_DLY_FLT_MODE_PAIR(dly_wr_pay_m1, WR_PAY_M1), >> +    HNS3_PMU_DLY_FLT_MODE_PAIR(dly_msix_write, MSIX_WRITE), >> + >> +    /* interrupt rate events */ >> +    HNS3_PMU_INTR_FLT_MODE_PAIR(pps_intr_msix_nic, MSIX_NIC), >> + >> +    NULL >> +}; >> + >> +static struct attribute_group hns3_pmu_events_group = { >> +    .name = "events", >> +    .attrs = hns3_pmu_events_attr, >> +}; >> + >> +static struct attribute_group hns3_pmu_filter_mode_group = { >> +    .name = "filtermode", >> +    .attrs = hns3_pmu_filter_mode_attr, >> +}; >> + >> +static struct attribute *hns3_pmu_format_attr[] = { >> +    HNS3_PMU_FORMAT_ATTR(event, "config:0-16"), >> +    HNS3_PMU_FORMAT_ATTR(port, "config1:0-3"), >> +    HNS3_PMU_FORMAT_ATTR(tc, "config1:4-7"), >> +    HNS3_PMU_FORMAT_ATTR(bdf, "config1:8-23"), >> +    HNS3_PMU_FORMAT_ATTR(queue, "config1:24-39"), >> +    HNS3_PMU_FORMAT_ATTR(intr, "config1:40-51"), >> +    HNS3_PMU_FORMAT_ATTR(global, "config1:52-52"), >> +    NULL >> +}; >> + >> +static struct attribute_group hns3_pmu_format_group = { >> +    .name = "format", >> +    .attrs = hns3_pmu_format_attr, >> +}; >> + >> +static struct attribute *hns3_pmu_cpumask_attrs[] = { >> +    &dev_attr_cpumask.attr, >> +    NULL >> +}; >> + >> +static struct attribute_group hns3_pmu_cpumask_attr_group = { >> +    .attrs = hns3_pmu_cpumask_attrs, >> +}; >> + >> +static struct attribute *hns3_pmu_identifier_attrs[] = { >> +    &dev_attr_identifier.attr, >> +    NULL >> +}; >> + >> +static struct attribute_group hns3_pmu_identifier_attr_group = { >> +    .attrs = hns3_pmu_identifier_attrs, >> +}; >> + >> +static struct attribute *hns3_pmu_bdf_range_attrs[] = { >> +    &dev_attr_bdf_min.attr, >> +    &dev_attr_bdf_max.attr, >> +    NULL >> +}; >> + >> +static struct attribute_group hns3_pmu_bdf_range_attr_group = { >> +    .attrs = hns3_pmu_bdf_range_attrs, >> +}; >> + >> +static struct attribute *hns3_pmu_hw_clk_freq_attrs[] = { >> +    &dev_attr_hw_clk_freq.attr, >> +    NULL >> +}; >> + >> +static struct attribute_group hns3_pmu_hw_clk_freq_attr_group = { >> +    .attrs = hns3_pmu_hw_clk_freq_attrs, >> +}; >> + >> +static const struct attribute_group *hns3_pmu_attr_groups[] = { >> +    &hns3_pmu_events_group, >> +    &hns3_pmu_filter_mode_group, >> +    &hns3_pmu_format_group, >> +    &hns3_pmu_cpumask_attr_group, >> +    &hns3_pmu_identifier_attr_group, >> +    &hns3_pmu_bdf_range_attr_group, >> +    &hns3_pmu_hw_clk_freq_attr_group, >> +    NULL >> +}; >> + >> +static u32 hns3_pmu_get_offset(u32 offset, u32 idx) >> +{ >> +    return offset + HNS3_PMU_REG_EVENT_OFFSET + >> +           HNS3_PMU_REG_EVENT_SIZE * idx; >> +} >> + >> +static u32 hns3_pmu_readl(struct hns3_pmu *hns3_pmu, u32 reg_offset, u32 idx) >> +{ >> +    u32 offset = hns3_pmu_get_offset(reg_offset, idx); >> + >> +    return readl(hns3_pmu->base + offset); >> +} >> + >> +static void hns3_pmu_writel(struct hns3_pmu *hns3_pmu, u32 reg_offset, u32 idx, >> +                u32 val) >> +{ >> +    u32 offset = hns3_pmu_get_offset(reg_offset, idx); >> + >> +    writel(val, hns3_pmu->base + offset); >> +} >> + >> +static u64 hns3_pmu_readq(struct hns3_pmu *hns3_pmu, u32 reg_offset, u32 idx) >> +{ >> +    u32 offset = hns3_pmu_get_offset(reg_offset, idx); >> + >> +    return readq(hns3_pmu->base + offset); >> +} >> + >> +static void hns3_pmu_writeq(struct hns3_pmu *hns3_pmu, u32 reg_offset, u32 idx, >> +                u64 val) >> +{ >> +    u32 offset = hns3_pmu_get_offset(reg_offset, idx); >> + >> +    writeq(val, hns3_pmu->base + offset); >> +} >> + >> +static bool hns3_pmu_cmp_event(struct perf_event *target, >> +                   struct perf_event *event) >> +{ >> +    return hns3_get_real_event(target) == hns3_get_real_event(event); >> +} >> + >> +static int hns3_pmu_find_related_event(struct hns3_pmu *hns3_pmu, > > maybe hns3_pmu_find_related_event_index() > Ok. >> +                       struct perf_event *event) >> +{ >> +    struct perf_event *sibling; >> +    int idx; >> + >> +    for (idx = 0; idx < HNS3_PMU_MAX_HW_EVENTS; idx++) { >> +        sibling = hns3_pmu->hw_events[idx]; >> +        if (!sibling) >> +            continue; >> + >> +        if (!hns3_pmu_cmp_event(sibling, event)) >> +            continue; >> + >> +        /* Related events must be used in group */ >> +        if (sibling->group_leader == event->group_leader) >> +            return idx; >> +        else > > no need for else > Ok. >> +            return -EINVAL; >> +    } >> + >> +    return idx; > > so is this an error path? As the only caller checks for idx < 0 as an error > Ok, I think I need to modify processing logic here, thanks. >> +} >> + >> +static int hns3_pmu_get_event_idx(struct hns3_pmu *hns3_pmu) >> +{ >> +    int idx; >> + >> +    for (idx = 0; idx < HNS3_PMU_MAX_HW_EVENTS; idx++) { >> +        if (!hns3_pmu->hw_events[idx]) >> +        return idx; > > misleading indent > Ok, thanks. >> +    } >> + >> +    return -EBUSY; >> +} >> + >> +static bool hns3_pmu_valid_bdf(struct hns3_pmu *hns3_pmu, u16 bdf) >> +{ >> +    struct pci_dev *pdev; >> + >> +    if (bdf < hns3_pmu->bdf_min || bdf > hns3_pmu->bdf_max) { >> +        pci_err(hns3_pmu->pdev, "Invalid EP device: %#x!\n", bdf); >> +        return false; >> +    } >> + >> +    pdev = pci_get_domain_bus_and_slot(pci_domain_nr(hns3_pmu->pdev->bus), >> +                       PCI_BUS_NUM(bdf), >> +                       GET_PCI_DEVFN(bdf)); >> +    if (!pdev) { >> +        pci_err(hns3_pmu->pdev, "Nonexistent EP device: %#x!\n", bdf); >> +        return false; >> +    } >> + >> +    pci_dev_put(pdev); >> +    return true; >> +} >> + >> +static void hns3_pmu_set_qid_para(struct hns3_pmu *hns3_pmu, u32 idx, u16 bdf, >> +                  u16 queue) >> +{ >> +    u32 val; >> + >> +    val = GET_PCI_DEVFN(bdf); >> +    val |= (u32)queue << HNS3_PMU_QID_PARA_QUEUE_S; >> +    hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_QID_PARA, idx, val); >> +} >> + >> +static bool hns3_pmu_qid_req_start(struct hns3_pmu *hns3_pmu, u32 idx) >> +{ >> +    bool queue_id_valid = false; >> +    u32 reg_qid_ctrl, val; >> +    int err; >> + >> +    /* enable queue id request */ >> +    hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_QID_CTRL, idx, >> +            HNS3_PMU_QID_CTRL_REQ_ENABLE); >> + >> +    reg_qid_ctrl = hns3_pmu_get_offset(HNS3_PMU_REG_EVENT_QID_CTRL, idx); >> +    err = readl_poll_timeout(hns3_pmu->base + reg_qid_ctrl, val, >> +                 val & HNS3_PMU_QID_CTRL_DONE, 1, 1000); >> +    if (err == -ETIMEDOUT) { >> +        pci_err(hns3_pmu->pdev, "QID request timeout!\n"); >> +        goto out; >> +    } >> + >> +    queue_id_valid = (val & HNS3_PMU_QID_CTRL_MISS) == 0; > > this seems neater > > queue_id_valid = !(val & HNS3_PMU_QID_CTRL_MISS); > Ok. >> + >> +out: >> +    /* disable qid request and clear status */ >> +    hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_QID_CTRL, idx, 0); >> + >> +    return queue_id_valid; >> +} >> + >> +static bool hns3_pmu_valid_queue(struct hns3_pmu *hns3_pmu, u32 idx, u16 bdf, >> +                 u16 queue) >> +{ >> +    hns3_pmu_set_qid_para(hns3_pmu, idx, bdf, queue); >> + >> +    return hns3_pmu_qid_req_start(hns3_pmu, idx); >> +} >> + >> +static struct hns3_pmu_event_attr *hns3_pmu_get_pmu_event(u32 event) >> +{ >> +    struct hns3_pmu_event_attr *pmu_event; >> +    struct dev_ext_attribute *eattr; >> +    struct device_attribute *dattr; >> +    struct attribute *attr; >> +    u32 i; >> + >> +    for (i = 0; i < ARRAY_SIZE(hns3_pmu_events_attr) - 1; i++) { >> +        attr = hns3_pmu_events_attr[i]; >> +        dattr = container_of(attr, struct device_attribute, attr); >> +        eattr = container_of(dattr, struct dev_ext_attribute, attr); >> +        pmu_event = (struct hns3_pmu_event_attr *)eattr->var; > > eattr->var is void * so no need for a cast > Ok, thanks. >> + >> +        if (event == pmu_event->event) >> +            return pmu_event; >> +    } >> + >> +    return NULL; >> +} >> + >> +static int hns3_pmu_set_func_mode(struct perf_event *event, >> +                  struct hns3_pmu *hns3_pmu) >> +{ >> +    struct hw_perf_event *hwc = &event->hw; >> +    u16 bdf = hns3_get_bdf(event); >> + >> +    if (!hns3_pmu_valid_bdf(hns3_pmu, bdf)) >> +        return -ENOENT; >> + >> +    HNS3_PMU_SET_HW_FILTER(hwc, HNS3_PMU_HW_FILTER_FUNC); >> + >> +    return 0; >> +} >> + >> +static int hns3_pmu_set_func_queue_mode(struct perf_event *event, >> +                    struct hns3_pmu *hns3_pmu) >> +{ >> +    struct hw_perf_event *hwc = &event->hw; >> +    u16 queue_id = hns3_get_queue(event); >> +    u16 bdf = hns3_get_bdf(event); >> + >> +    if (!hns3_pmu_valid_bdf(hns3_pmu, bdf)) >> +        return -ENOENT; >> + >> +    if (!hns3_pmu_valid_queue(hns3_pmu, hwc->idx, bdf, queue_id)) { >> +        pci_err(hns3_pmu->pdev, "Invalid queue: %u\n", queue_id); >> +        return -ENOENT; >> +    } >> + >> +    HNS3_PMU_SET_HW_FILTER(hwc, HNS3_PMU_HW_FILTER_FUNC_QUEUE); >> + >> +    return 0; >> +} >> + >> +static bool >> +hns3_pmu_is_enabled_global_mode(struct perf_event *event, >> +                struct hns3_pmu_event_attr *pmu_event) >> +{ >> +    u8 global = hns3_get_global(event); >> + >> +    if (!(pmu_event->filter_support & HNS3_PMU_FILTER_SUPPORT_GLOBAL)) >> +        return false; >> + >> +    return !!global; > > no need for !! since you return bool the compiler will do this for you > Ok. >> +} >> + >> +static bool hns3_pmu_is_enabled_func_mode(struct perf_event *event, >> +                      struct hns3_pmu_event_attr *pmu_event) >> +{ >> +    u16 queue_id = hns3_get_queue(event); >> +    u16 bdf = hns3_get_bdf(event); >> + >> +    if (!(pmu_event->filter_support & HNS3_PMU_FILTER_SUPPORT_FUNC)) >> +        return false; >> +    else if (queue_id != HNS3_PMU_FILTER_ALL_QUEUE) >> +        return false; >> + >> +    return !!bdf; > > as above > Ok. >> +} >> + >> +static bool >> +hns3_pmu_is_enabled_func_queue_mode(struct perf_event *event, >> +                    struct hns3_pmu_event_attr *pmu_event) >> +{ >> +    u16 queue_id = hns3_get_queue(event); >> +    u16 bdf = hns3_get_bdf(event); >> + >> +    if (!(pmu_event->filter_support & HNS3_PMU_FILTER_SUPPORT_FUNC_QUEUE)) >> +        return false; >> +    else if (queue_id == HNS3_PMU_FILTER_ALL_QUEUE) >> +        return false; >> + >> +    return !!bdf; > > again > Ok. >> +} >> + >> +static bool hns3_pmu_is_enabled_port_mode(struct perf_event *event, >> +                      struct hns3_pmu_event_attr *pmu_event) >> +{ >> +    u8 tc_id = hns3_get_tc(event); >> + >> +    if (!(pmu_event->filter_support & HNS3_PMU_FILTER_SUPPORT_PORT)) >> +        return false; >> + >> +    return tc_id == HNS3_PMU_FILTER_ALL_TC; >> +} >> + >> +static bool >> +hns3_pmu_is_enabled_port_tc_mode(struct perf_event *event, >> +                 struct hns3_pmu_event_attr *pmu_event) >> +{ >> +    u8 tc_id = hns3_get_tc(event); >> + >> +    if (!(pmu_event->filter_support & HNS3_PMU_FILTER_SUPPORT_PORT_TC)) >> +        return false; >> + >> +    return tc_id != HNS3_PMU_FILTER_ALL_TC; >> +} >> + >> +static bool >> +hns3_pmu_is_enabled_func_intr_mode(struct perf_event *event, >> +                   struct hns3_pmu *hns3_pmu, >> +                   struct hns3_pmu_event_attr *pmu_event) >> +{ >> +    u16 bdf = hns3_get_bdf(event); >> + >> +    if (!(pmu_event->filter_support & HNS3_PMU_FILTER_SUPPORT_FUNC_INTR)) >> +        return false; >> + >> +    return hns3_pmu_valid_bdf(hns3_pmu, bdf); >> +} >> + >> +static int hns3_pmu_select_filter_mode(struct perf_event *event, >> +                       struct hns3_pmu *hns3_pmu) >> +{ >> +    struct hns3_pmu_event_attr *pmu_event; >> +    struct hw_perf_event *hwc = &event->hw; >> +    u32 event_id = hns3_get_event(event); >> + >> +    pmu_event = hns3_pmu_get_pmu_event(event_id); >> +    if (!pmu_event) { >> +        pci_err(hns3_pmu->pdev, "Invalid pmu event\n"); >> +        return -ENOENT; >> +    } >> + >> +    if (hns3_pmu_is_enabled_global_mode(event, pmu_event)) { >> +        HNS3_PMU_SET_HW_FILTER(hwc, HNS3_PMU_HW_FILTER_GLOBAL); >> +        return 0; >> +    } >> + >> +    if (hns3_pmu_is_enabled_func_mode(event, pmu_event)) >> +        return hns3_pmu_set_func_mode(event, hns3_pmu); >> + >> +    if (hns3_pmu_is_enabled_func_queue_mode(event, pmu_event)) >> +        return hns3_pmu_set_func_queue_mode(event, hns3_pmu); >> + >> +    if (hns3_pmu_is_enabled_port_mode(event, pmu_event)) { >> +        HNS3_PMU_SET_HW_FILTER(hwc, HNS3_PMU_HW_FILTER_PORT); >> +        return 0; >> +    } >> + >> +    if (hns3_pmu_is_enabled_port_tc_mode(event, pmu_event)) { >> +        HNS3_PMU_SET_HW_FILTER(hwc, HNS3_PMU_HW_FILTER_PORT_TC); >> +        return 0; >> +    } >> + >> +    if (hns3_pmu_is_enabled_func_intr_mode(event, hns3_pmu, pmu_event)) { >> +        HNS3_PMU_SET_HW_FILTER(hwc, HNS3_PMU_HW_FILTER_FUNC_INTR); >> +        return 0; >> +    } >> + >> +    return -ENOENT; >> +} >> + >> +static bool hns3_pmu_validate_event_group(struct perf_event *event) >> +{ >> +    struct perf_event *sibling, *leader = event->group_leader; >> +    struct perf_event *event_group[HNS3_PMU_MAX_HW_EVENTS]; >> +    int counters = 1; >> +    int num; >> + >> +    event_group[0] = leader; >> +    if (!is_software_event(leader)) { >> +        if (leader->pmu != event->pmu) >> +            return false; >> + >> +        if (leader != event && !hns3_pmu_cmp_event(leader, event)) >> +            event_group[counters++] = event; >> +    } >> + >> +    for_each_sibling_event(sibling, event->group_leader) { >> +        if (is_software_event(sibling)) >> +            continue; >> + >> +        if (sibling->pmu != event->pmu) >> +            return false; >> + >> +        for (num = 0; num < counters; num++) { >> +            if (hns3_pmu_cmp_event(event_group[num], sibling)) >> +                break; >> +        } >> + >> +        if (num == counters) >> +            event_group[counters++] = sibling; >> +    } >> + >> +    return counters <= HNS3_PMU_MAX_HW_EVENTS; >> +} >> + >> +static u32 hns3_pmu_get_filter_condition(struct perf_event *event) >> +{ >> +    struct hw_perf_event *hwc = &event->hw; >> +    u16 intr_id = hns3_get_intr(event); >> +    u8 port_id = hns3_get_port(event); >> +    u16 bdf = hns3_get_bdf(event); >> +    u8 tc_id = hns3_get_tc(event); >> +    u8 filter_mode; >> +    u32 filter = 0; >> + >> +    filter_mode = *(u8 *)hwc->addr_filters; >> +    switch (filter_mode) { >> +    case HNS3_PMU_HW_FILTER_PORT: >> +        filter = FILTER_CONDITION_PORT(port_id); >> +        break; >> +    case HNS3_PMU_HW_FILTER_PORT_TC: >> +        filter = FILTER_CONDITION_PORT_TC(port_id, tc_id); >> +        break; >> +    case HNS3_PMU_HW_FILTER_FUNC: >> +    case HNS3_PMU_HW_FILTER_FUNC_QUEUE: >> +        filter = GET_PCI_DEVFN(bdf); >> +        break; >> +    case HNS3_PMU_HW_FILTER_FUNC_INTR: >> +        filter = FILTER_CONDITION_FUNC_INTR(GET_PCI_DEVFN(bdf), >> +                            intr_id); >> +        break; >> +    default: >> +        break; >> +    } >> + >> +    return filter; >> +} >> + >> +static void hns3_pmu_config_filter(struct perf_event *event) >> +{ >> +    struct hns3_pmu *hns3_pmu = to_hns3_pmu(event->pmu); >> +    u8 event_type = hns3_get_event_type(event); >> +    u8 subevent_id = hns3_get_subevent(event); >> +    struct hw_perf_event *hwc = &event->hw; >> +    u8 filter_mode = *(u8 *)hwc->addr_filters; >> +    u16 queue_id = hns3_get_queue(event); >> +    u16 bdf = hns3_get_bdf(event); >> +    u32 idx = hwc->idx; >> +    u32 val; >> + >> +    val = event_type; >> +    val |= subevent_id << HNS3_PMU_CTRL_SUBEVENT_S; >> +    val |= filter_mode << HNS3_PMU_CTRL_FILTER_MODE_S; >> +    val |= HNS3_PMU_EVENT_OVERFLOW_RESTART; >> +    hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx, val); >> + >> +    val = hns3_pmu_get_filter_condition(event); >> +    hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_HIGH, idx, val); >> + >> +    if (filter_mode == HNS3_PMU_HW_FILTER_FUNC_QUEUE) >> +        hns3_pmu_set_qid_para(hns3_pmu, idx, bdf, queue_id); >> +} >> + >> +static void hns3_pmu_enable_counter(struct hns3_pmu *hns3_pmu, >> +                    struct hw_perf_event *hwc) >> +{ >> +    u32 idx = hwc->idx; >> +    u32 val; >> + >> +    val = hns3_pmu_readl(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx); >> +    val |= HNS3_PMU_EVENT_EN; >> +    hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx, val); >> +} >> + >> +static void hns3_pmu_disable_counter(struct hns3_pmu *hns3_pmu, >> +                     struct hw_perf_event *hwc) >> +{ >> +    u32 idx = hwc->idx; >> +    u32 val; >> + >> +    val = hns3_pmu_readl(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx); >> +    val &= ~HNS3_PMU_EVENT_EN; >> +    hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx, val); >> +} >> + >> +static void hns3_pmu_enable_intr(struct hns3_pmu *hns3_pmu, >> +                 struct hw_perf_event *hwc) >> +{ >> +    u32 idx = hwc->idx; >> +    u32 val; >> + >> +    val = hns3_pmu_readl(hns3_pmu, HNS3_PMU_REG_EVENT_INTR_MASK, idx); >> +    val &= ~HNS3_PMU_INTR_MASK_OVERFLOW; >> +    hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_INTR_MASK, idx, val); >> +} >> + >> +static void hns3_pmu_disable_intr(struct hns3_pmu *hns3_pmu, >> +                  struct hw_perf_event *hwc) >> +{ >> +    u32 idx = hwc->idx; >> +    u32 val; >> + >> +    val = hns3_pmu_readl(hns3_pmu, HNS3_PMU_REG_EVENT_INTR_MASK, idx); >> +    val |= HNS3_PMU_INTR_MASK_OVERFLOW; >> +    hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_INTR_MASK, idx, val); >> +} >> + >> +static void hns3_pmu_clear_intr_status(struct hns3_pmu *hns3_pmu, u32 idx) >> +{ >> +    u32 val; >> + >> +    val = hns3_pmu_readl(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx); >> +    val |= HNS3_PMU_EVENT_STATUS_RESET; >> +    hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx, val); >> + >> +    val = hns3_pmu_readl(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx); >> +    val &= ~HNS3_PMU_EVENT_STATUS_RESET; >> +    hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx, val); >> +} >> + >> +static u64 hns3_pmu_read_counter(struct perf_event *event) >> +{ >> +    struct hns3_pmu *hns3_pmu = to_hns3_pmu(event->pmu); >> + >> +    return hns3_pmu_readq(hns3_pmu, event->hw.event_base, event->hw.idx); >> +} >> + >> +static void hns3_pmu_write_counter(struct perf_event *event, u64 value) >> +{ >> +    struct hns3_pmu *hns3_pmu = to_hns3_pmu(event->pmu); >> +    u32 idx = event->hw.idx; >> + >> +    hns3_pmu_writeq(hns3_pmu, HNS3_PMU_REG_EVENT_COUNTER, idx, value); >> +    hns3_pmu_writeq(hns3_pmu, HNS3_PMU_REG_EVENT_EXT_COUNTER, idx, value); >> +} >> + >> +static void hns3_pmu_init_counter(struct perf_event *event) >> +{ >> +    struct hw_perf_event *hwc = &event->hw; >> + >> +    local64_set(&hwc->prev_count, 0); >> +    hns3_pmu_write_counter(event, 0); >> +} >> + >> +static int hns3_pmu_event_init(struct perf_event *event) >> +{ >> +    struct hns3_pmu *hns3_pmu = to_hns3_pmu(event->pmu); >> +    struct hw_perf_event *hwc = &event->hw; >> +    int idx; >> +    int ret; >> + >> +    if (event->attr.type != event->pmu->type) >> +        return -ENOENT; >> + >> +    /* Sampling is not supported */ >> +    if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) >> +        return -EOPNOTSUPP; >> + >> +    event->cpu = hns3_pmu->on_cpu; >> + >> +    idx = hns3_pmu_get_event_idx(hns3_pmu); >> +    if (idx < 0) { >> +        pci_err(hns3_pmu->pdev, "Up to %u events are supported!\n", >> +            HNS3_PMU_MAX_HW_EVENTS); >> +        return -EBUSY; >> +    } >> + >> +    hwc->idx = idx; >> + >> +    ret = hns3_pmu_select_filter_mode(event, hns3_pmu); >> +    if (ret) { >> +        pci_err(hns3_pmu->pdev, "Invalid filter, ret = %d.\n", ret); >> +        return ret; >> +    } >> + >> +    if (!hns3_pmu_validate_event_group(event)) { >> +        pci_err(hns3_pmu->pdev, "Invalid event group.\n"); >> +        return -EINVAL; >> +    } >> + >> +    if (hns3_get_ext_counter_used(event)) >> +        hwc->event_base = HNS3_PMU_REG_EVENT_EXT_COUNTER; >> +    else >> +        hwc->event_base = HNS3_PMU_REG_EVENT_COUNTER; >> + >> +    return 0; >> +} >> + >> +static void hns3_pmu_read(struct perf_event *event) >> +{ >> +    struct hw_perf_event *hwc = &event->hw; >> +    u64 new_cnt, prev_cnt, delta; >> + >> +    do { >> +        prev_cnt = local64_read(&hwc->prev_count); >> +        new_cnt = hns3_pmu_read_counter(event); >> +    } while (local64_cmpxchg(&hwc->prev_count, prev_cnt, new_cnt) != >> +         prev_cnt); >> + >> +    delta = new_cnt - prev_cnt; >> +    local64_add(delta, &event->count); >> +} >> + >> +static void hns3_pmu_start(struct perf_event *event, int flags) >> +{ >> +    struct hns3_pmu *hns3_pmu = to_hns3_pmu(event->pmu); >> +    struct hw_perf_event *hwc = &event->hw; >> + >> +    if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED))) >> +        return; >> + >> +    WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); >> +    hwc->state = 0; >> + >> +    hns3_pmu_config_filter(event); >> +    hns3_pmu_init_counter(event); >> +    hns3_pmu_enable_intr(hns3_pmu, hwc); >> +    hns3_pmu_enable_counter(hns3_pmu, hwc); >> + >> +    perf_event_update_userpage(event); >> +} >> + >> +static void hns3_pmu_stop(struct perf_event *event, int flags) >> +{ >> +    struct hns3_pmu *hns3_pmu = to_hns3_pmu(event->pmu); >> +    struct hw_perf_event *hwc = &event->hw; >> + >> +    hns3_pmu_disable_counter(hns3_pmu, hwc); >> +    hns3_pmu_disable_intr(hns3_pmu, hwc); >> + >> +    WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); >> +    hwc->state |= PERF_HES_STOPPED; >> + >> +    if (hwc->state & PERF_HES_UPTODATE) >> +        return; >> + >> +    /* Read hardware counter and update the perf counter statistics */ >> +    hns3_pmu_read(event); >> +    hwc->state |= PERF_HES_UPTODATE; >> +} >> + >> +static int hns3_pmu_add(struct perf_event *event, int flags) >> +{ >> +    struct hns3_pmu *hns3_pmu = to_hns3_pmu(event->pmu); >> +    struct hw_perf_event *hwc = &event->hw; >> +    int idx; >> + >> +    hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; >> + >> +    /* Check all working events to find a related event. */ >> +    idx = hns3_pmu_find_related_event(hns3_pmu, event); >> +    if (idx < 0) >> +        return idx; >> + >> +    /* Current event shares an enabled hardware event with related event */ >> +    if (idx < HNS3_PMU_MAX_HW_EVENTS) { >> +        hwc->idx = idx; >> +        goto start_count; >> +    } >> + >> +    idx = hns3_pmu_get_event_idx(hns3_pmu); >> +    if (idx < 0) >> +        return idx; >> + >> +    hwc->idx = idx; >> +    hns3_pmu->hw_events[idx] = event; >> + >> +start_count: >> +    if (flags & PERF_EF_START) >> +        hns3_pmu_start(event, PERF_EF_RELOAD); >> + >> +    return 0; >> +} >> + >> +static void hns3_pmu_del(struct perf_event *event, int flags) >> +{ >> +    struct hns3_pmu *hns3_pmu = to_hns3_pmu(event->pmu); >> +    struct hw_perf_event *hwc = &event->hw; >> + >> +    hns3_pmu_stop(event, PERF_EF_UPDATE); >> +    hns3_pmu->hw_events[hwc->idx] = NULL; >> +    perf_event_update_userpage(event); >> +} >> + >> +static void hns3_pmu_enable(struct pmu *pmu) >> +{ >> +    struct hns3_pmu *hns3_pmu = to_hns3_pmu(pmu); >> +    u32 val; >> + >> +    val = readl(hns3_pmu->base + HNS3_PMU_REG_GLOBAL_CTRL); >> +    val |= HNS3_PMU_GLOBAL_START; >> +    writel(val, hns3_pmu->base + HNS3_PMU_REG_GLOBAL_CTRL); >> +} >> + >> +static void hns3_pmu_disable(struct pmu *pmu) >> +{ >> +    struct hns3_pmu *hns3_pmu = to_hns3_pmu(pmu); >> +    u32 val; >> + >> +    val = readl(hns3_pmu->base + HNS3_PMU_REG_GLOBAL_CTRL); >> +    val &= ~HNS3_PMU_GLOBAL_START; >> +    writel(val, hns3_pmu->base + HNS3_PMU_REG_GLOBAL_CTRL); >> +} >> + >> +static int hns3_pmu_alloc_pmu(struct pci_dev *pdev, struct hns3_pmu *hns3_pmu) >> +{ >> +    u16 device_id; >> +    char *name; >> +    u32 val; >> + >> +    hns3_pmu->base = pcim_iomap_table(pdev)[BAR_2]; >> +    if (!hns3_pmu->base) { >> +        pci_err(pdev, "ioremap failed for hns3_pmu resource\n"); >> +        return -ENOMEM; >> +    } >> + >> +    hns3_pmu->hw_clk_freq = readl(hns3_pmu->base + HNS3_PMU_REG_CLOCK_FREQ); >> + >> +    val = readl(hns3_pmu->base + HNS3_PMU_REG_BDF); >> +    hns3_pmu->bdf_min = val & 0xffff; >> +    hns3_pmu->bdf_max = val >> 16; >> + >> +    val = readl(hns3_pmu->base + HNS3_PMU_REG_DEVICE_ID); >> +    device_id = val & 0xffff; >> +    name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "hns3_pmu_sicl_%u", device_id); >> +    if (!name) >> +        return -ENOMEM; >> + >> +    hns3_pmu->pdev = pdev; >> +    hns3_pmu->on_cpu = -1; >> +    hns3_pmu->identifier = readl(hns3_pmu->base + HNS3_PMU_REG_VERSION); >> +    hns3_pmu->pmu = (struct pmu) { >> +        .name        = name, >> +        .module        = THIS_MODULE, >> +        .event_init    = hns3_pmu_event_init, >> +        .pmu_enable    = hns3_pmu_enable, >> +        .pmu_disable    = hns3_pmu_disable, >> +        .add        = hns3_pmu_add, >> +        .del        = hns3_pmu_del, >> +        .start        = hns3_pmu_start, >> +        .stop        = hns3_pmu_stop, >> +        .read        = hns3_pmu_read, >> +        .task_ctx_nr    = perf_invalid_context, >> +        .attr_groups    = hns3_pmu_attr_groups, >> +        .capabilities    = PERF_PMU_CAP_NO_EXCLUDE, >> +    }; >> + >> +    return 0; >> +} >> + >> +static irqreturn_t hns3_pmu_irq(int irq, void *data) >> +{ >> +    struct hns3_pmu *hns3_pmu = data; >> +    u32 intr_status, idx; >> + >> +    for (idx = 0; idx < HNS3_PMU_MAX_HW_EVENTS; idx++) { >> +        intr_status = hns3_pmu_readl(hns3_pmu, >> +                         HNS3_PMU_REG_EVENT_INTR_STATUS, >> +                         idx); >> + >> +        /* >> +         * As each counter will restart from 0 when it is overflowed, >> +         * extra processing is no need, just clear interrupt status. >> +         */ >> +        if (intr_status) >> +            hns3_pmu_clear_intr_status(hns3_pmu, idx); >> +    } >> + >> +    return IRQ_HANDLED; >> +} >> + >> +static int hns3_pmu_online_cpu(unsigned int cpu, struct hlist_node *node) >> +{ >> +    struct hns3_pmu *hns3_pmu; >> + >> +    hns3_pmu = hlist_entry_safe(node, struct hns3_pmu, node); >> +    if (!hns3_pmu) >> +        return -ENODEV; >> + >> +    if (hns3_pmu->on_cpu == -1) { >> +        hns3_pmu->on_cpu = cpu; >> +        irq_set_affinity(hns3_pmu->irq, cpumask_of(cpu)); >> +    } >> + >> +    return 0; >> +} >> + >> +static int hns3_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node) >> +{ >> +    struct hns3_pmu *hns3_pmu; >> +    unsigned int target; >> + >> +    hns3_pmu = hlist_entry_safe(node, struct hns3_pmu, node); >> +    if (!hns3_pmu) >> +        return -ENODEV; >> + >> +    /* Nothing to do if this CPU doesn't own the PMU */ >> +    if (hns3_pmu->on_cpu != cpu) >> +        return 0; >> + >> +    /* Choose a new CPU from all online cpus */ >> +    target = cpumask_any_but(cpu_online_mask, cpu); >> +    if (target >= nr_cpu_ids) >> +        return 0; >> + >> +    perf_pmu_migrate_context(&hns3_pmu->pmu, cpu, target); >> +    hns3_pmu->on_cpu = target; >> +    irq_set_affinity(hns3_pmu->irq, cpumask_of(target)); >> + >> +    return 0; >> +} >> + >> +static void hns3_pmu_free_irq(void *data) >> +{ >> +    struct pci_dev *pdev = data; >> + >> +    pci_free_irq_vectors(pdev); >> +} >> + >> +static int hns3_pmu_irq_register(struct pci_dev *pdev, >> +                 struct hns3_pmu *hns3_pmu) >> +{ >> +    int irq, ret; >> + >> +    ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); >> +    if (ret < 0) { >> +        pci_err(pdev, "failed to enable MSI vectors, ret = %d.\n", ret); >> +        return ret; >> +    } >> + >> +    ret = devm_add_action(&pdev->dev, hns3_pmu_free_irq, pdev); >> +    if (ret) { >> +        pci_err(pdev, "failed to add free irq action, ret = %d.\n", ret); >> +        return ret; >> +    } >> + >> +    irq = pci_irq_vector(pdev, 0); >> +    ret = devm_request_irq(&pdev->dev, irq, hns3_pmu_irq, 0, >> +                   hns3_pmu->pmu.name, hns3_pmu); >> +    if (ret) { >> +        pci_err(pdev, "failed to register irq, ret = %d.\n", ret); >> +        return ret; >> +    } >> + >> +    hns3_pmu->irq = irq; >> + >> +    return 0; >> +} >> + >> +static int hns3_pmu_init_pmu(struct pci_dev *pdev, struct hns3_pmu *hns3_pmu) >> +{ >> +    int ret; >> + >> +    ret = hns3_pmu_alloc_pmu(pdev, hns3_pmu); >> +    if (ret) >> +        return ret; >> + >> +    ret = hns3_pmu_irq_register(pdev, hns3_pmu); >> +    if (ret) >> +        return ret; >> + >> +    ret = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_HNS3_PMU_ONLINE, >> +                       &hns3_pmu->node); >> +    if (ret) { >> +        pci_err(pdev, "failed to register hotplug, ret = %d.\n", ret); >> +        return ret; >> +    } >> + >> +    ret = perf_pmu_register(&hns3_pmu->pmu, hns3_pmu->pmu.name, -1); >> +    if (ret) { >> +        pci_err(pdev, "failed to register perf PMU, ret = %d.\n", ret); >> +        cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_HNS3_PMU_ONLINE, >> +                        &hns3_pmu->node); >> +    } >> + >> +    return ret; >> +} >> + >> +static void hns3_pmu_uninit_pmu(struct pci_dev *pdev) >> +{ >> +    struct hns3_pmu *hns3_pmu = pci_get_drvdata(pdev); >> + >> +    perf_pmu_unregister(&hns3_pmu->pmu); >> +    cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_HNS3_PMU_ONLINE, >> +                    &hns3_pmu->node); >> +} >> + >> +static int hns3_pmu_init_dev(struct pci_dev *pdev) >> +{ >> +    int ret; >> + >> +    ret = pcim_enable_device(pdev); >> +    if (ret) { >> +        pci_err(pdev, "failed to enable pci device, ret = %d.\n", ret); >> +        return ret; >> +    } >> + >> +    ret = pcim_iomap_regions(pdev, BIT(BAR_2), "hns3_pmu"); >> +    if (ret < 0) { >> +        pci_err(pdev, "failed to request pci region, ret = %d.\n", ret); >> +        return ret; >> +    } >> + >> +    pci_set_master(pdev); >> + >> +    return 0; >> +} >> + >> +static int hns3_pmu_probe(struct pci_dev *pdev, const struct pci_device_id *id) >> +{ >> +    struct hns3_pmu *hns3_pmu; >> +    int ret; >> + >> +    hns3_pmu = devm_kzalloc(&pdev->dev, sizeof(*hns3_pmu), GFP_KERNEL); >> +    if (!hns3_pmu) >> +        return -ENOMEM; >> + >> +    ret = hns3_pmu_init_dev(pdev); >> +    if (ret) >> +        return ret; >> + >> +    ret = hns3_pmu_init_pmu(pdev, hns3_pmu); >> +    if (ret) { >> +        pci_clear_master(pdev); >> +        return ret; >> +    } >> + >> +    pci_set_drvdata(pdev, hns3_pmu); >> + >> +    return ret; >> +} >> + >> +static void hns3_pmu_remove(struct pci_dev *pdev) >> +{ >> +    hns3_pmu_uninit_pmu(pdev); >> +    pci_clear_master(pdev); >> +    pci_set_drvdata(pdev, NULL); >> +} >> + >> +static const struct pci_device_id hns3_pmu_ids[] = { >> +    { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, 0xa22b) }, >> +    { 0, } >> +}; >> +MODULE_DEVICE_TABLE(pci, hns3_pmu_ids); >> + >> +static struct pci_driver hns3_pmu_driver = { >> +    .name = "hns3_pmu", >> +    .id_table = hns3_pmu_ids, >> +    .probe = hns3_pmu_probe, >> +    .remove = hns3_pmu_remove, >> +}; >> + >> +static int __init hns3_pmu_module_init(void) >> +{ >> +    int ret; >> + >> +    ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_HNS3_PMU_ONLINE, >> +                      "AP_PERF_ARM_HNS3_PMU_ONLINE", >> +                      hns3_pmu_online_cpu, >> +                      hns3_pmu_offline_cpu); >> +    if (ret) { >> +        pr_err("failed to setup HNS3 PMU hotplug, ret = %d.\n", ret); >> +        return ret; >> +    } >> + >> +    ret = pci_register_driver(&hns3_pmu_driver); >> +    if (ret) { >> +        pr_err("failed to register pci driver, ret = %d.\n", ret); >> +        cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HNS3_PMU_ONLINE); >> +    } >> + >> +    return ret; >> +} >> +module_init(hns3_pmu_module_init); >> + >> +static void __exit hns3_pmu_module_exit(void) >> +{ >> +    pci_unregister_driver(&hns3_pmu_driver); >> +    cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HNS3_PMU_ONLINE); >> +} >> +module_exit(hns3_pmu_module_exit); >> + >> +MODULE_DESCRIPTION("HNS3 PMU driver"); >> +MODULE_LICENSE("GPL v2"); >> diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h >> index 411a428ace4d..9c2cb0600740 100644 >> --- a/include/linux/cpuhotplug.h >> +++ b/include/linux/cpuhotplug.h >> @@ -226,6 +226,7 @@ enum cpuhp_state { >>       CPUHP_AP_PERF_ARM_HISI_PA_ONLINE, >>       CPUHP_AP_PERF_ARM_HISI_SLLC_ONLINE, >>       CPUHP_AP_PERF_ARM_HISI_PCIE_PMU_ONLINE, >> +    CPUHP_AP_PERF_ARM_HNS3_PMU_ONLINE, >>       CPUHP_AP_PERF_ARM_L2X0_ONLINE, >>       CPUHP_AP_PERF_ARM_QCOM_L2_ONLINE, >>       CPUHP_AP_PERF_ARM_QCOM_L3_ONLINE, > > . From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 98E3FC433F5 for ; Sat, 16 Apr 2022 10:39:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:CC:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=qTW044agbIYWgCNFCKeCbesMFasy91rMmx8ZJJ/lVAA=; b=OiPV7un0d/tAknzpuBpm/rMnC3 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(7.221.188.64) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Sat, 16 Apr 2022 18:37:33 +0800 Received: from [10.67.102.67] (10.67.102.67) by kwepemm600016.china.huawei.com (7.193.23.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Sat, 16 Apr 2022 18:37:32 +0800 Subject: Re: [PATCH V3 2/2] drivers/perf: hisi: add driver for HNS3 PMU To: John Garry , "will@kernel.org" , "mark.rutland@arm.com" CC: "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Linuxarm , "liuqi (BA)" , Zhangshaokun , "Fangjian (Jay)" , "lipeng (Y)" , "shenjian (K)" , moyufeng References: <20220329113930.37631-1-huangguangbin2@huawei.com> <20220329113930.37631-3-huangguangbin2@huawei.com> <2a66d1d7-cf85-1ce0-1adf-f72a27243fe1@huawei.com> From: "huangguangbin (A)" Message-ID: <5f23529e-0ddf-57bf-9bc3-5246fbec92c2@huawei.com> Date: Sat, 16 Apr 2022 18:37:32 +0800 User-Agent: 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MjozOSwgR3VhbmdiaW4gSHVhbmcgd3JvdGU6Cj4+IEhOUzMoSGlTaWxpY29uIE5ldHdvcmsgU3lz dGVtIDMpIFBNVSBpcyBSQ2lFUCBkZXZpY2UgaW4gSGlTaWxpY29uIFNvQyBOSUMsCj4+IHN1cHBv cnRzIGNvbGxlY3Rpb24gb2YgcGVyZm9ybWFuY2Ugc3RhdGlzdGljcyBzdWNoIGFzIGJhbmR3aWR0 aCwgbGF0ZW5jeSwKPj4gcGFja2V0IHJhdGUgYW5kIGludGVycnVwdCByYXRlLgo+Pgo+PiBOSUMg b2YgZWFjaCBTSUNMIGhhcyBvbmUgUE1VIGRldmljZSBmb3IgaXQuIERyaXZlciByZWdpc3RlcnMg ZWFjaCBQTVUKPj4gZGV2aWNlIHRvIHBlcmYsIGFuZCBleHBvcnRzIGluZm9ybWF0aW9uIG9mIHN1 cHBvcnRlZCBldmVudHMsIGZpbHRlciBtb2RlIG9mCj4+IGVhY2ggZXZlbnQsIGJkZiByYW5nZSwg aGFyZHdhcmUgY2xvY2sgZnJlcXVlbmN5LCBpZGVudGlmaWVyIGFuZCBzbyBvbiB2aWEKPj4gc3lz ZnMuCj4+Cj4+IEVhY2ggUE1VIGRldmljZSBoYXMgaXRzIG93biByZWdpc3RlcnMgb2YgY29udHJv bCwgY291bnRlcnMgYW5kIGludGVycnVwdCwKPj4gYW5kIGl0IHN1cHBvcnRzIDggaGFyZHdhcmUg ZXZlbnRzLCBlYWNoIGhhcmR3YXJkIGV2ZW50IGhhcyBpdHMgb3duCj4+IHJlZ2lzdGVycyBmb3Ig Y29uZmlndXJhdGlvbiwgY291bnRlcnMgYW5kIGludGVycnVwdC4KPj4KPj4gRmlsdGVyIG9wdGlv bnMgY29udGFpbnM6Cj4+IGNvbmZpZ8KgwqDCoMKgwqDCoCAtIHNlbGVjdCBldmVudAo+PiBwb3J0 wqDCoMKgwqDCoMKgwqDCoCAtIHNlbGVjdCBwaHlzaWNhbCBwb3J0IG9mIG5pYwo+PiB0Y8KgwqDC oMKgwqDCoMKgwqDCoMKgIC0gc2VsZWN0IHRjKG11c3QgYmUgdXNlZCB3aXRoIHBvcnQpCj4+IGZ1 bmPCoMKgwqDCoMKgwqDCoMKgIC0gc2VsZWN0IFBGL1ZGCj4+IHF1ZXVlwqDCoMKgwqDCoMKgwqAg LSBzZWxlY3QgcXVldWUgb2YgUEYvVkYobXVzdCBiZSB1c2VkIHdpdGggZnVuYykKPj4gaW50csKg wqDCoMKgwqDCoMKgwqAgLSBzZWxlY3QgaW50ZXJydXB0IG51bWJlcihtdXN0IGJlIHVzZWQgd2l0 aCBmdW5jKQo+PiBnbG9iYWzCoMKgwqDCoMKgwqAgLSBzZWxlY3QgYWxsIGZ1bmN0aW9ucyBvZiBJ TyBESUUKPj4KPiAKPiBHZW5lcmFsbHkgbG9va3Mgb2ssIEp1c3QgYSBmZXcgbW9yZSBjb21tZW50 cy4KPiAKPj4gU2lnbmVkLW9mZi1ieTogR3VhbmdiaW4gSHVhbmcgPGh1YW5nZ3VhbmdiaW4yQGh1 YXdlaS5jb20+Cj4+IC0tLQo+PiDCoCBNQUlOVEFJTkVSU8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgIHzCoMKgwqAgNiArCj4+IMKgIGRyaXZlcnMvcGVyZi9oaXNp bGljb24vS2NvbmZpZ8KgwqDCoCB8wqDCoCAxMCArCj4+IMKgIGRyaXZlcnMvcGVyZi9oaXNpbGlj b24vTWFrZWZpbGXCoMKgIHzCoMKgwqAgMSArCj4+IMKgIGRyaXZlcnMvcGVyZi9oaXNpbGljb24v aG5zM19wbXUuYyB8IDE2NDAgKysrKysrKysrKysrKysrKysrKysrKysrKysrKysKPj4gwqAgaW5j bHVkZS9saW51eC9jcHVob3RwbHVnLmjCoMKgwqDCoMKgwqDCoCB8wqDCoMKgIDEgKwo+PiDCoCA1 IGZpbGVzIGNoYW5nZWQsIDE2NTggaW5zZXJ0aW9ucygrKQo+PiDCoCBjcmVhdGUgbW9kZSAxMDA2 NDQgZHJpdmVycy9wZXJmL2hpc2lsaWNvbi9obnMzX3BtdS5jCj4+Cj4+IGRpZmYgLS1naXQgYS9N QUlOVEFJTkVSUyBiL01BSU5UQUlORVJTCj4+IGluZGV4IDY5YTI5MzVkYWY2Yy4uMzRiODczNDg1 MDNhIDEwMDY0NAo+PiAtLS0gYS9NQUlOVEFJTkVSUwo+PiArKysgYi9NQUlOVEFJTkVSUwo+PiBA QCAtODY5MSw2ICs4NjkxLDEyIEBAIEY6wqDCoMKgIERvY3VtZW50YXRpb24vYWRtaW4tZ3VpZGUv cGVyZi9oaXNpLXBjaWUtcG11LnJzdAo+PiDCoCBGOsKgwqDCoCBEb2N1bWVudGF0aW9uL2FkbWlu LWd1aWRlL3BlcmYvaGlzaS1wbXUucnN0Cj4+IMKgIEY6wqDCoMKgIGRyaXZlcnMvcGVyZi9oaXNp bGljb24KPj4gK0hJU0lMSUNPTiBITlMzIFBNVSBEUklWRVIKPj4gK006wqDCoMKgIEd1YW5nYmlu IEh1YW5nIDxodWFuZ2d1YW5nYmluMkBodWF3ZWkuY29tPgo+PiArUzrCoMKgwqAgU3VwcG9ydGVk Cj4+ICtGOsKgwqDCoCBEb2N1bWVudGF0aW9uL2FkbWluLWd1aWRlL3BlcmYvaG5zMy1wbXUucnN0 Cj4+ICtGOsKgwqDCoCBkcml2ZXJzL3BlcmYvaGlzaWxpY29uL2huczNfcG11LmMKPj4gKwo+PiDC oCBISVNJTElDT04gUU0gQU5EIFpJUCBDb250cm9sbGVyIERSSVZFUgo+PiDCoCBNOsKgwqDCoCBa aG91IFdhbmcgPHdhbmd6aG91MUBoaXNpbGljb24uY29tPgo+PiDCoCBMOsKgwqDCoCBsaW51eC1j cnlwdG9Admdlci5rZXJuZWwub3JnCj4+IGRpZmYgLS1naXQgYS9kcml2ZXJzL3BlcmYvaGlzaWxp Y29uL0tjb25maWcgYi9kcml2ZXJzL3BlcmYvaGlzaWxpY29uL0tjb25maWcKPj4gaW5kZXggNTU0 NjIxOGI1NTk4Li4xNzFiZmMxYjZiYzIgMTAwNjQ0Cj4+IC0tLSBhL2RyaXZlcnMvcGVyZi9oaXNp bGljb24vS2NvbmZpZwo+PiArKysgYi9kcml2ZXJzL3BlcmYvaGlzaWxpY29uL0tjb25maWcKPj4g QEAgLTE0LDMgKzE0LDEzIEBAIGNvbmZpZyBISVNJX1BDSUVfUE1VCj4+IMKgwqDCoMKgwqDCoMKg IFJDaUVQIGRldmljZXMuCj4+IMKgwqDCoMKgwqDCoMKgIEFkZHMgdGhlIFBDSWUgUE1VIGludG8g cGVyZiBldmVudHMgc3lzdGVtIGZvciBtb25pdG9yaW5nIGxhdGVuY3ksCj4+IMKgwqDCoMKgwqDC oMKgIGJhbmR3aWR0aCBldGMuCj4+ICsKPj4gK2NvbmZpZyBITlMzX1BNVQo+PiArwqDCoMKgIHRy aXN0YXRlICJITlMzIFBFUkYgUE1VIgo+PiArwqDCoMKgIGRlcGVuZHMgb24gQVJNNjQgfHwgQ09N UElMRV9URVNUCj4gCj4gaXMgc2VlIGhuczNfcG11X3JlYWRxKCkgYmVsb3csIHNvIHlvdSBuZWVk IHRvIGVuc3VyZSB0aGUgYXJjaCBzdXBwb3J0cyByZWFkcSAtIHNvIEkgdGhpbmsgdGhhdCB5b3Ug bmVlZCB0byBkZXBlbmQgb24gNjRiLiBJIGFzc3VtZSB0aGF0IHlvdSBuZXZlciBidWlsdCB0aGlz IGZvciBhIDMyYiBhcmNoCj4gCk91ciBDUFUgYXJjaCBpcyBqdXN0IGFybTY0LCBzbyBJIHNldCBp dCB0byBkZXBlbmQgb24gQVJNNjQuIFllYWgsIEkgbmV2ZXIgYnVpbHQgdGhpcyBmb3IgYSAzMmIg YXJjaCBiZWNhdXNlIHdlIHdvdWxkIG5ldmVyIHJ1biB0aGlzIGRyaXZlciBvbiAzMmIgQ1BVLgpB cmUgeW91IG1lYW4gdGhhdCBobnMzX3BtdV9yZWFkcSgpIHdpbGwgYmUgY29tcGlsZWQgZmFpbGVk IGZvciAzMmIgYXJjaD8gU28gSSB0aGluayB0aGF0IEkgbmVlZCB0byBkZWxldGUgQ09NUElMRV9U RVNUIHRvIHByZXZlbnQgZnJvbSB0aGlzIGNhc2UuCgoKPj4gK8KgwqDCoCBkZXBlbmRzIG9uIFBD SQo+PiArwqDCoMKgIGhlbHAKPj4gK8KgwqDCoMKgwqAgUHJvdmlkZSBzdXBwb3J0IGZvciBITlMz IHBlcmZvcm1hbmNlIG1vbml0b3JpbmcgdW5pdCAoUE1VKSBSQ2lFUAo+PiArwqDCoMKgwqDCoCBk ZXZpY2VzLgo+PiArwqDCoMKgwqDCoCBBZGRzIHRoZSBITlMzIFBNVSBpbnRvIHBlcmYgZXZlbnRz IHN5c3RlbSBmb3IgbW9uaXRvcmluZyBsYXRlbmN5LAo+PiArwqDCoMKgwqDCoCBiYW5kd2lkdGgg ZXRjLgo+PiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9wZXJmL2hpc2lsaWNvbi9NYWtlZmlsZSBiL2Ry aXZlcnMvcGVyZi9oaXNpbGljb24vTWFrZWZpbGUKPj4gaW5kZXggNTA2ZWQzOWUzMjY2Li4xMzI5 N2VjMjc5OGYgMTAwNjQ0Cj4+IC0tLSBhL2RyaXZlcnMvcGVyZi9oaXNpbGljb24vTWFrZWZpbGUK Pj4gKysrIGIvZHJpdmVycy9wZXJmL2hpc2lsaWNvbi9NYWtlZmlsZQo+PiBAQCAtNCwzICs0LDQg QEAgb2JqLSQoQ09ORklHX0hJU0lfUE1VKSArPSBoaXNpX3VuY29yZV9wbXUubyBoaXNpX3VuY29y ZV9sM2NfcG11Lm8gXAo+PiDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgaGlzaV91bmNv cmVfcGFfcG11Lm8KPj4gwqAgb2JqLSQoQ09ORklHX0hJU0lfUENJRV9QTVUpICs9IGhpc2lfcGNp ZV9wbXUubwo+PiArb2JqLSQoQ09ORklHX0hOUzNfUE1VKSArPSBobnMzX3BtdS5vCj4+IGRpZmYg LS1naXQgYS9kcml2ZXJzL3BlcmYvaGlzaWxpY29uL2huczNfcG11LmMgYi9kcml2ZXJzL3BlcmYv aGlzaWxpY29uL2huczNfcG11LmMKPj4gbmV3IGZpbGUgbW9kZSAxMDA2NDQKPj4gaW5kZXggMDAw MDAwMDAwMDAwLi4yZWNkOGYyOTlhODYKPj4gLS0tIC9kZXYvbnVsbAo+PiArKysgYi9kcml2ZXJz L3BlcmYvaGlzaWxpY29uL2huczNfcG11LmMKPj4gQEAgLTAsMCArMSwxNjQwIEBACj4+ICsvLyBT UERYLUxpY2Vuc2UtSWRlbnRpZmllcjogR1BMLTIuMC1vbmx5Cj4+ICsvKgo+PiArICogVGhpcyBk cml2ZXIgYWRkcyBzdXBwb3J0IGZvciBITlMzIFBNVSBpRVAgZGV2aWNlLiBSZWxhdGVkIHBlcmYg ZXZlbnRzIGFyZQo+PiArICogYmFuZHdpZHRoLCBsYXRlbmN5LCBwYWNrZXQgcmF0ZSwgaW50ZXJy dXB0IHJhdGUgZXRjLgo+PiArICoKPj4gKyAqIENvcHlyaWdodCAoQykgMjAyMiBIaVNpbGljb24g TGltaXRlZAo+PiArICovCj4+ICsjaW5jbHVkZSA8bGludXgvYml0ZmllbGQuaD4KPj4gKyNpbmNs dWRlIDxsaW51eC9iaXRtYXAuaD4KPj4gKyNpbmNsdWRlIDxsaW51eC9idWcuaD4KPj4gKyNpbmNs dWRlIDxsaW51eC9jcHVob3RwbHVnLmg+Cj4+ICsjaW5jbHVkZSA8bGludXgvY3B1bWFzay5oPgo+ PiArI2luY2x1ZGUgPGxpbnV4L2RlbGF5Lmg+Cj4+ICsjaW5jbHVkZSA8bGludXgvZGV2aWNlLmg+ Cj4+ICsjaW5jbHVkZSA8bGludXgvZXJyLmg+Cj4+ICsjaW5jbHVkZSA8bGludXgvaW50ZXJydXB0 Lmg+Cj4+ICsjaW5jbHVkZSA8bGludXgvaW9wb2xsLmg+Cj4+ICsjaW5jbHVkZSA8bGludXgvaXJx Lmg+Cj4+ICsjaW5jbHVkZSA8bGludXgva2VybmVsLmg+Cj4+ICsjaW5jbHVkZSA8bGludXgvbGlz dC5oPgo+PiArI2luY2x1ZGUgPGxpbnV4L21vZHVsZS5oPgo+PiArI2luY2x1ZGUgPGxpbnV4L3Bj aS5oPgo+PiArI2luY2x1ZGUgPGxpbnV4L3BjaS1lcGYuaD4KPj4gKyNpbmNsdWRlIDxsaW51eC9w ZXJmX2V2ZW50Lmg+Cj4+ICsjaW5jbHVkZSA8bGludXgvc21wLmg+Cj4+ICsKPj4gKy8qIHJlZ2lz dGVycyBvZmZzZXQgYWRkcmVzcyAqLwo+PiArI2RlZmluZSBITlMzX1BNVV9SRUdfR0xPQkFMX0NU UkzCoMKgwqDCoMKgwqDCoCAweDAwMDAKPj4gKyNkZWZpbmUgSE5TM19QTVVfUkVHX0NMT0NLX0ZS RVHCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIDB4MDAyMAo+PiArI2RlZmluZSBITlMzX1BNVV9SRUdf QkRGwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCAweDBmZTAKPj4gKyNkZWZpbmUgSE5TM19QTVVfUkVH X1ZFUlNJT07CoMKgwqDCoMKgwqDCoMKgwqDCoMKgIDB4MGZlNAo+PiArI2RlZmluZSBITlMzX1BN VV9SRUdfREVWSUNFX0lEwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCAweDBmZTgKPj4gKwo+PiArI2Rl ZmluZSBITlMzX1BNVV9SRUdfRVZFTlRfT0ZGU0VUwqDCoMKgwqDCoMKgwqAgMHgxMDAwCj4+ICsj ZGVmaW5lIEhOUzNfUE1VX1JFR19FVkVOVF9TSVpFwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCAweDEw MDAKPj4gKyNkZWZpbmUgSE5TM19QTVVfUkVHX0VWRU5UX0NUUkxfTE9XwqDCoMKgwqDCoMKgwqAg MHgwMAo+PiArI2RlZmluZSBITlMzX1BNVV9SRUdfRVZFTlRfQ1RSTF9ISUdIwqDCoMKgwqDCoMKg wqAgMHgwNAo+PiArI2RlZmluZSBITlMzX1BNVV9SRUdfRVZFTlRfSU5UUl9TVEFUVVPCoMKgwqDC oMKgwqDCoCAweDA4Cj4+ICsjZGVmaW5lIEhOUzNfUE1VX1JFR19FVkVOVF9JTlRSX01BU0vCoMKg wqDCoMKgwqDCoCAweDBjCj4+ICsjZGVmaW5lIEhOUzNfUE1VX1JFR19FVkVOVF9DT1VOVEVSwqDC oMKgwqDCoMKgwqAgMHgxMAo+PiArI2RlZmluZSBITlMzX1BNVV9SRUdfRVZFTlRfRVhUX0NPVU5U RVLCoMKgwqDCoMKgwqDCoCAweDE4Cj4+ICsjZGVmaW5lIEhOUzNfUE1VX1JFR19FVkVOVF9RSURf Q1RSTMKgwqDCoMKgwqDCoMKgIDB4MjgKPj4gKyNkZWZpbmUgSE5TM19QTVVfUkVHX0VWRU5UX1FJ RF9QQVJBwqDCoMKgwqDCoMKgwqAgMHgyYwo+PiArCj4+ICsjZGVmaW5lIEhOUzNfUE1VX0ZJTFRF Ul9TVVBQT1JUX0dMT0JBTMKgwqDCoMKgwqDCoMKgIEJJVCgwKQo+PiArI2RlZmluZSBITlMzX1BN VV9GSUxURVJfU1VQUE9SVF9QT1JUwqDCoMKgwqDCoMKgwqAgQklUKDEpCj4+ICsjZGVmaW5lIEhO UzNfUE1VX0ZJTFRFUl9TVVBQT1JUX1BPUlRfVEPCoMKgwqDCoMKgwqDCoCBCSVQoMikKPj4gKyNk ZWZpbmUgSE5TM19QTVVfRklMVEVSX1NVUFBPUlRfRlVOQ8KgwqDCoMKgwqDCoMKgIEJJVCgzKQo+ PiArI2RlZmluZSBITlMzX1BNVV9GSUxURVJfU1VQUE9SVF9GVU5DX1FVRVVFwqDCoMKgIEJJVCg0 KQo+PiArI2RlZmluZSBITlMzX1BNVV9GSUxURVJfU1VQUE9SVF9GVU5DX0lOVFLCoMKgwqAgQklU KDUpCj4+ICsKPj4gKyNkZWZpbmUgSE5TM19QTVVfRklMVEVSX0FMTF9UQ8KgwqDCoMKgwqDCoMKg wqDCoMKgwqAgMHhmCj4+ICsjZGVmaW5lIEhOUzNfUE1VX0ZJTFRFUl9BTExfUVVFVUXCoMKgwqDC oMKgwqDCoCAweGZmZmYKPj4gKwo+PiArI2RlZmluZSBITlMzX1BNVV9DVFJMX1NVQkVWRU5UX1PC oMKgwqDCoMKgwqDCoCA0Cj4+ICsjZGVmaW5lIEhOUzNfUE1VX0NUUkxfRklMVEVSX01PREVfU8Kg wqDCoMKgwqDCoMKgIDI0Cj4+ICsKPj4gKyNkZWZpbmUgSE5TM19QTVVfR0xPQkFMX1NUQVJUwqDC oMKgwqDCoMKgwqDCoMKgwqDCoCBCSVQoMCkKPj4gKwo+PiArI2RlZmluZSBITlMzX1BNVV9FVkVO VF9TVEFUVVNfUkVTRVTCoMKgwqDCoMKgwqDCoCBCSVQoMTEpCj4+ICsjZGVmaW5lIEhOUzNfUE1V X0VWRU5UX0VOwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCBCSVQoMTIpCj4+ICsjZGVmaW5lIEhOUzNf UE1VX0VWRU5UX09WRVJGTE9XX1JFU1RBUlTCoMKgwqDCoMKgwqDCoCBCSVQoMTUpCj4+ICsKPj4g KyNkZWZpbmUgSE5TM19QTVVfUUlEX1BBUkFfRlVOQ19TwqDCoMKgwqDCoMKgwqAgMAo+PiArI2Rl ZmluZSBITlMzX1BNVV9RSURfUEFSQV9RVUVVRV9TwqDCoMKgwqDCoMKgwqAgMTYKPj4gKwo+PiAr I2RlZmluZSBITlMzX1BNVV9RSURfQ1RSTF9SRVFfRU5BQkxFwqDCoMKgwqDCoMKgwqAgQklUKDAp Cj4+ICsjZGVmaW5lIEhOUzNfUE1VX1FJRF9DVFJMX0RPTkXCoMKgwqDCoMKgwqDCoMKgwqDCoMKg IEJJVCgxKQo+PiArI2RlZmluZSBITlMzX1BNVV9RSURfQ1RSTF9NSVNTwqDCoMKgwqDCoMKgwqDC oMKgwqDCoCBCSVQoMikKPj4gKwo+PiArI2RlZmluZSBITlMzX1BNVV9JTlRSX01BU0tfT1ZFUkZM T1fCoMKgwqDCoMKgwqDCoCBCSVQoMSkKPj4gKwo+PiArI2RlZmluZSBITlMzX1BNVV9NQVhfSFdf RVZFTlRTwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCA4Cj4+ICsKPj4gKy8qCj4+ICsgKiBFYWNoIGhh cmR3YXJlIGV2ZW50IGNvbnRhaW5zIHR3byByZWdpc3RlcnMgKGNvdW50ZXIgYW5kIGV4dF9jb3Vu dGVyKSBmb3IKPj4gKyAqIGJhbmR3aWR0aCwgcGFja2V0IHJhdGUsIGxhdGVuY3kgYW5kIGludGVy cnVwdCByYXRlLiBUaGVzZSB0d28gcmVnaXN0ZXJzIHdpbGwKPj4gKyAqIGJlIHRyaWdnZXJlZCB0 byBydW4gYXQgdGhlIHNhbWUgd2hlbiBhIGhhcmR3YXJlIGV2ZW50IGlzIGVuYWJsZWQuCj4+ICsg Kgo+PiArICogUGVyZm9ybWFuY2Ugb2YgZWFjaCBoYXJkd2FyZSBldmVudCBpcyBjYWxjdWxhdGVk IGJ5OiBjb3VudGVyIC8gZXh0X2NvdW50ZXIuCj4+ICsgKgo+PiArICogQXMgcHJvY2VzcyBvZiBw ZXJmb3JtYW5jZSBkYXRhIGlzIG5vdCByZWNvbW1lbmRlZCBwdXQgaW4gZHJpdmVyLCB3ZSBleHBv c2UKPiAKPiAvcy9BcyBwcm9jZXNzIG9mIHBlcmZvcm1hbmNlIGRhdGEgaXMgbm90IHJlY29tbWVu ZGVkIHB1dCBpbiBkcml2ZXIvU2luY2UgcHJvY2Vzc2luZyBvZiBkYXRhIGlzIHByZWZlcnJlZCB0 byBiZSBkb25lIGluIHVzZXJzcGFjZS8KPiAKT2suCgo+PiArICogZXh0X2NvdW50ZXIgYXMgYSBz ZXBhcmF0ZSBldmVudCBmb3IgdXNlcnNwYWNlIGFuZCB1c2UgYml0IDE2IHRvIGluZGljYXRlIGl0 Lgo+PiArICogRm9yIGV4YW1wbGUsIGV2ZW50IDB4MDAwMDEgYW5kIDB4MTAwMDEgYXJlIGFjdHVh bGx5IG9uZSBldmVudCBmb3IgaGFyZHdhcmUKPj4gKyAqIGJlY2F1c2UgYml0IDAtMTUgYXJlIHNh bWUuIElmIHRoZSBiaXQgMTYgb2Ygb25lIGV2ZW50IGlzIDAgbWVhbnMgdG8gZ2V0Cj4+ICsgKiBj b3VudGVyLCBvdGhlcndpc2UgbWVhbnMgdG8gZ2V0IGV4dF9jb3VudGVyLgo+IAo+IAo+IEkgYW0g bm90IHN1cmUgd2hhdCB5b3UgbWVhbiBieSAiZ2V0IGV4dF9jb3VudGVyIiBvciAiZ2V0IGNvdW50 ZXIiIC0gcGxlYXNlIG1ha2UgdGhpcyBhIGJpdCBtb3JlIGNsZWFyCj4gCk9rLgoKPj4gKyAqLwo+ PiArLyogYmFuZHdpZHRoIGV2ZW50cyAqLwo+PiArI2RlZmluZSBITlMzX1BNVV9FVlRfQldfU1NV X0VHVV9CWVRFX05VTcKgwqDCoMKgwqDCoMKgIDB4MDAwMDEKPj4gKyNkZWZpbmUgSE5TM19QTVVf RVZUX0JXX1NTVV9FR1VfVElNRcKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgMHgxMDAwMQo+PiArI2Rl ZmluZSBITlMzX1BNVV9FVlRfQldfU1NVX1JQVV9CWVRFX05VTcKgwqDCoMKgwqDCoMKgIDB4MDAw MDIKPj4gKyNkZWZpbmUgSE5TM19QTVVfRVZUX0JXX1NTVV9SUFVfVElNRcKgwqDCoMKgwqDCoMKg wqDCoMKgwqAgMHgxMDAwMgo+PiArI2RlZmluZSBITlMzX1BNVV9FVlRfQldfU1NVX1JPQ0VfQllU RV9OVU3CoMKgwqDCoMKgwqDCoCAweDAwMDAzCj4+ICsjZGVmaW5lIEhOUzNfUE1VX0VWVF9CV19T U1VfUk9DRV9USU1FwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCAweDEwMDAzCj4+ICsjZGVmaW5lIEhO UzNfUE1VX0VWVF9CV19ST0NFX1NTVV9CWVRFX05VTcKgwqDCoMKgwqDCoMKgIDB4MDAwMDQKPj4g KyNkZWZpbmUgSE5TM19QTVVfRVZUX0JXX1JPQ0VfU1NVX1RJTUXCoMKgwqDCoMKgwqDCoMKgwqDC oMKgIDB4MTAwMDQKPj4gKyNkZWZpbmUgSE5TM19QTVVfRVZUX0JXX1RQVV9TU1VfQllURV9OVU3C oMKgwqDCoMKgwqDCoCAweDAwMDA1Cj4+ICsjZGVmaW5lIEhOUzNfUE1VX0VWVF9CV19UUFVfU1NV X1RJTUXCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIDB4MTAwMDUKPj4gKyNkZWZpbmUgSE5TM19QTVVf RVZUX0JXX1JQVV9SQ0JSWF9CWVRFX05VTcKgwqDCoMKgwqDCoMKgIDB4MDAwMDYKPj4gKyNkZWZp bmUgSE5TM19QTVVfRVZUX0JXX1JQVV9SQ0JSWF9USU1FwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCAw eDEwMDA2Cj4+ICsjZGVmaW5lIEhOUzNfUE1VX0VWVF9CV19SQ0JUWF9UWFNDSF9CWVRFX05VTcKg wqDCoMKgwqDCoMKgIDB4MDAwMDgKPj4gKyNkZWZpbmUgSE5TM19QTVVfRVZUX0JXX1JDQlRYX1RY U0NIX1RJTUXCoMKgwqDCoMKgwqDCoCAweDEwMDA4Cj4+ICsjZGVmaW5lIEhOUzNfUE1VX0VWVF9C V19XUl9GQkRfQllURV9OVU3CoMKgwqDCoMKgwqDCoMKgwqDCoMKgIDB4MDAwMDkKPj4gKyNkZWZp bmUgSE5TM19QTVVfRVZUX0JXX1dSX0ZCRF9USU1FwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCAweDEw MDA5Cj4+ICsjZGVmaW5lIEhOUzNfUE1VX0VWVF9CV19XUl9FQkRfQllURV9OVU3CoMKgwqDCoMKg wqDCoMKgwqDCoMKgIDB4MDAwMGEKPj4gKyNkZWZpbmUgSE5TM19QTVVfRVZUX0JXX1dSX0VCRF9U SU1FwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCAweDEwMDBhCj4+ICsjZGVmaW5lIEhOUzNfUE1VX0VW VF9CV19SRF9GQkRfQllURV9OVU3CoMKgwqDCoMKgwqDCoMKgwqDCoMKgIDB4MDAwMGIKPj4gKyNk ZWZpbmUgSE5TM19QTVVfRVZUX0JXX1JEX0ZCRF9USU1FwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCAw eDEwMDBiCj4+ICsjZGVmaW5lIEhOUzNfUE1VX0VWVF9CV19SRF9FQkRfQllURV9OVU3CoMKgwqDC oMKgwqDCoMKgwqDCoMKgIDB4MDAwMGMKPj4gKyNkZWZpbmUgSE5TM19QTVVfRVZUX0JXX1JEX0VC RF9USU1FwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCAweDEwMDBjCj4+ICsjZGVmaW5lIEhOUzNfUE1V X0VWVF9CV19SRF9QQVlfTTBfQllURV9OVU3CoMKgwqDCoMKgwqDCoCAweDAwMDBkCj4+ICsjZGVm aW5lIEhOUzNfUE1VX0VWVF9CV19SRF9QQVlfTTBfVElNRcKgwqDCoMKgwqDCoMKgwqDCoMKgwqAg MHgxMDAwZAo+PiArI2RlZmluZSBITlMzX1BNVV9FVlRfQldfUkRfUEFZX00xX0JZVEVfTlVNwqDC oMKgwqDCoMKgwqAgMHgwMDAwZQo+PiArI2RlZmluZSBITlMzX1BNVV9FVlRfQldfUkRfUEFZX00x X1RJTUXCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIDB4MTAwMGUKPj4gKyNkZWZpbmUgSE5TM19QTVVf RVZUX0JXX1dSX1BBWV9NMF9CWVRFX05VTcKgwqDCoMKgwqDCoMKgIDB4MDAwMGYKPj4gKyNkZWZp bmUgSE5TM19QTVVfRVZUX0JXX1dSX1BBWV9NMF9USU1FwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCAw eDEwMDBmCj4+ICsjZGVmaW5lIEhOUzNfUE1VX0VWVF9CV19XUl9QQVlfTTFfQllURV9OVU3CoMKg wqDCoMKgwqDCoCAweDAwMDEwCj4+ICsjZGVmaW5lIEhOUzNfUE1VX0VWVF9CV19XUl9QQVlfTTFf VElNRcKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgMHgxMDAxMAo+PiArCj4+ICsvKiBwYWNrZXQgcmF0 ZSBldmVudHMgKi8KPj4gKyNkZWZpbmUgSE5TM19QTVVfRVZUX1BQU19JR1VfU1NVX1BBQ0tFVF9O VU3CoMKgwqDCoMKgwqDCoCAweDAwMTAwCj4+ICsjZGVmaW5lIEhOUzNfUE1VX0VWVF9QUFNfSUdV X1NTVV9USU1FwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCAweDEwMTAwCj4+ICsjZGVmaW5lIEhOUzNf UE1VX0VWVF9QUFNfU1NVX0VHVV9QQUNLRVRfTlVNwqDCoMKgwqDCoMKgwqAgMHgwMDEwMQo+PiAr I2RlZmluZSBITlMzX1BNVV9FVlRfUFBTX1NTVV9FR1VfVElNRcKgwqDCoMKgwqDCoMKgwqDCoMKg wqAgMHgxMDEwMQo+PiArI2RlZmluZSBITlMzX1BNVV9FVlRfUFBTX1NTVV9SUFVfUEFDS0VUX05V TcKgwqDCoMKgwqDCoMKgIDB4MDAxMDIKPj4gKyNkZWZpbmUgSE5TM19QTVVfRVZUX1BQU19TU1Vf UlBVX1RJTUXCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIDB4MTAxMDIKPj4gKyNkZWZpbmUgSE5TM19Q TVVfRVZUX1BQU19TU1VfUk9DRV9QQUNLRVRfTlVNwqDCoMKgwqDCoMKgwqAgMHgwMDEwMwo+PiAr I2RlZmluZSBITlMzX1BNVV9FVlRfUFBTX1NTVV9ST0NFX1RJTUXCoMKgwqDCoMKgwqDCoMKgwqDC oMKgIDB4MTAxMDMKPj4gKyNkZWZpbmUgSE5TM19QTVVfRVZUX1BQU19ST0NFX1NTVV9QQUNLRVRf TlVNwqDCoMKgwqDCoMKgwqAgMHgwMDEwNAo+PiArI2RlZmluZSBITlMzX1BNVV9FVlRfUFBTX1JP Q0VfU1NVX1RJTUXCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIDB4MTAxMDQKPj4gKyNkZWZpbmUgSE5T M19QTVVfRVZUX1BQU19UUFVfU1NVX1BBQ0tFVF9OVU3CoMKgwqDCoMKgwqDCoCAweDAwMTA1Cj4+ ICsjZGVmaW5lIEhOUzNfUE1VX0VWVF9QUFNfVFBVX1NTVV9USU1FwqDCoMKgwqDCoMKgwqDCoMKg wqDCoCAweDEwMTA1Cj4+ICsjZGVmaW5lIEhOUzNfUE1VX0VWVF9QUFNfUlBVX1JDQlJYX1BBQ0tF VF9OVU3CoMKgwqDCoMKgwqDCoCAweDAwMTA2Cj4+ICsjZGVmaW5lIEhOUzNfUE1VX0VWVF9QUFNf UlBVX1JDQlJYX1RJTUXCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIDB4MTAxMDYKPj4gKyNkZWZpbmUg SE5TM19QTVVfRVZUX1BQU19SQ0JUWF9UUFVfUEFDS0VUX05VTcKgwqDCoMKgwqDCoMKgIDB4MDAx MDcKPj4gKyNkZWZpbmUgSE5TM19QTVVfRVZUX1BQU19SQ0JUWF9UUFVfVElNRcKgwqDCoMKgwqDC oMKgwqDCoMKgwqAgMHgxMDEwNwo+PiArI2RlZmluZSBITlMzX1BNVV9FVlRfUFBTX1JDQlRYX1RY U0NIX1BBQ0tFVF9OVU3CoMKgwqDCoMKgwqDCoCAweDAwMTA4Cj4+ICsjZGVmaW5lIEhOUzNfUE1V X0VWVF9QUFNfUkNCVFhfVFhTQ0hfVElNRcKgwqDCoMKgwqDCoMKgIDB4MTAxMDgKPj4gKyNkZWZp bmUgSE5TM19QTVVfRVZUX1BQU19XUl9GQkRfUEFDS0VUX05VTcKgwqDCoMKgwqDCoMKgIDB4MDAx MDkKPj4gKyNkZWZpbmUgSE5TM19QTVVfRVZUX1BQU19XUl9GQkRfVElNRcKgwqDCoMKgwqDCoMKg wqDCoMKgwqAgMHgxMDEwOQo+PiArI2RlZmluZSBITlMzX1BNVV9FVlRfUFBTX1dSX0VCRF9QQUNL RVRfTlVNwqDCoMKgwqDCoMKgwqAgMHgwMDEwYQo+PiArI2RlZmluZSBITlMzX1BNVV9FVlRfUFBT X1dSX0VCRF9USU1FwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCAweDEwMTBhCj4+ICsjZGVmaW5lIEhO UzNfUE1VX0VWVF9QUFNfUkRfRkJEX1BBQ0tFVF9OVU3CoMKgwqDCoMKgwqDCoCAweDAwMTBiCj4+ ICsjZGVmaW5lIEhOUzNfUE1VX0VWVF9QUFNfUkRfRkJEX1RJTUXCoMKgwqDCoMKgwqDCoMKgwqDC oMKgIDB4MTAxMGIKPj4gKyNkZWZpbmUgSE5TM19QTVVfRVZUX1BQU19SRF9FQkRfUEFDS0VUX05V TcKgwqDCoMKgwqDCoMKgIDB4MDAxMGMKPj4gKyNkZWZpbmUgSE5TM19QTVVfRVZUX1BQU19SRF9F QkRfVElNRcKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgMHgxMDEwYwo+PiArI2RlZmluZSBITlMzX1BN VV9FVlRfUFBTX1JEX1BBWV9NMF9QQUNLRVRfTlVNwqDCoMKgwqDCoMKgwqAgMHgwMDEwZAo+PiAr I2RlZmluZSBITlMzX1BNVV9FVlRfUFBTX1JEX1BBWV9NMF9USU1FwqDCoMKgwqDCoMKgwqDCoMKg wqDCoCAweDEwMTBkCj4+ICsjZGVmaW5lIEhOUzNfUE1VX0VWVF9QUFNfUkRfUEFZX00xX1BBQ0tF VF9OVU3CoMKgwqDCoMKgwqDCoCAweDAwMTBlCj4+ICsjZGVmaW5lIEhOUzNfUE1VX0VWVF9QUFNf UkRfUEFZX00xX1RJTUXCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIDB4MTAxMGUKPj4gKyNkZWZpbmUg SE5TM19QTVVfRVZUX1BQU19XUl9QQVlfTTBfUEFDS0VUX05VTcKgwqDCoMKgwqDCoMKgIDB4MDAx MGYKPj4gKyNkZWZpbmUgSE5TM19QTVVfRVZUX1BQU19XUl9QQVlfTTBfVElNRcKgwqDCoMKgwqDC oMKgwqDCoMKgwqAgMHgxMDEwZgo+PiArI2RlZmluZSBITlMzX1BNVV9FVlRfUFBTX1dSX1BBWV9N MV9QQUNLRVRfTlVNwqDCoMKgwqDCoMKgwqAgMHgwMDExMAo+PiArI2RlZmluZSBITlMzX1BNVV9F VlRfUFBTX1dSX1BBWV9NMV9USU1FwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCAweDEwMTEwCj4+ICsj ZGVmaW5lIEhOUzNfUE1VX0VWVF9QUFNfTklDUk9IX1RYX1BSRV9QQUNLRVRfTlVNwqDCoMKgIDB4 MDAxMTEKPj4gKyNkZWZpbmUgSE5TM19QTVVfRVZUX1BQU19OSUNST0hfVFhfUFJFX1RJTUXCoMKg wqDCoMKgwqDCoCAweDEwMTExCj4+ICsjZGVmaW5lIEhOUzNfUE1VX0VWVF9QUFNfTklDUk9IX1JY X1BSRV9QQUNLRVRfTlVNwqDCoMKgIDB4MDAxMTIKPj4gKyNkZWZpbmUgSE5TM19QTVVfRVZUX1BQ U19OSUNST0hfUlhfUFJFX1RJTUXCoMKgwqDCoMKgwqDCoCAweDEwMTEyCj4+ICsKPj4gKy8qIGxh dGVuY3kgZXZlbnRzICovCj4+ICsjZGVmaW5lIEhOUzNfUE1VX0VWVF9ETFlfVFhfUFVTSF9USU1F wqDCoMKgwqDCoMKgwqDCoMKgwqDCoCAweDAwMjAyCj4+ICsjZGVmaW5lIEhOUzNfUE1VX0VWVF9E TFlfVFhfUFVTSF9QQUNLRVRfTlVNwqDCoMKgwqDCoMKgwqAgMHgxMDIwMgo+PiArI2RlZmluZSBI TlMzX1BNVV9FVlRfRExZX1RYX1RJTUXCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIDB4MDAyMDQKPj4g KyNkZWZpbmUgSE5TM19QTVVfRVZUX0RMWV9UWF9QQUNLRVRfTlVNwqDCoMKgwqDCoMKgwqDCoMKg wqDCoCAweDEwMjA0Cj4+ICsjZGVmaW5lIEhOUzNfUE1VX0VWVF9ETFlfU1NVX1RYX05JQ19USU1F wqDCoMKgwqDCoMKgwqAgMHgwMDIwNgo+PiArI2RlZmluZSBITlMzX1BNVV9FVlRfRExZX1NTVV9U WF9OSUNfUEFDS0VUX05VTcKgwqDCoMKgwqDCoMKgIDB4MTAyMDYKPj4gKyNkZWZpbmUgSE5TM19Q TVVfRVZUX0RMWV9TU1VfVFhfUk9DRV9USU1FwqDCoMKgwqDCoMKgwqAgMHgwMDIwNwo+PiArI2Rl ZmluZSBITlMzX1BNVV9FVlRfRExZX1NTVV9UWF9ST0NFX1BBQ0tFVF9OVU3CoMKgwqDCoMKgwqDC oCAweDEwMjA3Cj4+ICsjZGVmaW5lIEhOUzNfUE1VX0VWVF9ETFlfU1NVX1JYX05JQ19USU1FwqDC oMKgwqDCoMKgwqAgMHgwMDIwOAo+PiArI2RlZmluZSBITlMzX1BNVV9FVlRfRExZX1NTVV9SWF9O SUNfUEFDS0VUX05VTcKgwqDCoMKgwqDCoMKgIDB4MTAyMDgKPj4gKyNkZWZpbmUgSE5TM19QTVVf RVZUX0RMWV9TU1VfUlhfUk9DRV9USU1FwqDCoMKgwqDCoMKgwqAgMHgwMDIwOQo+PiArI2RlZmlu ZSBITlMzX1BNVV9FVlRfRExZX1NTVV9SWF9ST0NFX1BBQ0tFVF9OVU3CoMKgwqDCoMKgwqDCoCAw eDEwMjA5Cj4+ICsjZGVmaW5lIEhOUzNfUE1VX0VWVF9ETFlfUlBVX1RJTUXCoMKgwqDCoMKgwqDC oMKgwqDCoMKgIDB4MDAyMGUKPj4gKyNkZWZpbmUgSE5TM19QTVVfRVZUX0RMWV9SUFVfUEFDS0VU X05VTcKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgMHgxMDIwZQo+PiArI2RlZmluZSBITlMzX1BNVV9F VlRfRExZX1RQVV9USU1FwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCAweDAwMjBmCj4+ICsjZGVmaW5l IEhOUzNfUE1VX0VWVF9ETFlfVFBVX1BBQ0tFVF9OVU3CoMKgwqDCoMKgwqDCoMKgwqDCoMKgIDB4 MTAyMGYKPj4gKyNkZWZpbmUgSE5TM19QTVVfRVZUX0RMWV9SUEVfVElNRcKgwqDCoMKgwqDCoMKg wqDCoMKgwqAgMHgwMDIxMAo+PiArI2RlZmluZSBITlMzX1BNVV9FVlRfRExZX1JQRV9QQUNLRVRf TlVNwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCAweDEwMjEwCj4+ICsjZGVmaW5lIEhOUzNfUE1VX0VW VF9ETFlfVFBFX1RJTUXCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIDB4MDAyMTEKPj4gKyNkZWZpbmUg SE5TM19QTVVfRVZUX0RMWV9UUEVfUEFDS0VUX05VTcKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgMHgx MDIxMQo+PiArI2RlZmluZSBITlMzX1BNVV9FVlRfRExZX1RQRV9QVVNIX1RJTUXCoMKgwqDCoMKg wqDCoMKgwqDCoMKgIDB4MDAyMTIKPj4gKyNkZWZpbmUgSE5TM19QTVVfRVZUX0RMWV9UUEVfUFVT SF9QQUNLRVRfTlVNwqDCoMKgwqDCoMKgwqAgMHgxMDIxMgo+PiArI2RlZmluZSBITlMzX1BNVV9F VlRfRExZX1dSX0ZCRF9USU1FwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCAweDAwMjEzCj4+ICsjZGVm aW5lIEhOUzNfUE1VX0VWVF9ETFlfV1JfRkJEX1BBQ0tFVF9OVU3CoMKgwqDCoMKgwqDCoCAweDEw MjEzCj4+ICsjZGVmaW5lIEhOUzNfUE1VX0VWVF9ETFlfV1JfRUJEX1RJTUXCoMKgwqDCoMKgwqDC oMKgwqDCoMKgIDB4MDAyMTQKPj4gKyNkZWZpbmUgSE5TM19QTVVfRVZUX0RMWV9XUl9FQkRfUEFD S0VUX05VTcKgwqDCoMKgwqDCoMKgIDB4MTAyMTQKPj4gKyNkZWZpbmUgSE5TM19QTVVfRVZUX0RM WV9SRF9GQkRfVElNRcKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgMHgwMDIxNQo+PiArI2RlZmluZSBI TlMzX1BNVV9FVlRfRExZX1JEX0ZCRF9QQUNLRVRfTlVNwqDCoMKgwqDCoMKgwqAgMHgxMDIxNQo+ PiArI2RlZmluZSBITlMzX1BNVV9FVlRfRExZX1JEX0VCRF9USU1FwqDCoMKgwqDCoMKgwqDCoMKg wqDCoCAweDAwMjE2Cj4+ICsjZGVmaW5lIEhOUzNfUE1VX0VWVF9ETFlfUkRfRUJEX1BBQ0tFVF9O VU3CoMKgwqDCoMKgwqDCoCAweDEwMjE2Cj4+ICsjZGVmaW5lIEhOUzNfUE1VX0VWVF9ETFlfUkRf UEFZX00wX1RJTUXCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIDB4MDAyMTcKPj4gKyNkZWZpbmUgSE5T M19QTVVfRVZUX0RMWV9SRF9QQVlfTTBfUEFDS0VUX05VTcKgwqDCoMKgwqDCoMKgIDB4MTAyMTcK Pj4gKyNkZWZpbmUgSE5TM19QTVVfRVZUX0RMWV9SRF9QQVlfTTFfVElNRcKgwqDCoMKgwqDCoMKg wqDCoMKgwqAgMHgwMDIxOAo+PiArI2RlZmluZSBITlMzX1BNVV9FVlRfRExZX1JEX1BBWV9NMV9Q QUNLRVRfTlVNwqDCoMKgwqDCoMKgwqAgMHgxMDIxOAo+PiArI2RlZmluZSBITlMzX1BNVV9FVlRf RExZX1dSX1BBWV9NMF9USU1FwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCAweDAwMjE5Cj4+ICsjZGVm aW5lIEhOUzNfUE1VX0VWVF9ETFlfV1JfUEFZX00wX1BBQ0tFVF9OVU3CoMKgwqDCoMKgwqDCoCAw eDEwMjE5Cj4+ICsjZGVmaW5lIEhOUzNfUE1VX0VWVF9ETFlfV1JfUEFZX00xX1RJTUXCoMKgwqDC oMKgwqDCoMKgwqDCoMKgIDB4MDAyMWEKPj4gKyNkZWZpbmUgSE5TM19QTVVfRVZUX0RMWV9XUl9Q QVlfTTFfUEFDS0VUX05VTcKgwqDCoMKgwqDCoMKgIDB4MTAyMWEKPj4gKyNkZWZpbmUgSE5TM19Q TVVfRVZUX0RMWV9NU0lYX1dSSVRFX1RJTUXCoMKgwqDCoMKgwqDCoCAweDAwMjFjCj4+ICsjZGVm aW5lIEhOUzNfUE1VX0VWVF9ETFlfTVNJWF9XUklURV9QQUNLRVRfTlVNwqDCoMKgwqDCoMKgwqAg MHgxMDIxYwo+PiArCj4+ICsvKiBpbnRlcnJ1cHQgcmF0ZSBldmVudHMgKi8KPj4gKyNkZWZpbmUg SE5TM19QTVVfRVZUX1BQU19NU0lYX05JQ19JTlRSX05VTcKgwqDCoMKgwqDCoMKgIDB4MDAzMDAK Pj4gKyNkZWZpbmUgSE5TM19QTVVfRVZUX1BQU19NU0lYX05JQ19USU1FwqDCoMKgwqDCoMKgwqDC oMKgwqDCoCAweDEwMzAwCj4+ICsKPj4gKy8qIGZpbHRlciBtb2RlIHN1cHBvcnRlZCBieSBlYWNo IGJhbmR3aWR0aCBldmVudCAqLwo+PiArI2RlZmluZSBITlMzX1BNVV9GSUxURVJfQldfU1NVX0VH VcKgwqDCoMKgwqDCoMKgIDB4MDcKPj4gKyNkZWZpbmUgSE5TM19QTVVfRklMVEVSX0JXX1NTVV9S UFXCoMKgwqDCoMKgwqDCoCAweDFmCj4+ICsjZGVmaW5lIEhOUzNfUE1VX0ZJTFRFUl9CV19TU1Vf Uk9DRcKgwqDCoMKgwqDCoMKgIDB4MGYKPj4gKyNkZWZpbmUgSE5TM19QTVVfRklMVEVSX0JXX1JP Q0VfU1NVwqDCoMKgwqDCoMKgwqAgMHgwZgo+PiArI2RlZmluZSBITlMzX1BNVV9GSUxURVJfQldf VFBVX1NTVcKgwqDCoMKgwqDCoMKgIDB4MWYKPj4gKyNkZWZpbmUgSE5TM19QTVVfRklMVEVSX0JX X1JQVV9SQ0JSWMKgwqDCoMKgwqDCoMKgIDB4MTEKPj4gKyNkZWZpbmUgSE5TM19QTVVfRklMVEVS X0JXX1JDQlRYX1RYU0NIwqDCoMKgwqDCoMKgwqAgMHgxMQo+PiArI2RlZmluZSBITlMzX1BNVV9G SUxURVJfQldfV1JfRkJEwqDCoMKgwqDCoMKgwqAgMHgxYgo+PiArI2RlZmluZSBITlMzX1BNVV9G SUxURVJfQldfV1JfRUJEwqDCoMKgwqDCoMKgwqAgMHgxMQo+PiArI2RlZmluZSBITlMzX1BNVV9G SUxURVJfQldfUkRfRkJEwqDCoMKgwqDCoMKgwqAgMHgwMQo+PiArI2RlZmluZSBITlMzX1BNVV9G SUxURVJfQldfUkRfRUJEwqDCoMKgwqDCoMKgwqAgMHgxYgo+PiArI2RlZmluZSBITlMzX1BNVV9G SUxURVJfQldfUkRfUEFZX00wwqDCoMKgwqDCoMKgwqAgMHgwMQo+PiArI2RlZmluZSBITlMzX1BN VV9GSUxURVJfQldfUkRfUEFZX00xwqDCoMKgwqDCoMKgwqAgMHgwMQo+PiArI2RlZmluZSBITlMz X1BNVV9GSUxURVJfQldfV1JfUEFZX00wwqDCoMKgwqDCoMKgwqAgMHgwMQo+PiArI2RlZmluZSBI TlMzX1BNVV9GSUxURVJfQldfV1JfUEFZX00xwqDCoMKgwqDCoMKgwqAgMHgwMQo+PiArCj4+ICsv KiBmaWx0ZXIgbW9kZSBzdXBwb3J0ZWQgYnkgZWFjaCBwYWNrZXQgcmF0ZSBldmVudCAqLwo+PiAr I2RlZmluZSBITlMzX1BNVV9GSUxURVJfUFBTX0lHVV9TU1XCoMKgwqDCoMKgwqDCoCAweDA3Cj4+ ICsjZGVmaW5lIEhOUzNfUE1VX0ZJTFRFUl9QUFNfU1NVX0VHVcKgwqDCoMKgwqDCoMKgIDB4MDcK Pj4gKyNkZWZpbmUgSE5TM19QTVVfRklMVEVSX1BQU19TU1VfUlBVwqDCoMKgwqDCoMKgwqAgMHgx Zgo+PiArI2RlZmluZSBITlMzX1BNVV9GSUxURVJfUFBTX1NTVV9ST0NFwqDCoMKgwqDCoMKgwqAg MHgwZgo+PiArI2RlZmluZSBITlMzX1BNVV9GSUxURVJfUFBTX1JPQ0VfU1NVwqDCoMKgwqDCoMKg wqAgMHgwZgo+PiArI2RlZmluZSBITlMzX1BNVV9GSUxURVJfUFBTX1RQVV9TU1XCoMKgwqDCoMKg wqDCoCAweDFmCj4+ICsjZGVmaW5lIEhOUzNfUE1VX0ZJTFRFUl9QUFNfUlBVX1JDQlJYwqDCoMKg wqDCoMKgwqAgMHgxMQo+PiArI2RlZmluZSBITlMzX1BNVV9GSUxURVJfUFBTX1JDQlRYX1RQVcKg wqDCoMKgwqDCoMKgIDB4MWYKPj4gKyNkZWZpbmUgSE5TM19QTVVfRklMVEVSX1BQU19SQ0JUWF9U WFNDSMKgwqDCoMKgwqDCoMKgIDB4MTEKPj4gKyNkZWZpbmUgSE5TM19QTVVfRklMVEVSX1BQU19X Ul9GQkTCoMKgwqDCoMKgwqDCoCAweDFiCj4+ICsjZGVmaW5lIEhOUzNfUE1VX0ZJTFRFUl9QUFNf V1JfRUJEwqDCoMKgwqDCoMKgwqAgMHgxMQo+PiArI2RlZmluZSBITlMzX1BNVV9GSUxURVJfUFBT X1JEX0ZCRMKgwqDCoMKgwqDCoMKgIDB4MDEKPj4gKyNkZWZpbmUgSE5TM19QTVVfRklMVEVSX1BQ U19SRF9FQkTCoMKgwqDCoMKgwqDCoCAweDFiCj4+ICsjZGVmaW5lIEhOUzNfUE1VX0ZJTFRFUl9Q UFNfUkRfUEFZX00wwqDCoMKgwqDCoMKgwqAgMHgwMQo+PiArI2RlZmluZSBITlMzX1BNVV9GSUxU RVJfUFBTX1JEX1BBWV9NMcKgwqDCoMKgwqDCoMKgIDB4MDEKPj4gKyNkZWZpbmUgSE5TM19QTVVf RklMVEVSX1BQU19XUl9QQVlfTTDCoMKgwqDCoMKgwqDCoCAweDAxCj4+ICsjZGVmaW5lIEhOUzNf UE1VX0ZJTFRFUl9QUFNfV1JfUEFZX00xwqDCoMKgwqDCoMKgwqAgMHgwMQo+PiArI2RlZmluZSBI TlMzX1BNVV9GSUxURVJfUFBTX05JQ1JPSF9UWF9QUkXCoMKgwqAgMHgwMQo+PiArI2RlZmluZSBI TlMzX1BNVV9GSUxURVJfUFBTX05JQ1JPSF9SWF9QUkXCoMKgwqAgMHgwMQo+PiArCj4+ICsvKiBm aWx0ZXIgbW9kZSBzdXBwb3J0ZWQgYnkgZWFjaCBsYXRlbmN5IGV2ZW50ICovCj4+ICsjZGVmaW5l IEhOUzNfUE1VX0ZJTFRFUl9ETFlfVFhfUFVTSMKgwqDCoMKgwqDCoMKgIDB4MDEKPj4gKyNkZWZp bmUgSE5TM19QTVVfRklMVEVSX0RMWV9UWMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgMHgwMQo+PiAr I2RlZmluZSBITlMzX1BNVV9GSUxURVJfRExZX1NTVV9UWF9OSUPCoMKgwqDCoMKgwqDCoCAweDA3 Cj4+ICsjZGVmaW5lIEhOUzNfUE1VX0ZJTFRFUl9ETFlfU1NVX1RYX1JPQ0XCoMKgwqDCoMKgwqDC oCAweDA3Cj4+ICsjZGVmaW5lIEhOUzNfUE1VX0ZJTFRFUl9ETFlfU1NVX1JYX05JQ8KgwqDCoMKg wqDCoMKgIDB4MDcKPj4gKyNkZWZpbmUgSE5TM19QTVVfRklMVEVSX0RMWV9TU1VfUlhfUk9DRcKg wqDCoMKgwqDCoMKgIDB4MDcKPj4gKyNkZWZpbmUgSE5TM19QTVVfRklMVEVSX0RMWV9SUFXCoMKg wqDCoMKgwqDCoMKgwqDCoMKgIDB4MTEKPj4gKyNkZWZpbmUgSE5TM19QTVVfRklMVEVSX0RMWV9U UFXCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIDB4MWYKPj4gKyNkZWZpbmUgSE5TM19QTVVfRklMVEVS X0RMWV9SUEXCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIDB4MDEKPj4gKyNkZWZpbmUgSE5TM19QTVVf RklMVEVSX0RMWV9UUEXCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIDB4MGIKPj4gKyNkZWZpbmUgSE5T M19QTVVfRklMVEVSX0RMWV9UUEVfUFVTSMKgwqDCoMKgwqDCoMKgIDB4MWIKPj4gKyNkZWZpbmUg SE5TM19QTVVfRklMVEVSX0RMWV9XUl9GQkTCoMKgwqDCoMKgwqDCoCAweDFiCj4+ICsjZGVmaW5l IEhOUzNfUE1VX0ZJTFRFUl9ETFlfV1JfRUJEwqDCoMKgwqDCoMKgwqAgMHgxMQo+PiArI2RlZmlu ZSBITlMzX1BNVV9GSUxURVJfRExZX1JEX0ZCRMKgwqDCoMKgwqDCoMKgIDB4MDEKPj4gKyNkZWZp bmUgSE5TM19QTVVfRklMVEVSX0RMWV9SRF9FQkTCoMKgwqDCoMKgwqDCoCAweDFiCj4+ICsjZGVm aW5lIEhOUzNfUE1VX0ZJTFRFUl9ETFlfUkRfUEFZX00wwqDCoMKgwqDCoMKgwqAgMHgwMQo+PiAr I2RlZmluZSBITlMzX1BNVV9GSUxURVJfRExZX1JEX1BBWV9NMcKgwqDCoMKgwqDCoMKgIDB4MDEK Pj4gKyNkZWZpbmUgSE5TM19QTVVfRklMVEVSX0RMWV9XUl9QQVlfTTDCoMKgwqDCoMKgwqDCoCAw eDAxCj4+ICsjZGVmaW5lIEhOUzNfUE1VX0ZJTFRFUl9ETFlfV1JfUEFZX00xwqDCoMKgwqDCoMKg wqAgMHgwMQo+PiArI2RlZmluZSBITlMzX1BNVV9GSUxURVJfRExZX01TSVhfV1JJVEXCoMKgwqDC oMKgwqDCoCAweDAxCj4+ICsKPj4gKy8qIGZpbHRlciBtb2RlIHN1cHBvcnRlZCBieSBlYWNoIGlu dGVycnVwdCByYXRlIGV2ZW50ICovCj4+ICsjZGVmaW5lIEhOUzNfUE1VX0ZJTFRFUl9JTlRSX01T SVhfTklDwqDCoMKgwqDCoMKgwqAgMHgwMQo+PiArCj4+ICtlbnVtIGhuczNfcG11X2h3X2ZpbHRl cl9tb2RlIHsKPj4gK8KgwqDCoCBITlMzX1BNVV9IV19GSUxURVJfR0xPQkFMLAo+PiArwqDCoMKg IEhOUzNfUE1VX0hXX0ZJTFRFUl9QT1JULAo+PiArwqDCoMKgIEhOUzNfUE1VX0hXX0ZJTFRFUl9Q T1JUX1RDLAo+PiArwqDCoMKgIEhOUzNfUE1VX0hXX0ZJTFRFUl9GVU5DLAo+PiArwqDCoMKgIEhO UzNfUE1VX0hXX0ZJTFRFUl9GVU5DX1FVRVVFLAo+PiArwqDCoMKgIEhOUzNfUE1VX0hXX0ZJTFRF Ul9GVU5DX0lOVFIsCj4+ICt9Owo+PiArCj4+ICtzdHJ1Y3QgaG5zM19wbXVfZXZlbnRfYXR0ciB7 Cj4+ICvCoMKgwqAgdTMyIGV2ZW50Owo+PiArwqDCoMKgIHUxNiBmaWx0ZXJfc3VwcG9ydDsKPj4g K307Cj4+ICsKPj4gK3N0cnVjdCBobnMzX3BtdSB7Cj4+ICvCoMKgwqAgc3RydWN0IHBlcmZfZXZl bnQgKmh3X2V2ZW50c1tITlMzX1BNVV9NQVhfSFdfRVZFTlRTXTsKPj4gK8KgwqDCoCBzdHJ1Y3Qg aGxpc3Rfbm9kZSBub2RlOwo+PiArwqDCoMKgIHN0cnVjdCBwY2lfZGV2ICpwZGV2Owo+PiArwqDC oMKgIHN0cnVjdCBwbXUgcG11Owo+PiArwqDCoMKgIHZvaWQgX19pb21lbSAqYmFzZTsKPj4gK8Kg wqDCoCBpbnQgaXJxOwo+PiArwqDCoMKgIGludCBvbl9jcHU7Cj4+ICvCoMKgwqAgdTMyIGlkZW50 aWZpZXI7Cj4+ICvCoMKgwqAgdTMyIGh3X2Nsa19mcmVxOyAvKiBoYXJkd2FyZSBjbG9jayBmcmVx dWVuY3kgb2YgUE1VICovCj4+ICvCoMKgwqAgLyogbWF4aW11bSBhbmQgbWluaW11biBiZGYgYWxs b3dlZCBieSBQTVUgKi8KPj4gK8KgwqDCoCB1MTYgYmRmX21pbjsKPj4gK8KgwqDCoCB1MTYgYmRm X21heDsKPj4gK307Cj4+ICsKPj4gKyNkZWZpbmUgdG9faG5zM19wbXUocCnCoCAoY29udGFpbmVy X29mKChwKSwgc3RydWN0IGhuczNfcG11LCBwbXUpKQo+PiArI2RlZmluZSBhdHRyX3RvX2RhdHRy KGEpIChjb250YWluZXJfb2YoKGEpLCBzdHJ1Y3QgZGV2aWNlX2F0dHJpYnV0ZSwgYXR0cikpCj4+ ICsjZGVmaW5lIGRhdHRyX3RvX2VhdHRyKGQpIChjb250YWluZXJfb2YoKGQpLCBzdHJ1Y3QgZGV2 X2V4dF9hdHRyaWJ1dGUsIGF0dHIpKQo+PiArCj4+ICsjZGVmaW5lIEdFVF9QQ0lfREVWRk4oYmRm KcKgICgoYmRmKSAmIDB4ZmYpCj4+ICsKPj4gKyNkZWZpbmUgRklMVEVSX0NPTkRJVElPTl9QT1JU KHBvcnQpICgoMSA8PCAocG9ydCkpICYgMHhmZikKPj4gKyNkZWZpbmUgRklMVEVSX0NPTkRJVElP Tl9QT1JUX1RDKHBvcnQsIHRjKSAoKChwb3J0KSA8PCAzKSB8ICgodGMpICYgMHgwNykpCj4+ICsj ZGVmaW5lIEZJTFRFUl9DT05ESVRJT05fRlVOQ19JTlRSKGZ1bmMsIGludHIpICgoKGludHIpIDw8 IDgpIHwgKGZ1bmMpKQo+PiArCj4+ICsjZGVmaW5lIEJZVEVTX1RPX0JJVFMoYnl0ZXMpwqDCoMKg wqDCoMKgwqAgKChieXRlcykgKiA4KQo+IAo+IG5vdCB1c2VkCj4gCk9rLCB0aGFua3MuCgo+PiAr Cj4+ICsjZGVmaW5lIEhOUzNfUE1VX0ZJTFRFUl9BVFRSKF9uYW1lLCBfY29uZmlnLCBfc3RhcnQs IF9lbmQpwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCBcCj4+ICvCoMKgwqAgc3RhdGljIGlubGluZSB1 NjQgaG5zM19nZXRfIyNfbmFtZShzdHJ1Y3QgcGVyZl9ldmVudCAqZXZlbnQpwqAgXAo+PiArwqDC oMKgIHvCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqAgXAo+PiArwqDCoMKgwqDCoMKgwqAgcmV0dXJuIEZJRUxEX0dFVChHRU5NQVNL X1VMTChfZW5kLCBfc3RhcnQpLMKgwqDCoMKgwqDCoMKgwqDCoMKgIFwKPj4gK8KgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgIGV2ZW50LT5hdHRyLl9jb25maWcpO8KgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoCBcCj4+ICvCoMKgwqAgfQo+PiArCj4+ICtITlMzX1BNVV9GSUxURVJf QVRUUihldmVudCwgY29uZmlnLCAwLCAxNik7Cj4+ICtITlMzX1BNVV9GSUxURVJfQVRUUihzdWJl dmVudCwgY29uZmlnLCAwLCA3KTsKPj4gK0hOUzNfUE1VX0ZJTFRFUl9BVFRSKGV2ZW50X3R5cGUs IGNvbmZpZywgOCwgMTUpOwo+PiArSE5TM19QTVVfRklMVEVSX0FUVFIoZXh0X2NvdW50ZXJfdXNl ZCwgY29uZmlnLCAxNiwgMTYpOwo+PiArSE5TM19QTVVfRklMVEVSX0FUVFIocmVhbF9ldmVudCwg Y29uZmlnLCAwLCAxNSk7Cj4+ICtITlMzX1BNVV9GSUxURVJfQVRUUihwb3J0LCBjb25maWcxLCAw LCAzKTsKPj4gK0hOUzNfUE1VX0ZJTFRFUl9BVFRSKHRjLCBjb25maWcxLCA0LCA3KTsKPj4gK0hO UzNfUE1VX0ZJTFRFUl9BVFRSKGJkZiwgY29uZmlnMSwgOCwgMjMpOwo+PiArSE5TM19QTVVfRklM VEVSX0FUVFIocXVldWUsIGNvbmZpZzEsIDI0LCAzOSk7Cj4+ICtITlMzX1BNVV9GSUxURVJfQVRU UihpbnRyLCBjb25maWcxLCA0MCwgNTEpOwo+PiArSE5TM19QTVVfRklMVEVSX0FUVFIoZ2xvYmFs LCBjb25maWcxLCA1MiwgNTIpOwo+PiArCj4+ICsjZGVmaW5lIEhOUzNfQldfRVZUX0JZVEVfTlVN KF9uYW1lKcKgwqDCoCAoJihzdHJ1Y3QgaG5zM19wbXVfZXZlbnRfYXR0cikge1wKPj4gK8KgwqDC oCBITlMzX1BNVV9FVlRfQldfIyNfbmFtZSMjX0JZVEVfTlVNLMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoCBcCj4+ICvCoMKgwqAgSE5TM19QTVVfRklMVEVSX0JXXyMjX25hbWV9KQo+PiAr I2RlZmluZSBITlMzX0JXX0VWVF9USU1FKF9uYW1lKcKgwqDCoMKgwqDCoMKgICgmKHN0cnVjdCBo bnMzX3BtdV9ldmVudF9hdHRyKSB7XAo+PiArwqDCoMKgIEhOUzNfUE1VX0VWVF9CV18jI19uYW1l IyNfVElNRSzCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCBcCj4+ICvCoMKg wqAgSE5TM19QTVVfRklMVEVSX0JXXyMjX25hbWV9KQo+PiArI2RlZmluZSBITlMzX1BQU19FVlRf UEFDS0VUX05VTShfbmFtZSnCoMKgwqAgKCYoc3RydWN0IGhuczNfcG11X2V2ZW50X2F0dHIpIHtc Cj4+ICvCoMKgwqAgSE5TM19QTVVfRVZUX1BQU18jI19uYW1lIyNfUEFDS0VUX05VTSzCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgXAo+PiArwqDCoMKgIEhOUzNfUE1VX0ZJTFRFUl9QUFNf IyNfbmFtZX0pCj4+ICsjZGVmaW5lIEhOUzNfUFBTX0VWVF9USU1FKF9uYW1lKcKgwqDCoCAoJihz dHJ1Y3QgaG5zM19wbXVfZXZlbnRfYXR0cikge1wKPj4gK8KgwqDCoCBITlMzX1BNVV9FVlRfUFBT XyMjX25hbWUjI19USU1FLMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCBcCj4+ICvCoMKg wqAgSE5TM19QTVVfRklMVEVSX1BQU18jI19uYW1lfSkKPj4gKyNkZWZpbmUgSE5TM19ETFlfRVZU X1RJTUUoX25hbWUpwqDCoMKgICgmKHN0cnVjdCBobnMzX3BtdV9ldmVudF9hdHRyKSB7XAo+PiAr wqDCoMKgIEhOUzNfUE1VX0VWVF9ETFlfIyNfbmFtZSMjX1RJTUUswqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgIFwKPj4gK8KgwqDCoCBITlMzX1BNVV9GSUxURVJfRExZXyMjX25hbWV9KQo+ PiArI2RlZmluZSBITlMzX0RMWV9FVlRfUEFDS0VUX05VTShfbmFtZSnCoMKgwqAgKCYoc3RydWN0 IGhuczNfcG11X2V2ZW50X2F0dHIpIHtcCj4+ICvCoMKgwqAgSE5TM19QTVVfRVZUX0RMWV8jI19u YW1lIyNfUEFDS0VUX05VTSzCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgXAo+PiArwqDC oMKgIEhOUzNfUE1VX0ZJTFRFUl9ETFlfIyNfbmFtZX0pCj4+ICsjZGVmaW5lIEhOUzNfSU5UUl9F VlRfSU5UUl9OVU0oX25hbWUpwqDCoMKgICgmKHN0cnVjdCBobnMzX3BtdV9ldmVudF9hdHRyKSB7 XAo+PiArwqDCoMKgIEhOUzNfUE1VX0VWVF9QUFNfIyNfbmFtZSMjX0lOVFJfTlVNLMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoCBcCj4+ICvCoMKgwqAgSE5TM19QTVVfRklMVEVSX0lOVFJf IyNfbmFtZX0pCj4+ICsjZGVmaW5lIEhOUzNfSU5UUl9FVlRfVElNRShfbmFtZSnCoMKgwqAgKCYo c3RydWN0IGhuczNfcG11X2V2ZW50X2F0dHIpIHtcCj4+ICvCoMKgwqAgSE5TM19QTVVfRVZUX1BQ U18jI19uYW1lIyNfVElNRSzCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgXAo+PiArwqDC oMKgIEhOUzNfUE1VX0ZJTFRFUl9JTlRSXyMjX25hbWV9KQo+PiArCj4+ICtzdGF0aWMgc3NpemVf dCBobnMzX3BtdV9mb3JtYXRfc2hvdyhzdHJ1Y3QgZGV2aWNlICpkZXYsCj4+ICvCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCBzdHJ1Y3QgZGV2aWNlX2F0dHJpYnV0ZSAqYXR0 ciwgY2hhciAqYnVmKQo+PiArewo+PiArwqDCoMKgIHN0cnVjdCBkZXZfZXh0X2F0dHJpYnV0ZSAq ZWF0dHI7Cj4+ICsKPj4gK8KgwqDCoCBlYXR0ciA9IGNvbnRhaW5lcl9vZihhdHRyLCBzdHJ1Y3Qg ZGV2X2V4dF9hdHRyaWJ1dGUsIGF0dHIpOwo+PiArCj4+ICvCoMKgwqAgcmV0dXJuIHN5c2ZzX2Vt aXQoYnVmLCAiJXNcbiIsIChjaGFyICopZWF0dHItPnZhcik7Cj4+ICt9Cj4+ICsKPj4gK3N0YXRp YyBzc2l6ZV90IGhuczNfcG11X2V2ZW50X3Nob3coc3RydWN0IGRldmljZSAqZGV2LAo+PiArwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIHN0cnVjdCBkZXZpY2VfYXR0cmlidXRl ICphdHRyLCBjaGFyICpidWYpCj4+ICt7Cj4+ICvCoMKgwqAgc3RydWN0IGhuczNfcG11X2V2ZW50 X2F0dHIgKmV2ZW50Owo+PiArwqDCoMKgIHN0cnVjdCBkZXZfZXh0X2F0dHJpYnV0ZSAqZWF0dHI7 Cj4+ICsKPj4gK8KgwqDCoCBlYXR0ciA9IGNvbnRhaW5lcl9vZihhdHRyLCBzdHJ1Y3QgZGV2X2V4 dF9hdHRyaWJ1dGUsIGF0dHIpOwo+PiArwqDCoMKgIGV2ZW50ID0gKHN0cnVjdCBobnMzX3BtdV9l dmVudF9hdHRyICopZWF0dHItPnZhcjsKPiAKPiBlYXR0ci0+dmFyIGlzIGEgdm9pZCAqLCBzbyBj YXN0aW5nIG5vdCByZXF1aXJlZAo+IApPaywgdGhhbmtzLgoKPj4gKwo+PiArwqDCoMKgIHJldHVy biBzeXNmc19lbWl0KGJ1ZiwgImNvbmZpZz0weCUwNXhcbiIsIGV2ZW50LT5ldmVudCk7Cj4+ICt9 Cj4+ICsKPj4gK3N0YXRpYyBzc2l6ZV90IGhuczNfcG11X2ZpbHRlcl9tb2RlX3Nob3coc3RydWN0 IGRldmljZSAqZGV2LAo+PiArwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oCBzdHJ1Y3QgZGV2aWNlX2F0dHJpYnV0ZSAqYXR0ciwKPj4gK8KgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqAgY2hhciAqYnVmKQo+PiArewo+PiArwqDCoMKgIHN0cnVjdCBo bnMzX3BtdV9ldmVudF9hdHRyICpldmVudDsKPj4gK8KgwqDCoCBzdHJ1Y3QgZGV2X2V4dF9hdHRy aWJ1dGUgKmVhdHRyOwo+PiArwqDCoMKgIGludCBsZW47Cj4+ICsKPj4gK8KgwqDCoCBlYXR0ciA9 IGNvbnRhaW5lcl9vZihhdHRyLCBzdHJ1Y3QgZGV2X2V4dF9hdHRyaWJ1dGUsIGF0dHIpOwo+PiAr wqDCoMKgIGV2ZW50ID0gKHN0cnVjdCBobnMzX3BtdV9ldmVudF9hdHRyICopZWF0dHItPnZhcjsK Pj4gKwo+PiArwqDCoMKgIGxlbiA9IHN5c2ZzX2VtaXRfYXQoYnVmLCAwLCAiZmlsdGVyIG1vZGUg c3VwcG9ydGVkOiAiKTsKPj4gK8KgwqDCoCBpZiAoZXZlbnQtPmZpbHRlcl9zdXBwb3J0ICYgSE5T M19QTVVfRklMVEVSX1NVUFBPUlRfR0xPQkFMKQo+PiArwqDCoMKgwqDCoMKgwqAgbGVuICs9IHN5 c2ZzX2VtaXRfYXQoYnVmLCBsZW4sICJnbG9iYWwgIik7Cj4+ICvCoMKgwqAgaWYgKGV2ZW50LT5m aWx0ZXJfc3VwcG9ydCAmIEhOUzNfUE1VX0ZJTFRFUl9TVVBQT1JUX1BPUlQpCj4+ICvCoMKgwqDC oMKgwqDCoCBsZW4gKz0gc3lzZnNfZW1pdF9hdChidWYsIGxlbiwgInBvcnQgIik7Cj4+ICvCoMKg wqAgaWYgKGV2ZW50LT5maWx0ZXJfc3VwcG9ydCAmIEhOUzNfUE1VX0ZJTFRFUl9TVVBQT1JUX1BP UlRfVEMpCj4+ICvCoMKgwqDCoMKgwqDCoCBsZW4gKz0gc3lzZnNfZW1pdF9hdChidWYsIGxlbiwg InBvcnQtdGMgIik7Cj4+ICvCoMKgwqAgaWYgKGV2ZW50LT5maWx0ZXJfc3VwcG9ydCAmIEhOUzNf UE1VX0ZJTFRFUl9TVVBQT1JUX0ZVTkMpCj4+ICvCoMKgwqDCoMKgwqDCoCBsZW4gKz0gc3lzZnNf ZW1pdF9hdChidWYsIGxlbiwgImZ1bmMgIik7Cj4+ICvCoMKgwqAgaWYgKGV2ZW50LT5maWx0ZXJf c3VwcG9ydCAmIEhOUzNfUE1VX0ZJTFRFUl9TVVBQT1JUX0ZVTkNfUVVFVUUpCj4+ICvCoMKgwqDC oMKgwqDCoCBsZW4gKz0gc3lzZnNfZW1pdF9hdChidWYsIGxlbiwgImZ1bmMtcXVldWUgIik7Cj4+ ICvCoMKgwqAgaWYgKGV2ZW50LT5maWx0ZXJfc3VwcG9ydCAmIEhOUzNfUE1VX0ZJTFRFUl9TVVBQ T1JUX0ZVTkNfSU5UUikKPj4gK8KgwqDCoMKgwqDCoMKgIGxlbiArPSBzeXNmc19lbWl0X2F0KGJ1 ZiwgbGVuLCAiZnVuYy1pbnRyIik7Cj4+ICsKPj4gK8KgwqDCoCBsZW4gKz0gc3lzZnNfZW1pdF9h dChidWYsIGxlbiwgIlxuIik7Cj4+ICsKPj4gK8KgwqDCoCByZXR1cm4gbGVuOwo+PiArfQo+PiAr Cj4+ICsjZGVmaW5lIEhOUzNfUE1VX0FUVFIoX25hbWUsIF9mdW5jLCBfY29uZmlnKcKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoCBcCj4+ICvCoMKgwqAgKCYoKHN0cnVjdCBkZXZfZXh0X2F0 dHJpYnV0ZVtdKSB7wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIFwKPj4gK8KgwqDCoMKg wqDCoMKgIHsgX19BVFRSKF9uYW1lLCAwNDQ0LCBfZnVuYywgTlVMTCksICh2b2lkICopX2NvbmZp ZyB9wqDCoMKgIFwKPj4gK8KgwqDCoCB9KVswXS5hdHRyLmF0dHIpCj4+ICsKPj4gKyNkZWZpbmUg SE5TM19QTVVfRk9STUFUX0FUVFIoX25hbWUsIF9mb3JtYXQpIFwKPj4gK8KgwqDCoCBITlMzX1BN VV9BVFRSKF9uYW1lLCBobnMzX3BtdV9mb3JtYXRfc2hvdywgKHZvaWQgKilfZm9ybWF0KQo+PiAr I2RlZmluZSBITlMzX1BNVV9FVkVOVF9BVFRSKF9uYW1lLCBfZXZlbnQpIFwKPj4gK8KgwqDCoCBI TlMzX1BNVV9BVFRSKF9uYW1lLCBobnMzX3BtdV9ldmVudF9zaG93LCAodm9pZCAqKV9ldmVudCkK Pj4gKyNkZWZpbmUgSE5TM19QTVVfRkxUX01PREVfQVRUUihfbmFtZSwgX2V2ZW50KSBcCj4+ICvC oMKgwqAgSE5TM19QTVVfQVRUUihfbmFtZSwgaG5zM19wbXVfZmlsdGVyX21vZGVfc2hvdywgKHZv aWQgKilfZXZlbnQpCj4+ICsKPj4gKyNkZWZpbmUgSE5TM19QTVVfQldfRVZUX1BBSVIoX25hbWUs IF9tYWNybykgXAo+PiArwqDCoMKgIEhOUzNfUE1VX0VWRU5UX0FUVFIoX25hbWUjI19ieXRlX251 bSwgSE5TM19CV19FVlRfQllURV9OVU0oX21hY3JvKSksIFwKPj4gK8KgwqDCoCBITlMzX1BNVV9F VkVOVF9BVFRSKF9uYW1lIyNfdGltZSwgSE5TM19CV19FVlRfVElNRShfbWFjcm8pKQo+PiArI2Rl ZmluZSBITlMzX1BNVV9QUFNfRVZUX1BBSVIoX25hbWUsIF9tYWNybykgXAo+PiArwqDCoMKgIEhO UzNfUE1VX0VWRU5UX0FUVFIoX25hbWUjI19wYWNrZXRfbnVtLCBITlMzX1BQU19FVlRfUEFDS0VU X05VTShfbWFjcm8pKSwgXAo+PiArwqDCoMKgIEhOUzNfUE1VX0VWRU5UX0FUVFIoX25hbWUjI190 aW1lLCBITlMzX1BQU19FVlRfVElNRShfbWFjcm8pKQo+PiArI2RlZmluZSBITlMzX1BNVV9ETFlf RVZUX1BBSVIoX25hbWUsIF9tYWNybykgXAo+PiArwqDCoMKgIEhOUzNfUE1VX0VWRU5UX0FUVFIo X25hbWUjI190aW1lLCBITlMzX0RMWV9FVlRfVElNRShfbWFjcm8pKSwgXAo+PiArwqDCoMKgIEhO UzNfUE1VX0VWRU5UX0FUVFIoX25hbWUjI19wYWNrZXRfbnVtLCBITlMzX0RMWV9FVlRfUEFDS0VU X05VTShfbWFjcm8pKQo+PiArI2RlZmluZSBITlMzX1BNVV9JTlRSX0VWVF9QQUlSKF9uYW1lLCBf bWFjcm8pIFwKPj4gK8KgwqDCoCBITlMzX1BNVV9FVkVOVF9BVFRSKF9uYW1lIyNfaW50cl9udW0s IEhOUzNfSU5UUl9FVlRfSU5UUl9OVU0oX21hY3JvKSksIFwKPj4gK8KgwqDCoCBITlMzX1BNVV9F VkVOVF9BVFRSKF9uYW1lIyNfdGltZSwgSE5TM19JTlRSX0VWVF9USU1FKF9tYWNybykpCj4+ICsK Pj4gKyNkZWZpbmUgSE5TM19QTVVfQldfRkxUX01PREVfUEFJUihfbmFtZSwgX21hY3JvKSBcCj4+ ICvCoMKgwqAgSE5TM19QTVVfRkxUX01PREVfQVRUUihfbmFtZSMjX2J5dGVfbnVtLCBITlMzX0JX X0VWVF9CWVRFX05VTShfbWFjcm8pKSwgXAo+PiArwqDCoMKgIEhOUzNfUE1VX0ZMVF9NT0RFX0FU VFIoX25hbWUjI190aW1lLCBITlMzX0JXX0VWVF9USU1FKF9tYWNybykpCj4+ICsjZGVmaW5lIEhO UzNfUE1VX1BQU19GTFRfTU9ERV9QQUlSKF9uYW1lLCBfbWFjcm8pIFwKPj4gK8KgwqDCoCBITlMz X1BNVV9GTFRfTU9ERV9BVFRSKF9uYW1lIyNfcGFja2V0X251bSwgSE5TM19QUFNfRVZUX1BBQ0tF VF9OVU0oX21hY3JvKSksIFwKPj4gK8KgwqDCoCBITlMzX1BNVV9GTFRfTU9ERV9BVFRSKF9uYW1l IyNfdGltZSwgSE5TM19QUFNfRVZUX1RJTUUoX21hY3JvKSkKPj4gKyNkZWZpbmUgSE5TM19QTVVf RExZX0ZMVF9NT0RFX1BBSVIoX25hbWUsIF9tYWNybykgXAo+PiArwqDCoMKgIEhOUzNfUE1VX0ZM VF9NT0RFX0FUVFIoX25hbWUjI190aW1lLCBITlMzX0RMWV9FVlRfVElNRShfbWFjcm8pKSwgXAo+ PiArwqDCoMKgIEhOUzNfUE1VX0ZMVF9NT0RFX0FUVFIoX25hbWUjI19wYWNrZXRfbnVtLCBITlMz X0RMWV9FVlRfUEFDS0VUX05VTShfbWFjcm8pKQo+PiArI2RlZmluZSBITlMzX1BNVV9JTlRSX0ZM VF9NT0RFX1BBSVIoX25hbWUsIF9tYWNybykgXAo+PiArwqDCoMKgIEhOUzNfUE1VX0ZMVF9NT0RF X0FUVFIoX25hbWUjI19pbnRyX251bSwgSE5TM19JTlRSX0VWVF9JTlRSX05VTShfbWFjcm8pKSwg XAo+PiArwqDCoMKgIEhOUzNfUE1VX0ZMVF9NT0RFX0FUVFIoX25hbWUjI190aW1lLCBITlMzX0lO VFJfRVZUX1RJTUUoX21hY3JvKSkKPj4gKwo+PiArc3RhdGljIHU4IGhuczNfcG11X2h3X2ZpbHRl cl9tb2Rlc1tdID0gewo+PiArwqDCoMKgIEhOUzNfUE1VX0hXX0ZJTFRFUl9HTE9CQUwsCj4+ICvC oMKgwqAgSE5TM19QTVVfSFdfRklMVEVSX1BPUlQsCj4+ICvCoMKgwqAgSE5TM19QTVVfSFdfRklM VEVSX1BPUlRfVEMsCj4+ICvCoMKgwqAgSE5TM19QTVVfSFdfRklMVEVSX0ZVTkMsCj4+ICvCoMKg wqAgSE5TM19QTVVfSFdfRklMVEVSX0ZVTkNfUVVFVUUsCj4+ICvCoMKgwqAgSE5TM19QTVVfSFdf RklMVEVSX0ZVTkNfSU5UUiwKPj4gK307Cj4+ICsKPj4gKyNkZWZpbmUgSE5TM19QTVVfU0VUX0hX X0ZJTFRFUihfaHdjLCBfbW9kZSkgXAo+PiArwqDCoMKgICgoX2h3YyktPmFkZHJfZmlsdGVycyA9 ICh2b2lkICopJmhuczNfcG11X2h3X2ZpbHRlcl9tb2Rlc1soX21vZGUpXSkKPj4gKwo+PiArc3Rh dGljIHNzaXplX3QgaWRlbnRpZmllcl9zaG93KHN0cnVjdCBkZXZpY2UgKmRldiwKPj4gK8KgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCBzdHJ1Y3QgZGV2aWNlX2F0dHJpYnV0ZSAq YXR0ciwgY2hhciAqYnVmKQo+PiArewo+PiArwqDCoMKgIHN0cnVjdCBobnMzX3BtdSAqaG5zM19w bXUgPSB0b19obnMzX3BtdShkZXZfZ2V0X2RydmRhdGEoZGV2KSk7Cj4+ICsKPj4gK8KgwqDCoCBy ZXR1cm4gc3lzZnNfZW1pdChidWYsICIweCV4XG4iLCBobnMzX3BtdS0+aWRlbnRpZmllcik7Cj4+ ICt9Cj4+ICtzdGF0aWMgREVWSUNFX0FUVFJfUk8oaWRlbnRpZmllcik7Cj4+ICsKPj4gK3N0YXRp YyBzc2l6ZV90IGNwdW1hc2tfc2hvdyhzdHJ1Y3QgZGV2aWNlICpkZXYsIHN0cnVjdCBkZXZpY2Vf YXR0cmlidXRlICphdHRyLAo+PiArwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIGNoYXIg KmJ1ZikKPj4gK3sKPj4gK8KgwqDCoCBzdHJ1Y3QgaG5zM19wbXUgKmhuczNfcG11ID0gdG9faG5z M19wbXUoZGV2X2dldF9kcnZkYXRhKGRldikpOwo+PiArCj4+ICvCoMKgwqAgcmV0dXJuIHN5c2Zz X2VtaXQoYnVmLCAiJWRcbiIsIGhuczNfcG11LT5vbl9jcHUpOwo+PiArfQo+PiArc3RhdGljIERF VklDRV9BVFRSX1JPKGNwdW1hc2spOwo+PiArCj4+ICtzdGF0aWMgc3NpemVfdCBiZGZfbWluX3No b3coc3RydWN0IGRldmljZSAqZGV2LCBzdHJ1Y3QgZGV2aWNlX2F0dHJpYnV0ZSAqYXR0ciwKPj4g K8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCBjaGFyICpidWYpCj4+ICt7Cj4+ICvCoMKg wqAgc3RydWN0IGhuczNfcG11ICpobnMzX3BtdSA9IHRvX2huczNfcG11KGRldl9nZXRfZHJ2ZGF0 YShkZXYpKTsKPj4gKwo+PiArwqDCoMKgIHJldHVybiBzeXNmc19lbWl0KGJ1ZiwgIjB4JTR4XG4i LCBobnMzX3BtdS0+YmRmX21pbik7Cj4+ICt9Cj4+ICtzdGF0aWMgREVWSUNFX0FUVFJfUk8oYmRm X21pbik7Cj4+ICsKPj4gK3N0YXRpYyBzc2l6ZV90IGJkZl9tYXhfc2hvdyhzdHJ1Y3QgZGV2aWNl ICpkZXYsIHN0cnVjdCBkZXZpY2VfYXR0cmlidXRlICphdHRyLAo+PiArwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgIGNoYXIgKmJ1ZikKPj4gK3sKPj4gK8KgwqDCoCBzdHJ1Y3QgaG5zM19w bXUgKmhuczNfcG11ID0gdG9faG5zM19wbXUoZGV2X2dldF9kcnZkYXRhKGRldikpOwo+PiArCj4+ ICvCoMKgwqAgcmV0dXJuIHN5c2ZzX2VtaXQoYnVmLCAiMHglNHhcbiIsIGhuczNfcG11LT5iZGZf bWF4KTsKPj4gK30KPj4gK3N0YXRpYyBERVZJQ0VfQVRUUl9STyhiZGZfbWF4KTsKPj4gKwo+PiAr c3RhdGljIHNzaXplX3QKPj4gK2h3X2Nsa19mcmVxX3Nob3coc3RydWN0IGRldmljZSAqZGV2LCBz dHJ1Y3QgZGV2aWNlX2F0dHJpYnV0ZSAqYXR0ciwgY2hhciAqYnVmKQo+IAo+IG5pdDogcGVvcGxl IGdlbmVyYWxseSBwcmVmZXIgdG8ga2VlcCByZXR1cm4gdHlwZSBvbiB0aGUgc2FtZSBsaW5lIGFz IGZ1bmN0aW9uIG5hbWUgYW5kIHRoZW4gc3BpbGwgbGluZXMgZm9yIHRoZSBhcmd1bWVudHMKPiAK T2suCgo+PiArewo+PiArwqDCoMKgIHN0cnVjdCBobnMzX3BtdSAqaG5zM19wbXUgPSB0b19obnMz X3BtdShkZXZfZ2V0X2RydmRhdGEoZGV2KSk7Cj4+ICsKPj4gK8KgwqDCoCByZXR1cm4gc3lzZnNf ZW1pdChidWYsICIldVxuIiwgaG5zM19wbXUtPmh3X2Nsa19mcmVxKTsKPj4gK30KPj4gK3N0YXRp YyBERVZJQ0VfQVRUUl9STyhod19jbGtfZnJlcSk7Cj4+ICsKPj4gK3N0YXRpYyBzdHJ1Y3QgYXR0 cmlidXRlICpobnMzX3BtdV9ldmVudHNfYXR0cltdID0gewo+PiArwqDCoMKgIC8qIGJhbmR3aWR0 aCBldmVudHMgKi8KPj4gK8KgwqDCoCBITlMzX1BNVV9CV19FVlRfUEFJUihid19zc3VfZWd1LCBT U1VfRUdVKSwKPj4gK8KgwqDCoCBITlMzX1BNVV9CV19FVlRfUEFJUihid19zc3VfcnB1LCBTU1Vf UlBVKSwKPj4gK8KgwqDCoCBITlMzX1BNVV9CV19FVlRfUEFJUihid19zc3Vfcm9jZSwgU1NVX1JP Q0UpLAo+PiArwqDCoMKgIEhOUzNfUE1VX0JXX0VWVF9QQUlSKGJ3X3JvY2Vfc3N1LCBST0NFX1NT VSksCj4+ICvCoMKgwqAgSE5TM19QTVVfQldfRVZUX1BBSVIoYndfdHB1X3NzdSwgVFBVX1NTVSks Cj4+ICvCoMKgwqAgSE5TM19QTVVfQldfRVZUX1BBSVIoYndfcnB1X3JjYnJ4LCBSUFVfUkNCUlgp LAo+PiArwqDCoMKgIEhOUzNfUE1VX0JXX0VWVF9QQUlSKGJ3X3JjYnR4X3R4c2NoLCBSQ0JUWF9U WFNDSCksCj4+ICvCoMKgwqAgSE5TM19QTVVfQldfRVZUX1BBSVIoYndfd3JfZmJkLCBXUl9GQkQp LAo+PiArwqDCoMKgIEhOUzNfUE1VX0JXX0VWVF9QQUlSKGJ3X3dyX2ViZCwgV1JfRUJEKSwKPj4g K8KgwqDCoCBITlMzX1BNVV9CV19FVlRfUEFJUihid19yZF9mYmQsIFJEX0ZCRCksCj4+ICvCoMKg wqAgSE5TM19QTVVfQldfRVZUX1BBSVIoYndfcmRfZWJkLCBSRF9FQkQpLAo+PiArwqDCoMKgIEhO UzNfUE1VX0JXX0VWVF9QQUlSKGJ3X3JkX3BheV9tMCwgUkRfUEFZX00wKSwKPj4gK8KgwqDCoCBI TlMzX1BNVV9CV19FVlRfUEFJUihid19yZF9wYXlfbTEsIFJEX1BBWV9NMSksCj4+ICvCoMKgwqAg SE5TM19QTVVfQldfRVZUX1BBSVIoYndfd3JfcGF5X20wLCBXUl9QQVlfTTApLAo+PiArwqDCoMKg IEhOUzNfUE1VX0JXX0VWVF9QQUlSKGJ3X3dyX3BheV9tMSwgV1JfUEFZX00xKSwKPj4gKwo+PiAr wqDCoMKgIC8qIHBhY2tldCByYXRlIGV2ZW50cyAqLwo+PiArwqDCoMKgIEhOUzNfUE1VX1BQU19F VlRfUEFJUihwcHNfaWd1X3NzdSwgSUdVX1NTVSksCj4+ICvCoMKgwqAgSE5TM19QTVVfUFBTX0VW VF9QQUlSKHBwc19zc3VfZWd1LCBTU1VfRUdVKSwKPj4gK8KgwqDCoCBITlMzX1BNVV9QUFNfRVZU X1BBSVIocHBzX3NzdV9ycHUsIFNTVV9SUFUpLAo+PiArwqDCoMKgIEhOUzNfUE1VX1BQU19FVlRf UEFJUihwcHNfc3N1X3JvY2UsIFNTVV9ST0NFKSwKPj4gK8KgwqDCoCBITlMzX1BNVV9QUFNfRVZU X1BBSVIocHBzX3JvY2Vfc3N1LCBST0NFX1NTVSksCj4+ICvCoMKgwqAgSE5TM19QTVVfUFBTX0VW VF9QQUlSKHBwc190cHVfc3N1LCBUUFVfU1NVKSwKPj4gK8KgwqDCoCBITlMzX1BNVV9QUFNfRVZU X1BBSVIocHBzX3JwdV9yY2JyeCwgUlBVX1JDQlJYKSwKPj4gK8KgwqDCoCBITlMzX1BNVV9QUFNf RVZUX1BBSVIocHBzX3JjYnR4X3RwdSwgUkNCVFhfVFBVKSwKPj4gK8KgwqDCoCBITlMzX1BNVV9Q UFNfRVZUX1BBSVIocHBzX3JjYnR4X3R4c2NoLCBSQ0JUWF9UWFNDSCksCj4+ICvCoMKgwqAgSE5T M19QTVVfUFBTX0VWVF9QQUlSKHBwc193cl9mYmQsIFdSX0ZCRCksCj4+ICvCoMKgwqAgSE5TM19Q TVVfUFBTX0VWVF9QQUlSKHBwc193cl9lYmQsIFdSX0VCRCksCj4+ICvCoMKgwqAgSE5TM19QTVVf UFBTX0VWVF9QQUlSKHBwc19yZF9mYmQsIFJEX0ZCRCksCj4+ICvCoMKgwqAgSE5TM19QTVVfUFBT X0VWVF9QQUlSKHBwc19yZF9lYmQsIFJEX0VCRCksCj4+ICvCoMKgwqAgSE5TM19QTVVfUFBTX0VW VF9QQUlSKHBwc19yZF9wYXlfbTAsIFJEX1BBWV9NMCksCj4+ICvCoMKgwqAgSE5TM19QTVVfUFBT X0VWVF9QQUlSKHBwc19yZF9wYXlfbTEsIFJEX1BBWV9NMSksCj4+ICvCoMKgwqAgSE5TM19QTVVf UFBTX0VWVF9QQUlSKHBwc193cl9wYXlfbTAsIFdSX1BBWV9NMCksCj4+ICvCoMKgwqAgSE5TM19Q TVVfUFBTX0VWVF9QQUlSKHBwc193cl9wYXlfbTEsIFdSX1BBWV9NMSksCj4+ICvCoMKgwqAgSE5T M19QTVVfUFBTX0VWVF9QQUlSKHBwc19pbnRyX25pY3JvaF90eF9wcmUsIE5JQ1JPSF9UWF9QUkUp LAo+PiArwqDCoMKgIEhOUzNfUE1VX1BQU19FVlRfUEFJUihwcHNfaW50cl9uaWNyb2hfcnhfcHJl LCBOSUNST0hfUlhfUFJFKSwKPj4gKwo+PiArwqDCoMKgIC8qIGxhdGVuY3kgZXZlbnRzICovCj4+ ICvCoMKgwqAgSE5TM19QTVVfRExZX0VWVF9QQUlSKGRseV90eF9wdXNoX3RvX21hYywgVFhfUFVT SCksCj4+ICvCoMKgwqAgSE5TM19QTVVfRExZX0VWVF9QQUlSKGRseV90eF9ub3JtYWxfdG9fbWFj LCBUWCksCj4+ICvCoMKgwqAgSE5TM19QTVVfRExZX0VWVF9QQUlSKGRseV9zc3VfdHhfdGhfbmlj LCBTU1VfVFhfTklDKSwKPj4gK8KgwqDCoCBITlMzX1BNVV9ETFlfRVZUX1BBSVIoZGx5X3NzdV90 eF90aF9yb2NlLCBTU1VfVFhfUk9DRSksCj4+ICvCoMKgwqAgSE5TM19QTVVfRExZX0VWVF9QQUlS KGRseV9zc3VfcnhfdGhfbmljLCBTU1VfUlhfTklDKSwKPj4gK8KgwqDCoCBITlMzX1BNVV9ETFlf RVZUX1BBSVIoZGx5X3NzdV9yeF90aF9yb2NlLCBTU1VfUlhfUk9DRSksCj4+ICvCoMKgwqAgSE5T M19QTVVfRExZX0VWVF9QQUlSKGRseV9ycHUsIFJQVSksCj4+ICvCoMKgwqAgSE5TM19QTVVfRExZ X0VWVF9QQUlSKGRseV90cHUsIFRQVSksCj4+ICvCoMKgwqAgSE5TM19QTVVfRExZX0VWVF9QQUlS KGRseV9ycGUsIFJQRSksCj4+ICvCoMKgwqAgSE5TM19QTVVfRExZX0VWVF9QQUlSKGRseV90cGVf bm9ybWFsLCBUUEUpLAo+PiArwqDCoMKgIEhOUzNfUE1VX0RMWV9FVlRfUEFJUihkbHlfdHBlX3B1 c2gsIFRQRV9QVVNIKSwKPj4gK8KgwqDCoCBITlMzX1BNVV9ETFlfRVZUX1BBSVIoZGx5X3dyX2Zi ZCwgV1JfRkJEKSwKPj4gK8KgwqDCoCBITlMzX1BNVV9ETFlfRVZUX1BBSVIoZGx5X3dyX2ViZCwg V1JfRUJEKSwKPj4gK8KgwqDCoCBITlMzX1BNVV9ETFlfRVZUX1BBSVIoZGx5X3JkX2ZiZCwgUkRf RkJEKSwKPj4gK8KgwqDCoCBITlMzX1BNVV9ETFlfRVZUX1BBSVIoZGx5X3JkX2ViZCwgUkRfRUJE KSwKPj4gK8KgwqDCoCBITlMzX1BNVV9ETFlfRVZUX1BBSVIoZGx5X3JkX3BheV9tMCwgUkRfUEFZ X00wKSwKPj4gK8KgwqDCoCBITlMzX1BNVV9ETFlfRVZUX1BBSVIoZGx5X3JkX3BheV9tMSwgUkRf UEFZX00xKSwKPj4gK8KgwqDCoCBITlMzX1BNVV9ETFlfRVZUX1BBSVIoZGx5X3dyX3BheV9tMCwg V1JfUEFZX00wKSwKPj4gK8KgwqDCoCBITlMzX1BNVV9ETFlfRVZUX1BBSVIoZGx5X3dyX3BheV9t MSwgV1JfUEFZX00xKSwKPj4gK8KgwqDCoCBITlMzX1BNVV9ETFlfRVZUX1BBSVIoZGx5X21zaXhf d3JpdGUsIE1TSVhfV1JJVEUpLAo+PiArCj4+ICvCoMKgwqAgLyogaW50ZXJydXB0IHJhdGUgZXZl bnRzICovCj4+ICvCoMKgwqAgSE5TM19QTVVfSU5UUl9FVlRfUEFJUihwcHNfaW50cl9tc2l4X25p YywgTVNJWF9OSUMpLAo+PiArCj4+ICvCoMKgwqAgTlVMTAo+PiArfTsKPj4gKwo+PiArc3RhdGlj IHN0cnVjdCBhdHRyaWJ1dGUgKmhuczNfcG11X2ZpbHRlcl9tb2RlX2F0dHJbXSA9IHsKPj4gK8Kg wqDCoCAvKiBiYW5kd2lkdGggZXZlbnRzICovCj4+ICvCoMKgwqAgSE5TM19QTVVfQldfRkxUX01P REVfUEFJUihid19zc3VfZWd1LCBTU1VfRUdVKSwKPj4gK8KgwqDCoCBITlMzX1BNVV9CV19GTFRf TU9ERV9QQUlSKGJ3X3NzdV9ycHUsIFNTVV9SUFUpLAo+PiArwqDCoMKgIEhOUzNfUE1VX0JXX0ZM VF9NT0RFX1BBSVIoYndfc3N1X3JvY2UsIFNTVV9ST0NFKSwKPj4gK8KgwqDCoCBITlMzX1BNVV9C V19GTFRfTU9ERV9QQUlSKGJ3X3JvY2Vfc3N1LCBST0NFX1NTVSksCj4+ICvCoMKgwqAgSE5TM19Q TVVfQldfRkxUX01PREVfUEFJUihid190cHVfc3N1LCBUUFVfU1NVKSwKPj4gK8KgwqDCoCBITlMz X1BNVV9CV19GTFRfTU9ERV9QQUlSKGJ3X3JwdV9yY2JyeCwgUlBVX1JDQlJYKSwKPj4gK8KgwqDC oCBITlMzX1BNVV9CV19GTFRfTU9ERV9QQUlSKGJ3X3JjYnR4X3R4c2NoLCBSQ0JUWF9UWFNDSCks Cj4+ICvCoMKgwqAgSE5TM19QTVVfQldfRkxUX01PREVfUEFJUihid193cl9mYmQsIFdSX0ZCRCks Cj4+ICvCoMKgwqAgSE5TM19QTVVfQldfRkxUX01PREVfUEFJUihid193cl9lYmQsIFdSX0VCRCks Cj4+ICvCoMKgwqAgSE5TM19QTVVfQldfRkxUX01PREVfUEFJUihid19yZF9mYmQsIFJEX0ZCRCks Cj4+ICvCoMKgwqAgSE5TM19QTVVfQldfRkxUX01PREVfUEFJUihid19yZF9lYmQsIFJEX0VCRCks Cj4+ICvCoMKgwqAgSE5TM19QTVVfQldfRkxUX01PREVfUEFJUihid19yZF9wYXlfbTAsIFJEX1BB WV9NMCksCj4+ICvCoMKgwqAgSE5TM19QTVVfQldfRkxUX01PREVfUEFJUihid19yZF9wYXlfbTEs IFJEX1BBWV9NMSksCj4+ICvCoMKgwqAgSE5TM19QTVVfQldfRkxUX01PREVfUEFJUihid193cl9w YXlfbTAsIFdSX1BBWV9NMCksCj4+ICvCoMKgwqAgSE5TM19QTVVfQldfRkxUX01PREVfUEFJUihi d193cl9wYXlfbTEsIFdSX1BBWV9NMSksCj4+ICsKPj4gK8KgwqDCoCAvKiBwYWNrZXQgcmF0ZSBl dmVudHMgKi8KPj4gK8KgwqDCoCBITlMzX1BNVV9QUFNfRkxUX01PREVfUEFJUihwcHNfaWd1X3Nz dSwgSUdVX1NTVSksCj4+ICvCoMKgwqAgSE5TM19QTVVfUFBTX0ZMVF9NT0RFX1BBSVIocHBzX3Nz dV9lZ3UsIFNTVV9FR1UpLAo+PiArwqDCoMKgIEhOUzNfUE1VX1BQU19GTFRfTU9ERV9QQUlSKHBw c19zc3VfcnB1LCBTU1VfUlBVKSwKPj4gK8KgwqDCoCBITlMzX1BNVV9QUFNfRkxUX01PREVfUEFJ UihwcHNfc3N1X3JvY2UsIFNTVV9ST0NFKSwKPj4gK8KgwqDCoCBITlMzX1BNVV9QUFNfRkxUX01P REVfUEFJUihwcHNfcm9jZV9zc3UsIFJPQ0VfU1NVKSwKPj4gK8KgwqDCoCBITlMzX1BNVV9QUFNf RkxUX01PREVfUEFJUihwcHNfdHB1X3NzdSwgVFBVX1NTVSksCj4+ICvCoMKgwqAgSE5TM19QTVVf UFBTX0ZMVF9NT0RFX1BBSVIocHBzX3JwdV9yY2JyeCwgUlBVX1JDQlJYKSwKPj4gK8KgwqDCoCBI TlMzX1BNVV9QUFNfRkxUX01PREVfUEFJUihwcHNfcmNidHhfdHB1LCBSQ0JUWF9UUFUpLAo+PiAr wqDCoMKgIEhOUzNfUE1VX1BQU19GTFRfTU9ERV9QQUlSKHBwc19yY2J0eF90eHNjaCwgUkNCVFhf VFhTQ0gpLAo+PiArwqDCoMKgIEhOUzNfUE1VX1BQU19GTFRfTU9ERV9QQUlSKHBwc193cl9mYmQs IFdSX0ZCRCksCj4+ICvCoMKgwqAgSE5TM19QTVVfUFBTX0ZMVF9NT0RFX1BBSVIocHBzX3dyX2Vi ZCwgV1JfRUJEKSwKPj4gK8KgwqDCoCBITlMzX1BNVV9QUFNfRkxUX01PREVfUEFJUihwcHNfcmRf ZmJkLCBSRF9GQkQpLAo+PiArwqDCoMKgIEhOUzNfUE1VX1BQU19GTFRfTU9ERV9QQUlSKHBwc19y ZF9lYmQsIFJEX0VCRCksCj4+ICvCoMKgwqAgSE5TM19QTVVfUFBTX0ZMVF9NT0RFX1BBSVIocHBz X3JkX3BheV9tMCwgUkRfUEFZX00wKSwKPj4gK8KgwqDCoCBITlMzX1BNVV9QUFNfRkxUX01PREVf UEFJUihwcHNfcmRfcGF5X20xLCBSRF9QQVlfTTEpLAo+PiArwqDCoMKgIEhOUzNfUE1VX1BQU19G TFRfTU9ERV9QQUlSKHBwc193cl9wYXlfbTAsIFdSX1BBWV9NMCksCj4+ICvCoMKgwqAgSE5TM19Q TVVfUFBTX0ZMVF9NT0RFX1BBSVIocHBzX3dyX3BheV9tMSwgV1JfUEFZX00xKSwKPj4gK8KgwqDC oCBITlMzX1BNVV9QUFNfRkxUX01PREVfUEFJUihwcHNfaW50cl9uaWNyb2hfdHhfcHJlLCBOSUNS T0hfVFhfUFJFKSwKPj4gK8KgwqDCoCBITlMzX1BNVV9QUFNfRkxUX01PREVfUEFJUihwcHNfaW50 cl9uaWNyb2hfcnhfcHJlLCBOSUNST0hfUlhfUFJFKSwKPj4gKwo+PiArwqDCoMKgIC8qIGxhdGVu Y3kgZXZlbnRzICovCj4+ICvCoMKgwqAgSE5TM19QTVVfRExZX0ZMVF9NT0RFX1BBSVIoZGx5X3R4 X3B1c2hfdG9fbWFjLCBUWF9QVVNIKSwKPj4gK8KgwqDCoCBITlMzX1BNVV9ETFlfRkxUX01PREVf UEFJUihkbHlfdHhfbm9ybWFsX3RvX21hYywgVFgpLAo+PiArwqDCoMKgIEhOUzNfUE1VX0RMWV9G TFRfTU9ERV9QQUlSKGRseV9zc3VfdHhfdGhfbmljLCBTU1VfVFhfTklDKSwKPj4gK8KgwqDCoCBI TlMzX1BNVV9ETFlfRkxUX01PREVfUEFJUihkbHlfc3N1X3R4X3RoX3JvY2UsIFNTVV9UWF9ST0NF KSwKPj4gK8KgwqDCoCBITlMzX1BNVV9ETFlfRkxUX01PREVfUEFJUihkbHlfc3N1X3J4X3RoX25p YywgU1NVX1JYX05JQyksCj4+ICvCoMKgwqAgSE5TM19QTVVfRExZX0ZMVF9NT0RFX1BBSVIoZGx5 X3NzdV9yeF90aF9yb2NlLCBTU1VfUlhfUk9DRSksCj4+ICvCoMKgwqAgSE5TM19QTVVfRExZX0ZM VF9NT0RFX1BBSVIoZGx5X3JwdSwgUlBVKSwKPj4gK8KgwqDCoCBITlMzX1BNVV9ETFlfRkxUX01P REVfUEFJUihkbHlfdHB1LCBUUFUpLAo+PiArwqDCoMKgIEhOUzNfUE1VX0RMWV9GTFRfTU9ERV9Q QUlSKGRseV9ycGUsIFJQRSksCj4+ICvCoMKgwqAgSE5TM19QTVVfRExZX0ZMVF9NT0RFX1BBSVIo ZGx5X3RwZV9ub3JtYWwsIFRQRSksCj4+ICvCoMKgwqAgSE5TM19QTVVfRExZX0ZMVF9NT0RFX1BB SVIoZGx5X3RwZV9wdXNoLCBUUEVfUFVTSCksCj4+ICvCoMKgwqAgSE5TM19QTVVfRExZX0ZMVF9N T0RFX1BBSVIoZGx5X3dyX2ZiZCwgV1JfRkJEKSwKPj4gK8KgwqDCoCBITlMzX1BNVV9ETFlfRkxU X01PREVfUEFJUihkbHlfd3JfZWJkLCBXUl9FQkQpLAo+PiArwqDCoMKgIEhOUzNfUE1VX0RMWV9G TFRfTU9ERV9QQUlSKGRseV9yZF9mYmQsIFJEX0ZCRCksCj4+ICvCoMKgwqAgSE5TM19QTVVfRExZ X0ZMVF9NT0RFX1BBSVIoZGx5X3JkX2ViZCwgUkRfRUJEKSwKPj4gK8KgwqDCoCBITlMzX1BNVV9E TFlfRkxUX01PREVfUEFJUihkbHlfcmRfcGF5X20wLCBSRF9QQVlfTTApLAo+PiArwqDCoMKgIEhO UzNfUE1VX0RMWV9GTFRfTU9ERV9QQUlSKGRseV9yZF9wYXlfbTEsIFJEX1BBWV9NMSksCj4+ICvC oMKgwqAgSE5TM19QTVVfRExZX0ZMVF9NT0RFX1BBSVIoZGx5X3dyX3BheV9tMCwgV1JfUEFZX00w KSwKPj4gK8KgwqDCoCBITlMzX1BNVV9ETFlfRkxUX01PREVfUEFJUihkbHlfd3JfcGF5X20xLCBX Ul9QQVlfTTEpLAo+PiArwqDCoMKgIEhOUzNfUE1VX0RMWV9GTFRfTU9ERV9QQUlSKGRseV9tc2l4 X3dyaXRlLCBNU0lYX1dSSVRFKSwKPj4gKwo+PiArwqDCoMKgIC8qIGludGVycnVwdCByYXRlIGV2 ZW50cyAqLwo+PiArwqDCoMKgIEhOUzNfUE1VX0lOVFJfRkxUX01PREVfUEFJUihwcHNfaW50cl9t c2l4X25pYywgTVNJWF9OSUMpLAo+PiArCj4+ICvCoMKgwqAgTlVMTAo+PiArfTsKPj4gKwo+PiAr c3RhdGljIHN0cnVjdCBhdHRyaWJ1dGVfZ3JvdXAgaG5zM19wbXVfZXZlbnRzX2dyb3VwID0gewo+ PiArwqDCoMKgIC5uYW1lID0gImV2ZW50cyIsCj4+ICvCoMKgwqAgLmF0dHJzID0gaG5zM19wbXVf ZXZlbnRzX2F0dHIsCj4+ICt9Owo+PiArCj4+ICtzdGF0aWMgc3RydWN0IGF0dHJpYnV0ZV9ncm91 cCBobnMzX3BtdV9maWx0ZXJfbW9kZV9ncm91cCA9IHsKPj4gK8KgwqDCoCAubmFtZSA9ICJmaWx0 ZXJtb2RlIiwKPj4gK8KgwqDCoCAuYXR0cnMgPSBobnMzX3BtdV9maWx0ZXJfbW9kZV9hdHRyLAo+ PiArfTsKPj4gKwo+PiArc3RhdGljIHN0cnVjdCBhdHRyaWJ1dGUgKmhuczNfcG11X2Zvcm1hdF9h dHRyW10gPSB7Cj4+ICvCoMKgwqAgSE5TM19QTVVfRk9STUFUX0FUVFIoZXZlbnQsICJjb25maWc6 MC0xNiIpLAo+PiArwqDCoMKgIEhOUzNfUE1VX0ZPUk1BVF9BVFRSKHBvcnQsICJjb25maWcxOjAt MyIpLAo+PiArwqDCoMKgIEhOUzNfUE1VX0ZPUk1BVF9BVFRSKHRjLCAiY29uZmlnMTo0LTciKSwK Pj4gK8KgwqDCoCBITlMzX1BNVV9GT1JNQVRfQVRUUihiZGYsICJjb25maWcxOjgtMjMiKSwKPj4g K8KgwqDCoCBITlMzX1BNVV9GT1JNQVRfQVRUUihxdWV1ZSwgImNvbmZpZzE6MjQtMzkiKSwKPj4g K8KgwqDCoCBITlMzX1BNVV9GT1JNQVRfQVRUUihpbnRyLCAiY29uZmlnMTo0MC01MSIpLAo+PiAr wqDCoMKgIEhOUzNfUE1VX0ZPUk1BVF9BVFRSKGdsb2JhbCwgImNvbmZpZzE6NTItNTIiKSwKPj4g K8KgwqDCoCBOVUxMCj4+ICt9Owo+PiArCj4+ICtzdGF0aWMgc3RydWN0IGF0dHJpYnV0ZV9ncm91 cCBobnMzX3BtdV9mb3JtYXRfZ3JvdXAgPSB7Cj4+ICvCoMKgwqAgLm5hbWUgPSAiZm9ybWF0IiwK Pj4gK8KgwqDCoCAuYXR0cnMgPSBobnMzX3BtdV9mb3JtYXRfYXR0ciwKPj4gK307Cj4+ICsKPj4g K3N0YXRpYyBzdHJ1Y3QgYXR0cmlidXRlICpobnMzX3BtdV9jcHVtYXNrX2F0dHJzW10gPSB7Cj4+ ICvCoMKgwqAgJmRldl9hdHRyX2NwdW1hc2suYXR0ciwKPj4gK8KgwqDCoCBOVUxMCj4+ICt9Owo+ PiArCj4+ICtzdGF0aWMgc3RydWN0IGF0dHJpYnV0ZV9ncm91cCBobnMzX3BtdV9jcHVtYXNrX2F0 dHJfZ3JvdXAgPSB7Cj4+ICvCoMKgwqAgLmF0dHJzID0gaG5zM19wbXVfY3B1bWFza19hdHRycywK Pj4gK307Cj4+ICsKPj4gK3N0YXRpYyBzdHJ1Y3QgYXR0cmlidXRlICpobnMzX3BtdV9pZGVudGlm aWVyX2F0dHJzW10gPSB7Cj4+ICvCoMKgwqAgJmRldl9hdHRyX2lkZW50aWZpZXIuYXR0ciwKPj4g K8KgwqDCoCBOVUxMCj4+ICt9Owo+PiArCj4+ICtzdGF0aWMgc3RydWN0IGF0dHJpYnV0ZV9ncm91 cCBobnMzX3BtdV9pZGVudGlmaWVyX2F0dHJfZ3JvdXAgPSB7Cj4+ICvCoMKgwqAgLmF0dHJzID0g aG5zM19wbXVfaWRlbnRpZmllcl9hdHRycywKPj4gK307Cj4+ICsKPj4gK3N0YXRpYyBzdHJ1Y3Qg YXR0cmlidXRlICpobnMzX3BtdV9iZGZfcmFuZ2VfYXR0cnNbXSA9IHsKPj4gK8KgwqDCoCAmZGV2 X2F0dHJfYmRmX21pbi5hdHRyLAo+PiArwqDCoMKgICZkZXZfYXR0cl9iZGZfbWF4LmF0dHIsCj4+ ICvCoMKgwqAgTlVMTAo+PiArfTsKPj4gKwo+PiArc3RhdGljIHN0cnVjdCBhdHRyaWJ1dGVfZ3Jv dXAgaG5zM19wbXVfYmRmX3JhbmdlX2F0dHJfZ3JvdXAgPSB7Cj4+ICvCoMKgwqAgLmF0dHJzID0g aG5zM19wbXVfYmRmX3JhbmdlX2F0dHJzLAo+PiArfTsKPj4gKwo+PiArc3RhdGljIHN0cnVjdCBh dHRyaWJ1dGUgKmhuczNfcG11X2h3X2Nsa19mcmVxX2F0dHJzW10gPSB7Cj4+ICvCoMKgwqAgJmRl dl9hdHRyX2h3X2Nsa19mcmVxLmF0dHIsCj4+ICvCoMKgwqAgTlVMTAo+PiArfTsKPj4gKwo+PiAr c3RhdGljIHN0cnVjdCBhdHRyaWJ1dGVfZ3JvdXAgaG5zM19wbXVfaHdfY2xrX2ZyZXFfYXR0cl9n cm91cCA9IHsKPj4gK8KgwqDCoCAuYXR0cnMgPSBobnMzX3BtdV9od19jbGtfZnJlcV9hdHRycywK Pj4gK307Cj4+ICsKPj4gK3N0YXRpYyBjb25zdCBzdHJ1Y3QgYXR0cmlidXRlX2dyb3VwICpobnMz X3BtdV9hdHRyX2dyb3Vwc1tdID0gewo+PiArwqDCoMKgICZobnMzX3BtdV9ldmVudHNfZ3JvdXAs Cj4+ICvCoMKgwqAgJmhuczNfcG11X2ZpbHRlcl9tb2RlX2dyb3VwLAo+PiArwqDCoMKgICZobnMz X3BtdV9mb3JtYXRfZ3JvdXAsCj4+ICvCoMKgwqAgJmhuczNfcG11X2NwdW1hc2tfYXR0cl9ncm91 cCwKPj4gK8KgwqDCoCAmaG5zM19wbXVfaWRlbnRpZmllcl9hdHRyX2dyb3VwLAo+PiArwqDCoMKg ICZobnMzX3BtdV9iZGZfcmFuZ2VfYXR0cl9ncm91cCwKPj4gK8KgwqDCoCAmaG5zM19wbXVfaHdf Y2xrX2ZyZXFfYXR0cl9ncm91cCwKPj4gK8KgwqDCoCBOVUxMCj4+ICt9Owo+PiArCj4+ICtzdGF0 aWMgdTMyIGhuczNfcG11X2dldF9vZmZzZXQodTMyIG9mZnNldCwgdTMyIGlkeCkKPj4gK3sKPj4g K8KgwqDCoCByZXR1cm4gb2Zmc2V0ICsgSE5TM19QTVVfUkVHX0VWRU5UX09GRlNFVCArCj4+ICvC oMKgwqDCoMKgwqDCoMKgwqDCoCBITlMzX1BNVV9SRUdfRVZFTlRfU0laRSAqIGlkeDsKPj4gK30K Pj4gKwo+PiArc3RhdGljIHUzMiBobnMzX3BtdV9yZWFkbChzdHJ1Y3QgaG5zM19wbXUgKmhuczNf cG11LCB1MzIgcmVnX29mZnNldCwgdTMyIGlkeCkKPj4gK3sKPj4gK8KgwqDCoCB1MzIgb2Zmc2V0 ID0gaG5zM19wbXVfZ2V0X29mZnNldChyZWdfb2Zmc2V0LCBpZHgpOwo+PiArCj4+ICvCoMKgwqAg cmV0dXJuIHJlYWRsKGhuczNfcG11LT5iYXNlICsgb2Zmc2V0KTsKPj4gK30KPj4gKwo+PiArc3Rh dGljIHZvaWQgaG5zM19wbXVfd3JpdGVsKHN0cnVjdCBobnMzX3BtdSAqaG5zM19wbXUsIHUzMiBy ZWdfb2Zmc2V0LCB1MzIgaWR4LAo+PiArwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIHUz MiB2YWwpCj4+ICt7Cj4+ICvCoMKgwqAgdTMyIG9mZnNldCA9IGhuczNfcG11X2dldF9vZmZzZXQo cmVnX29mZnNldCwgaWR4KTsKPj4gKwo+PiArwqDCoMKgIHdyaXRlbCh2YWwsIGhuczNfcG11LT5i YXNlICsgb2Zmc2V0KTsKPj4gK30KPj4gKwo+PiArc3RhdGljIHU2NCBobnMzX3BtdV9yZWFkcShz dHJ1Y3QgaG5zM19wbXUgKmhuczNfcG11LCB1MzIgcmVnX29mZnNldCwgdTMyIGlkeCkKPj4gK3sK Pj4gK8KgwqDCoCB1MzIgb2Zmc2V0ID0gaG5zM19wbXVfZ2V0X29mZnNldChyZWdfb2Zmc2V0LCBp ZHgpOwo+PiArCj4+ICvCoMKgwqAgcmV0dXJuIHJlYWRxKGhuczNfcG11LT5iYXNlICsgb2Zmc2V0 KTsKPj4gK30KPj4gKwo+PiArc3RhdGljIHZvaWQgaG5zM19wbXVfd3JpdGVxKHN0cnVjdCBobnMz X3BtdSAqaG5zM19wbXUsIHUzMiByZWdfb2Zmc2V0LCB1MzIgaWR4LAo+PiArwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgIHU2NCB2YWwpCj4+ICt7Cj4+ICvCoMKgwqAgdTMyIG9mZnNldCA9 IGhuczNfcG11X2dldF9vZmZzZXQocmVnX29mZnNldCwgaWR4KTsKPj4gKwo+PiArwqDCoMKgIHdy aXRlcSh2YWwsIGhuczNfcG11LT5iYXNlICsgb2Zmc2V0KTsKPj4gK30KPj4gKwo+PiArc3RhdGlj IGJvb2wgaG5zM19wbXVfY21wX2V2ZW50KHN0cnVjdCBwZXJmX2V2ZW50ICp0YXJnZXQsCj4+ICvC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgc3RydWN0IHBlcmZfZXZlbnQgKmV2 ZW50KQo+PiArewo+PiArwqDCoMKgIHJldHVybiBobnMzX2dldF9yZWFsX2V2ZW50KHRhcmdldCkg PT0gaG5zM19nZXRfcmVhbF9ldmVudChldmVudCk7Cj4+ICt9Cj4+ICsKPj4gK3N0YXRpYyBpbnQg aG5zM19wbXVfZmluZF9yZWxhdGVkX2V2ZW50KHN0cnVjdCBobnMzX3BtdSAqaG5zM19wbXUsCj4g Cj4gbWF5YmUgaG5zM19wbXVfZmluZF9yZWxhdGVkX2V2ZW50X2luZGV4KCkKPiAKT2suCgo+PiAr wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgc3RydWN0IHBlcmZf ZXZlbnQgKmV2ZW50KQo+PiArewo+PiArwqDCoMKgIHN0cnVjdCBwZXJmX2V2ZW50ICpzaWJsaW5n Owo+PiArwqDCoMKgIGludCBpZHg7Cj4+ICsKPj4gK8KgwqDCoCBmb3IgKGlkeCA9IDA7IGlkeCA8 IEhOUzNfUE1VX01BWF9IV19FVkVOVFM7IGlkeCsrKSB7Cj4+ICvCoMKgwqDCoMKgwqDCoCBzaWJs aW5nID0gaG5zM19wbXUtPmh3X2V2ZW50c1tpZHhdOwo+PiArwqDCoMKgwqDCoMKgwqAgaWYgKCFz aWJsaW5nKQo+PiArwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCBjb250aW51ZTsKPj4gKwo+PiArwqDC oMKgwqDCoMKgwqAgaWYgKCFobnMzX3BtdV9jbXBfZXZlbnQoc2libGluZywgZXZlbnQpKQo+PiAr wqDCoMKgwqDCoMKgwqDCoMKgwqDCoCBjb250aW51ZTsKPj4gKwo+PiArwqDCoMKgwqDCoMKgwqAg LyogUmVsYXRlZCBldmVudHMgbXVzdCBiZSB1c2VkIGluIGdyb3VwICovCj4+ICvCoMKgwqDCoMKg wqDCoCBpZiAoc2libGluZy0+Z3JvdXBfbGVhZGVyID09IGV2ZW50LT5ncm91cF9sZWFkZXIpCj4+ ICvCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIHJldHVybiBpZHg7Cj4+ICvCoMKgwqDCoMKgwqDCoCBl bHNlCj4gCj4gbm8gbmVlZCBmb3IgZWxzZQo+IApPay4KCj4+ICvCoMKgwqDCoMKgwqDCoMKgwqDC oMKgIHJldHVybiAtRUlOVkFMOwo+PiArwqDCoMKgIH0KPj4gKwo+PiArwqDCoMKgIHJldHVybiBp ZHg7Cj4gCj4gc28gaXMgdGhpcyBhbiBlcnJvciBwYXRoPyBBcyB0aGUgb25seSBjYWxsZXIgY2hl Y2tzIGZvciBpZHggPCAwIGFzIGFuIGVycm9yCj4gCk9rLCBJIHRoaW5rIEkgbmVlZCB0byBtb2Rp ZnkgcHJvY2Vzc2luZyBsb2dpYyBoZXJlLCB0aGFua3MuCgoKPj4gK30KPj4gKwo+PiArc3RhdGlj IGludCBobnMzX3BtdV9nZXRfZXZlbnRfaWR4KHN0cnVjdCBobnMzX3BtdSAqaG5zM19wbXUpCj4+ ICt7Cj4+ICvCoMKgwqAgaW50IGlkeDsKPj4gKwo+PiArwqDCoMKgIGZvciAoaWR4ID0gMDsgaWR4 IDwgSE5TM19QTVVfTUFYX0hXX0VWRU5UUzsgaWR4KyspIHsKPj4gK8KgwqDCoMKgwqDCoMKgIGlm ICghaG5zM19wbXUtPmh3X2V2ZW50c1tpZHhdKQo+PiArwqDCoMKgwqDCoMKgwqAgcmV0dXJuIGlk eDsKPiAKPiBtaXNsZWFkaW5nIGluZGVudAo+IApPaywgdGhhbmtzLgoKPj4gK8KgwqDCoCB9Cj4+ ICsKPj4gK8KgwqDCoCByZXR1cm4gLUVCVVNZOwo+PiArfQo+PiArCj4+ICtzdGF0aWMgYm9vbCBo bnMzX3BtdV92YWxpZF9iZGYoc3RydWN0IGhuczNfcG11ICpobnMzX3BtdSwgdTE2IGJkZikKPj4g K3sKPj4gK8KgwqDCoCBzdHJ1Y3QgcGNpX2RldiAqcGRldjsKPj4gKwo+PiArwqDCoMKgIGlmIChi ZGYgPCBobnMzX3BtdS0+YmRmX21pbiB8fCBiZGYgPiBobnMzX3BtdS0+YmRmX21heCkgewo+PiAr wqDCoMKgwqDCoMKgwqAgcGNpX2VycihobnMzX3BtdS0+cGRldiwgIkludmFsaWQgRVAgZGV2aWNl OiAlI3ghXG4iLCBiZGYpOwo+PiArwqDCoMKgwqDCoMKgwqAgcmV0dXJuIGZhbHNlOwo+PiArwqDC oMKgIH0KPj4gKwo+PiArwqDCoMKgIHBkZXYgPSBwY2lfZ2V0X2RvbWFpbl9idXNfYW5kX3Nsb3Qo cGNpX2RvbWFpbl9ucihobnMzX3BtdS0+cGRldi0+YnVzKSwKPj4gK8KgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIFBDSV9CVVNfTlVNKGJkZiksCj4+ICvCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCBHRVRfUENJX0RFVkZOKGJkZikp Owo+PiArwqDCoMKgIGlmICghcGRldikgewo+PiArwqDCoMKgwqDCoMKgwqAgcGNpX2VycihobnMz X3BtdS0+cGRldiwgIk5vbmV4aXN0ZW50IEVQIGRldmljZTogJSN4IVxuIiwgYmRmKTsKPj4gK8Kg wqDCoMKgwqDCoMKgIHJldHVybiBmYWxzZTsKPj4gK8KgwqDCoCB9Cj4+ICsKPj4gK8KgwqDCoCBw Y2lfZGV2X3B1dChwZGV2KTsKPj4gK8KgwqDCoCByZXR1cm4gdHJ1ZTsKPj4gK30KPj4gKwo+PiAr c3RhdGljIHZvaWQgaG5zM19wbXVfc2V0X3FpZF9wYXJhKHN0cnVjdCBobnMzX3BtdSAqaG5zM19w bXUsIHUzMiBpZHgsIHUxNiBiZGYsCj4+ICvCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgIHUxNiBxdWV1ZSkKPj4gK3sKPj4gK8KgwqDCoCB1MzIgdmFsOwo+PiArCj4+ICvCoMKgwqAg dmFsID0gR0VUX1BDSV9ERVZGTihiZGYpOwo+PiArwqDCoMKgIHZhbCB8PSAodTMyKXF1ZXVlIDw8 IEhOUzNfUE1VX1FJRF9QQVJBX1FVRVVFX1M7Cj4+ICvCoMKgwqAgaG5zM19wbXVfd3JpdGVsKGhu czNfcG11LCBITlMzX1BNVV9SRUdfRVZFTlRfUUlEX1BBUkEsIGlkeCwgdmFsKTsKPj4gK30KPj4g Kwo+PiArc3RhdGljIGJvb2wgaG5zM19wbXVfcWlkX3JlcV9zdGFydChzdHJ1Y3QgaG5zM19wbXUg KmhuczNfcG11LCB1MzIgaWR4KQo+PiArewo+PiArwqDCoMKgIGJvb2wgcXVldWVfaWRfdmFsaWQg PSBmYWxzZTsKPj4gK8KgwqDCoCB1MzIgcmVnX3FpZF9jdHJsLCB2YWw7Cj4+ICvCoMKgwqAgaW50 IGVycjsKPj4gKwo+PiArwqDCoMKgIC8qIGVuYWJsZSBxdWV1ZSBpZCByZXF1ZXN0ICovCj4+ICvC oMKgwqAgaG5zM19wbXVfd3JpdGVsKGhuczNfcG11LCBITlMzX1BNVV9SRUdfRVZFTlRfUUlEX0NU UkwsIGlkeCwKPj4gK8KgwqDCoMKgwqDCoMKgwqDCoMKgwqAgSE5TM19QTVVfUUlEX0NUUkxfUkVR X0VOQUJMRSk7Cj4+ICsKPj4gK8KgwqDCoCByZWdfcWlkX2N0cmwgPSBobnMzX3BtdV9nZXRfb2Zm c2V0KEhOUzNfUE1VX1JFR19FVkVOVF9RSURfQ1RSTCwgaWR4KTsKPj4gK8KgwqDCoCBlcnIgPSBy ZWFkbF9wb2xsX3RpbWVvdXQoaG5zM19wbXUtPmJhc2UgKyByZWdfcWlkX2N0cmwsIHZhbCwKPj4g K8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIHZhbCAmIEhOUzNfUE1VX1FJRF9DVFJM X0RPTkUsIDEsIDEwMDApOwo+PiArwqDCoMKgIGlmIChlcnIgPT0gLUVUSU1FRE9VVCkgewo+PiAr wqDCoMKgwqDCoMKgwqAgcGNpX2VycihobnMzX3BtdS0+cGRldiwgIlFJRCByZXF1ZXN0IHRpbWVv dXQhXG4iKTsKPj4gK8KgwqDCoMKgwqDCoMKgIGdvdG8gb3V0Owo+PiArwqDCoMKgIH0KPj4gKwo+ PiArwqDCoMKgIHF1ZXVlX2lkX3ZhbGlkID0gKHZhbCAmIEhOUzNfUE1VX1FJRF9DVFJMX01JU1Mp ID09IDA7Cj4gCj4gdGhpcyBzZWVtcyBuZWF0ZXIKPiAKPiBxdWV1ZV9pZF92YWxpZCA9ICEodmFs ICYgSE5TM19QTVVfUUlEX0NUUkxfTUlTUyk7Cj4gCk9rLgoKPj4gKwo+PiArb3V0Ogo+PiArwqDC oMKgIC8qIGRpc2FibGUgcWlkIHJlcXVlc3QgYW5kIGNsZWFyIHN0YXR1cyAqLwo+PiArwqDCoMKg IGhuczNfcG11X3dyaXRlbChobnMzX3BtdSwgSE5TM19QTVVfUkVHX0VWRU5UX1FJRF9DVFJMLCBp ZHgsIDApOwo+PiArCj4+ICvCoMKgwqAgcmV0dXJuIHF1ZXVlX2lkX3ZhbGlkOwo+PiArfQo+PiAr Cj4+ICtzdGF0aWMgYm9vbCBobnMzX3BtdV92YWxpZF9xdWV1ZShzdHJ1Y3QgaG5zM19wbXUgKmhu czNfcG11LCB1MzIgaWR4LCB1MTYgYmRmLAo+PiArwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqAgdTE2IHF1ZXVlKQo+PiArewo+PiArwqDCoMKgIGhuczNfcG11X3NldF9xaWRfcGFyYSho bnMzX3BtdSwgaWR4LCBiZGYsIHF1ZXVlKTsKPj4gKwo+PiArwqDCoMKgIHJldHVybiBobnMzX3Bt dV9xaWRfcmVxX3N0YXJ0KGhuczNfcG11LCBpZHgpOwo+PiArfQo+PiArCj4+ICtzdGF0aWMgc3Ry dWN0IGhuczNfcG11X2V2ZW50X2F0dHIgKmhuczNfcG11X2dldF9wbXVfZXZlbnQodTMyIGV2ZW50 KQo+PiArewo+PiArwqDCoMKgIHN0cnVjdCBobnMzX3BtdV9ldmVudF9hdHRyICpwbXVfZXZlbnQ7 Cj4+ICvCoMKgwqAgc3RydWN0IGRldl9leHRfYXR0cmlidXRlICplYXR0cjsKPj4gK8KgwqDCoCBz dHJ1Y3QgZGV2aWNlX2F0dHJpYnV0ZSAqZGF0dHI7Cj4+ICvCoMKgwqAgc3RydWN0IGF0dHJpYnV0 ZSAqYXR0cjsKPj4gK8KgwqDCoCB1MzIgaTsKPj4gKwo+PiArwqDCoMKgIGZvciAoaSA9IDA7IGkg PCBBUlJBWV9TSVpFKGhuczNfcG11X2V2ZW50c19hdHRyKSAtIDE7IGkrKykgewo+PiArwqDCoMKg wqDCoMKgwqAgYXR0ciA9IGhuczNfcG11X2V2ZW50c19hdHRyW2ldOwo+PiArwqDCoMKgwqDCoMKg wqAgZGF0dHIgPSBjb250YWluZXJfb2YoYXR0ciwgc3RydWN0IGRldmljZV9hdHRyaWJ1dGUsIGF0 dHIpOwo+PiArwqDCoMKgwqDCoMKgwqAgZWF0dHIgPSBjb250YWluZXJfb2YoZGF0dHIsIHN0cnVj dCBkZXZfZXh0X2F0dHJpYnV0ZSwgYXR0cik7Cj4+ICvCoMKgwqDCoMKgwqDCoCBwbXVfZXZlbnQg PSAoc3RydWN0IGhuczNfcG11X2V2ZW50X2F0dHIgKillYXR0ci0+dmFyOwo+IAo+IGVhdHRyLT52 YXIgaXMgdm9pZCAqIHNvIG5vIG5lZWQgZm9yIGEgY2FzdAo+IApPaywgdGhhbmtzLgoKPj4gKwo+ PiArwqDCoMKgwqDCoMKgwqAgaWYgKGV2ZW50ID09IHBtdV9ldmVudC0+ZXZlbnQpCj4+ICvCoMKg wqDCoMKgwqDCoMKgwqDCoMKgIHJldHVybiBwbXVfZXZlbnQ7Cj4+ICvCoMKgwqAgfQo+PiArCj4+ ICvCoMKgwqAgcmV0dXJuIE5VTEw7Cj4+ICt9Cj4+ICsKPj4gK3N0YXRpYyBpbnQgaG5zM19wbXVf c2V0X2Z1bmNfbW9kZShzdHJ1Y3QgcGVyZl9ldmVudCAqZXZlbnQsCj4+ICvCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgIHN0cnVjdCBobnMzX3BtdSAqaG5zM19wbXUpCj4+ICt7Cj4+ ICvCoMKgwqAgc3RydWN0IGh3X3BlcmZfZXZlbnQgKmh3YyA9ICZldmVudC0+aHc7Cj4+ICvCoMKg wqAgdTE2IGJkZiA9IGhuczNfZ2V0X2JkZihldmVudCk7Cj4+ICsKPj4gK8KgwqDCoCBpZiAoIWhu czNfcG11X3ZhbGlkX2JkZihobnMzX3BtdSwgYmRmKSkKPj4gK8KgwqDCoMKgwqDCoMKgIHJldHVy biAtRU5PRU5UOwo+PiArCj4+ICvCoMKgwqAgSE5TM19QTVVfU0VUX0hXX0ZJTFRFUihod2MsIEhO UzNfUE1VX0hXX0ZJTFRFUl9GVU5DKTsKPj4gKwo+PiArwqDCoMKgIHJldHVybiAwOwo+PiArfQo+ PiArCj4+ICtzdGF0aWMgaW50IGhuczNfcG11X3NldF9mdW5jX3F1ZXVlX21vZGUoc3RydWN0IHBl cmZfZXZlbnQgKmV2ZW50LAo+PiArwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqAgc3RydWN0IGhuczNfcG11ICpobnMzX3BtdSkKPj4gK3sKPj4gK8KgwqDCoCBzdHJ1Y3QgaHdf cGVyZl9ldmVudCAqaHdjID0gJmV2ZW50LT5odzsKPj4gK8KgwqDCoCB1MTYgcXVldWVfaWQgPSBo bnMzX2dldF9xdWV1ZShldmVudCk7Cj4+ICvCoMKgwqAgdTE2IGJkZiA9IGhuczNfZ2V0X2JkZihl dmVudCk7Cj4+ICsKPj4gK8KgwqDCoCBpZiAoIWhuczNfcG11X3ZhbGlkX2JkZihobnMzX3BtdSwg YmRmKSkKPj4gK8KgwqDCoMKgwqDCoMKgIHJldHVybiAtRU5PRU5UOwo+PiArCj4+ICvCoMKgwqAg aWYgKCFobnMzX3BtdV92YWxpZF9xdWV1ZShobnMzX3BtdSwgaHdjLT5pZHgsIGJkZiwgcXVldWVf aWQpKSB7Cj4+ICvCoMKgwqDCoMKgwqDCoCBwY2lfZXJyKGhuczNfcG11LT5wZGV2LCAiSW52YWxp ZCBxdWV1ZTogJXVcbiIsIHF1ZXVlX2lkKTsKPj4gK8KgwqDCoMKgwqDCoMKgIHJldHVybiAtRU5P RU5UOwo+PiArwqDCoMKgIH0KPj4gKwo+PiArwqDCoMKgIEhOUzNfUE1VX1NFVF9IV19GSUxURVIo aHdjLCBITlMzX1BNVV9IV19GSUxURVJfRlVOQ19RVUVVRSk7Cj4+ICsKPj4gK8KgwqDCoCByZXR1 cm4gMDsKPj4gK30KPj4gKwo+PiArc3RhdGljIGJvb2wKPj4gK2huczNfcG11X2lzX2VuYWJsZWRf Z2xvYmFsX21vZGUoc3RydWN0IHBlcmZfZXZlbnQgKmV2ZW50LAo+PiArwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgIHN0cnVjdCBobnMzX3BtdV9ldmVudF9hdHRyICpwbXVfZXZlbnQpCj4+ ICt7Cj4+ICvCoMKgwqAgdTggZ2xvYmFsID0gaG5zM19nZXRfZ2xvYmFsKGV2ZW50KTsKPj4gKwo+ PiArwqDCoMKgIGlmICghKHBtdV9ldmVudC0+ZmlsdGVyX3N1cHBvcnQgJiBITlMzX1BNVV9GSUxU RVJfU1VQUE9SVF9HTE9CQUwpKQo+PiArwqDCoMKgwqDCoMKgwqAgcmV0dXJuIGZhbHNlOwo+PiAr Cj4+ICvCoMKgwqAgcmV0dXJuICEhZ2xvYmFsOwo+IAo+IG5vIG5lZWQgZm9yICEhIHNpbmNlIHlv dSByZXR1cm4gYm9vbCB0aGUgY29tcGlsZXIgd2lsbCBkbyB0aGlzIGZvciB5b3UKPiAKT2suCgo+ PiArfQo+PiArCj4+ICtzdGF0aWMgYm9vbCBobnMzX3BtdV9pc19lbmFibGVkX2Z1bmNfbW9kZShz dHJ1Y3QgcGVyZl9ldmVudCAqZXZlbnQsCj4+ICvCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqAgc3RydWN0IGhuczNfcG11X2V2ZW50X2F0dHIgKnBtdV9ldmVudCkKPj4g K3sKPj4gK8KgwqDCoCB1MTYgcXVldWVfaWQgPSBobnMzX2dldF9xdWV1ZShldmVudCk7Cj4+ICvC oMKgwqAgdTE2IGJkZiA9IGhuczNfZ2V0X2JkZihldmVudCk7Cj4+ICsKPj4gK8KgwqDCoCBpZiAo IShwbXVfZXZlbnQtPmZpbHRlcl9zdXBwb3J0ICYgSE5TM19QTVVfRklMVEVSX1NVUFBPUlRfRlVO QykpCj4+ICvCoMKgwqDCoMKgwqDCoCByZXR1cm4gZmFsc2U7Cj4+ICvCoMKgwqAgZWxzZSBpZiAo cXVldWVfaWQgIT0gSE5TM19QTVVfRklMVEVSX0FMTF9RVUVVRSkKPj4gK8KgwqDCoMKgwqDCoMKg IHJldHVybiBmYWxzZTsKPj4gKwo+PiArwqDCoMKgIHJldHVybiAhIWJkZjsKPiAKPiBhcyBhYm92 ZQo+IApPay4KCj4+ICt9Cj4+ICsKPj4gK3N0YXRpYyBib29sCj4+ICtobnMzX3BtdV9pc19lbmFi bGVkX2Z1bmNfcXVldWVfbW9kZShzdHJ1Y3QgcGVyZl9ldmVudCAqZXZlbnQsCj4+ICvCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCBzdHJ1Y3QgaG5zM19wbXVfZXZlbnRfYXR0 ciAqcG11X2V2ZW50KQo+PiArewo+PiArwqDCoMKgIHUxNiBxdWV1ZV9pZCA9IGhuczNfZ2V0X3F1 ZXVlKGV2ZW50KTsKPj4gK8KgwqDCoCB1MTYgYmRmID0gaG5zM19nZXRfYmRmKGV2ZW50KTsKPj4g Kwo+PiArwqDCoMKgIGlmICghKHBtdV9ldmVudC0+ZmlsdGVyX3N1cHBvcnQgJiBITlMzX1BNVV9G SUxURVJfU1VQUE9SVF9GVU5DX1FVRVVFKSkKPj4gK8KgwqDCoMKgwqDCoMKgIHJldHVybiBmYWxz ZTsKPj4gK8KgwqDCoCBlbHNlIGlmIChxdWV1ZV9pZCA9PSBITlMzX1BNVV9GSUxURVJfQUxMX1FV RVVFKQo+PiArwqDCoMKgwqDCoMKgwqAgcmV0dXJuIGZhbHNlOwo+PiArCj4+ICvCoMKgwqAgcmV0 dXJuICEhYmRmOwo+IAo+IGFnYWluCj4gCk9rLgoKPj4gK30KPj4gKwo+PiArc3RhdGljIGJvb2wg aG5zM19wbXVfaXNfZW5hYmxlZF9wb3J0X21vZGUoc3RydWN0IHBlcmZfZXZlbnQgKmV2ZW50LAo+ PiArwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIHN0cnVjdCBobnMz X3BtdV9ldmVudF9hdHRyICpwbXVfZXZlbnQpCj4+ICt7Cj4+ICvCoMKgwqAgdTggdGNfaWQgPSBo bnMzX2dldF90YyhldmVudCk7Cj4+ICsKPj4gK8KgwqDCoCBpZiAoIShwbXVfZXZlbnQtPmZpbHRl cl9zdXBwb3J0ICYgSE5TM19QTVVfRklMVEVSX1NVUFBPUlRfUE9SVCkpCj4+ICvCoMKgwqDCoMKg wqDCoCByZXR1cm4gZmFsc2U7Cj4+ICsKPj4gK8KgwqDCoCByZXR1cm4gdGNfaWQgPT0gSE5TM19Q TVVfRklMVEVSX0FMTF9UQzsKPj4gK30KPj4gKwo+PiArc3RhdGljIGJvb2wKPj4gK2huczNfcG11 X2lzX2VuYWJsZWRfcG9ydF90Y19tb2RlKHN0cnVjdCBwZXJmX2V2ZW50ICpldmVudCwKPj4gK8Kg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIHN0cnVjdCBobnMzX3BtdV9ldmVudF9hdHRy ICpwbXVfZXZlbnQpCj4+ICt7Cj4+ICvCoMKgwqAgdTggdGNfaWQgPSBobnMzX2dldF90YyhldmVu dCk7Cj4+ICsKPj4gK8KgwqDCoCBpZiAoIShwbXVfZXZlbnQtPmZpbHRlcl9zdXBwb3J0ICYgSE5T M19QTVVfRklMVEVSX1NVUFBPUlRfUE9SVF9UQykpCj4+ICvCoMKgwqDCoMKgwqDCoCByZXR1cm4g ZmFsc2U7Cj4+ICsKPj4gK8KgwqDCoCByZXR1cm4gdGNfaWQgIT0gSE5TM19QTVVfRklMVEVSX0FM TF9UQzsKPj4gK30KPj4gKwo+PiArc3RhdGljIGJvb2wKPj4gK2huczNfcG11X2lzX2VuYWJsZWRf ZnVuY19pbnRyX21vZGUoc3RydWN0IHBlcmZfZXZlbnQgKmV2ZW50LAo+PiArwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIHN0cnVjdCBobnMzX3BtdSAqaG5zM19wbXUsCj4+ICvC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgc3RydWN0IGhuczNfcG11X2V2ZW50 X2F0dHIgKnBtdV9ldmVudCkKPj4gK3sKPj4gK8KgwqDCoCB1MTYgYmRmID0gaG5zM19nZXRfYmRm KGV2ZW50KTsKPj4gKwo+PiArwqDCoMKgIGlmICghKHBtdV9ldmVudC0+ZmlsdGVyX3N1cHBvcnQg JiBITlMzX1BNVV9GSUxURVJfU1VQUE9SVF9GVU5DX0lOVFIpKQo+PiArwqDCoMKgwqDCoMKgwqAg cmV0dXJuIGZhbHNlOwo+PiArCj4+ICvCoMKgwqAgcmV0dXJuIGhuczNfcG11X3ZhbGlkX2JkZiho bnMzX3BtdSwgYmRmKTsKPj4gK30KPj4gKwo+PiArc3RhdGljIGludCBobnMzX3BtdV9zZWxlY3Rf ZmlsdGVyX21vZGUoc3RydWN0IHBlcmZfZXZlbnQgKmV2ZW50LAo+PiArwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgc3RydWN0IGhuczNfcG11ICpobnMzX3BtdSkK Pj4gK3sKPj4gK8KgwqDCoCBzdHJ1Y3QgaG5zM19wbXVfZXZlbnRfYXR0ciAqcG11X2V2ZW50Owo+ PiArwqDCoMKgIHN0cnVjdCBod19wZXJmX2V2ZW50ICpod2MgPSAmZXZlbnQtPmh3Owo+PiArwqDC oMKgIHUzMiBldmVudF9pZCA9IGhuczNfZ2V0X2V2ZW50KGV2ZW50KTsKPj4gKwo+PiArwqDCoMKg IHBtdV9ldmVudCA9IGhuczNfcG11X2dldF9wbXVfZXZlbnQoZXZlbnRfaWQpOwo+PiArwqDCoMKg IGlmICghcG11X2V2ZW50KSB7Cj4+ICvCoMKgwqDCoMKgwqDCoCBwY2lfZXJyKGhuczNfcG11LT5w ZGV2LCAiSW52YWxpZCBwbXUgZXZlbnRcbiIpOwo+PiArwqDCoMKgwqDCoMKgwqAgcmV0dXJuIC1F Tk9FTlQ7Cj4+ICvCoMKgwqAgfQo+PiArCj4+ICvCoMKgwqAgaWYgKGhuczNfcG11X2lzX2VuYWJs ZWRfZ2xvYmFsX21vZGUoZXZlbnQsIHBtdV9ldmVudCkpIHsKPj4gK8KgwqDCoMKgwqDCoMKgIEhO UzNfUE1VX1NFVF9IV19GSUxURVIoaHdjLCBITlMzX1BNVV9IV19GSUxURVJfR0xPQkFMKTsKPj4g K8KgwqDCoMKgwqDCoMKgIHJldHVybiAwOwo+PiArwqDCoMKgIH0KPj4gKwo+PiArwqDCoMKgIGlm IChobnMzX3BtdV9pc19lbmFibGVkX2Z1bmNfbW9kZShldmVudCwgcG11X2V2ZW50KSkKPj4gK8Kg wqDCoMKgwqDCoMKgIHJldHVybiBobnMzX3BtdV9zZXRfZnVuY19tb2RlKGV2ZW50LCBobnMzX3Bt dSk7Cj4+ICsKPj4gK8KgwqDCoCBpZiAoaG5zM19wbXVfaXNfZW5hYmxlZF9mdW5jX3F1ZXVlX21v ZGUoZXZlbnQsIHBtdV9ldmVudCkpCj4+ICvCoMKgwqDCoMKgwqDCoCByZXR1cm4gaG5zM19wbXVf c2V0X2Z1bmNfcXVldWVfbW9kZShldmVudCwgaG5zM19wbXUpOwo+PiArCj4+ICvCoMKgwqAgaWYg KGhuczNfcG11X2lzX2VuYWJsZWRfcG9ydF9tb2RlKGV2ZW50LCBwbXVfZXZlbnQpKSB7Cj4+ICvC oMKgwqDCoMKgwqDCoCBITlMzX1BNVV9TRVRfSFdfRklMVEVSKGh3YywgSE5TM19QTVVfSFdfRklM VEVSX1BPUlQpOwo+PiArwqDCoMKgwqDCoMKgwqAgcmV0dXJuIDA7Cj4+ICvCoMKgwqAgfQo+PiAr Cj4+ICvCoMKgwqAgaWYgKGhuczNfcG11X2lzX2VuYWJsZWRfcG9ydF90Y19tb2RlKGV2ZW50LCBw bXVfZXZlbnQpKSB7Cj4+ICvCoMKgwqDCoMKgwqDCoCBITlMzX1BNVV9TRVRfSFdfRklMVEVSKGh3 YywgSE5TM19QTVVfSFdfRklMVEVSX1BPUlRfVEMpOwo+PiArwqDCoMKgwqDCoMKgwqAgcmV0dXJu IDA7Cj4+ICvCoMKgwqAgfQo+PiArCj4+ICvCoMKgwqAgaWYgKGhuczNfcG11X2lzX2VuYWJsZWRf ZnVuY19pbnRyX21vZGUoZXZlbnQsIGhuczNfcG11LCBwbXVfZXZlbnQpKSB7Cj4+ICvCoMKgwqDC oMKgwqDCoCBITlMzX1BNVV9TRVRfSFdfRklMVEVSKGh3YywgSE5TM19QTVVfSFdfRklMVEVSX0ZV TkNfSU5UUik7Cj4+ICvCoMKgwqDCoMKgwqDCoCByZXR1cm4gMDsKPj4gK8KgwqDCoCB9Cj4+ICsK Pj4gK8KgwqDCoCByZXR1cm4gLUVOT0VOVDsKPj4gK30KPj4gKwo+PiArc3RhdGljIGJvb2wgaG5z M19wbXVfdmFsaWRhdGVfZXZlbnRfZ3JvdXAoc3RydWN0IHBlcmZfZXZlbnQgKmV2ZW50KQo+PiAr ewo+PiArwqDCoMKgIHN0cnVjdCBwZXJmX2V2ZW50ICpzaWJsaW5nLCAqbGVhZGVyID0gZXZlbnQt Pmdyb3VwX2xlYWRlcjsKPj4gK8KgwqDCoCBzdHJ1Y3QgcGVyZl9ldmVudCAqZXZlbnRfZ3JvdXBb SE5TM19QTVVfTUFYX0hXX0VWRU5UU107Cj4+ICvCoMKgwqAgaW50IGNvdW50ZXJzID0gMTsKPj4g K8KgwqDCoCBpbnQgbnVtOwo+PiArCj4+ICvCoMKgwqAgZXZlbnRfZ3JvdXBbMF0gPSBsZWFkZXI7 Cj4+ICvCoMKgwqAgaWYgKCFpc19zb2Z0d2FyZV9ldmVudChsZWFkZXIpKSB7Cj4+ICvCoMKgwqDC oMKgwqDCoCBpZiAobGVhZGVyLT5wbXUgIT0gZXZlbnQtPnBtdSkKPj4gK8KgwqDCoMKgwqDCoMKg wqDCoMKgwqAgcmV0dXJuIGZhbHNlOwo+PiArCj4+ICvCoMKgwqDCoMKgwqDCoCBpZiAobGVhZGVy ICE9IGV2ZW50ICYmICFobnMzX3BtdV9jbXBfZXZlbnQobGVhZGVyLCBldmVudCkpCj4+ICvCoMKg wqDCoMKgwqDCoMKgwqDCoMKgIGV2ZW50X2dyb3VwW2NvdW50ZXJzKytdID0gZXZlbnQ7Cj4+ICvC oMKgwqAgfQo+PiArCj4+ICvCoMKgwqAgZm9yX2VhY2hfc2libGluZ19ldmVudChzaWJsaW5nLCBl dmVudC0+Z3JvdXBfbGVhZGVyKSB7Cj4+ICvCoMKgwqDCoMKgwqDCoCBpZiAoaXNfc29mdHdhcmVf ZXZlbnQoc2libGluZykpCj4+ICvCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIGNvbnRpbnVlOwo+PiAr Cj4+ICvCoMKgwqDCoMKgwqDCoCBpZiAoc2libGluZy0+cG11ICE9IGV2ZW50LT5wbXUpCj4+ICvC oMKgwqDCoMKgwqDCoMKgwqDCoMKgIHJldHVybiBmYWxzZTsKPj4gKwo+PiArwqDCoMKgwqDCoMKg wqAgZm9yIChudW0gPSAwOyBudW0gPCBjb3VudGVyczsgbnVtKyspIHsKPj4gK8KgwqDCoMKgwqDC oMKgwqDCoMKgwqAgaWYgKGhuczNfcG11X2NtcF9ldmVudChldmVudF9ncm91cFtudW1dLCBzaWJs aW5nKSkKPj4gK8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCBicmVhazsKPj4gK8KgwqDC oMKgwqDCoMKgIH0KPj4gKwo+PiArwqDCoMKgwqDCoMKgwqAgaWYgKG51bSA9PSBjb3VudGVycykK Pj4gK8KgwqDCoMKgwqDCoMKgwqDCoMKgwqAgZXZlbnRfZ3JvdXBbY291bnRlcnMrK10gPSBzaWJs aW5nOwo+PiArwqDCoMKgIH0KPj4gKwo+PiArwqDCoMKgIHJldHVybiBjb3VudGVycyA8PSBITlMz X1BNVV9NQVhfSFdfRVZFTlRTOwo+PiArfQo+PiArCj4+ICtzdGF0aWMgdTMyIGhuczNfcG11X2dl dF9maWx0ZXJfY29uZGl0aW9uKHN0cnVjdCBwZXJmX2V2ZW50ICpldmVudCkKPj4gK3sKPj4gK8Kg wqDCoCBzdHJ1Y3QgaHdfcGVyZl9ldmVudCAqaHdjID0gJmV2ZW50LT5odzsKPj4gK8KgwqDCoCB1 MTYgaW50cl9pZCA9IGhuczNfZ2V0X2ludHIoZXZlbnQpOwo+PiArwqDCoMKgIHU4IHBvcnRfaWQg PSBobnMzX2dldF9wb3J0KGV2ZW50KTsKPj4gK8KgwqDCoCB1MTYgYmRmID0gaG5zM19nZXRfYmRm KGV2ZW50KTsKPj4gK8KgwqDCoCB1OCB0Y19pZCA9IGhuczNfZ2V0X3RjKGV2ZW50KTsKPj4gK8Kg wqDCoCB1OCBmaWx0ZXJfbW9kZTsKPj4gK8KgwqDCoCB1MzIgZmlsdGVyID0gMDsKPj4gKwo+PiAr wqDCoMKgIGZpbHRlcl9tb2RlID0gKih1OCAqKWh3Yy0+YWRkcl9maWx0ZXJzOwo+PiArwqDCoMKg IHN3aXRjaCAoZmlsdGVyX21vZGUpIHsKPj4gK8KgwqDCoCBjYXNlIEhOUzNfUE1VX0hXX0ZJTFRF Ul9QT1JUOgo+PiArwqDCoMKgwqDCoMKgwqAgZmlsdGVyID0gRklMVEVSX0NPTkRJVElPTl9QT1JU KHBvcnRfaWQpOwo+PiArwqDCoMKgwqDCoMKgwqAgYnJlYWs7Cj4+ICvCoMKgwqAgY2FzZSBITlMz X1BNVV9IV19GSUxURVJfUE9SVF9UQzoKPj4gK8KgwqDCoMKgwqDCoMKgIGZpbHRlciA9IEZJTFRF Ul9DT05ESVRJT05fUE9SVF9UQyhwb3J0X2lkLCB0Y19pZCk7Cj4+ICvCoMKgwqDCoMKgwqDCoCBi cmVhazsKPj4gK8KgwqDCoCBjYXNlIEhOUzNfUE1VX0hXX0ZJTFRFUl9GVU5DOgo+PiArwqDCoMKg IGNhc2UgSE5TM19QTVVfSFdfRklMVEVSX0ZVTkNfUVVFVUU6Cj4+ICvCoMKgwqDCoMKgwqDCoCBm aWx0ZXIgPSBHRVRfUENJX0RFVkZOKGJkZik7Cj4+ICvCoMKgwqDCoMKgwqDCoCBicmVhazsKPj4g K8KgwqDCoCBjYXNlIEhOUzNfUE1VX0hXX0ZJTFRFUl9GVU5DX0lOVFI6Cj4+ICvCoMKgwqDCoMKg wqDCoCBmaWx0ZXIgPSBGSUxURVJfQ09ORElUSU9OX0ZVTkNfSU5UUihHRVRfUENJX0RFVkZOKGJk ZiksCj4+ICvCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqAgaW50cl9pZCk7Cj4+ICvCoMKgwqDCoMKgwqDCoCBicmVhazsKPj4gK8KgwqDCoCBkZWZh dWx0Ogo+PiArwqDCoMKgwqDCoMKgwqAgYnJlYWs7Cj4+ICvCoMKgwqAgfQo+PiArCj4+ICvCoMKg wqAgcmV0dXJuIGZpbHRlcjsKPj4gK30KPj4gKwo+PiArc3RhdGljIHZvaWQgaG5zM19wbXVfY29u ZmlnX2ZpbHRlcihzdHJ1Y3QgcGVyZl9ldmVudCAqZXZlbnQpCj4+ICt7Cj4+ICvCoMKgwqAgc3Ry dWN0IGhuczNfcG11ICpobnMzX3BtdSA9IHRvX2huczNfcG11KGV2ZW50LT5wbXUpOwo+PiArwqDC oMKgIHU4IGV2ZW50X3R5cGUgPSBobnMzX2dldF9ldmVudF90eXBlKGV2ZW50KTsKPj4gK8KgwqDC oCB1OCBzdWJldmVudF9pZCA9IGhuczNfZ2V0X3N1YmV2ZW50KGV2ZW50KTsKPj4gK8KgwqDCoCBz dHJ1Y3QgaHdfcGVyZl9ldmVudCAqaHdjID0gJmV2ZW50LT5odzsKPj4gK8KgwqDCoCB1OCBmaWx0 ZXJfbW9kZSA9ICoodTggKilod2MtPmFkZHJfZmlsdGVyczsKPj4gK8KgwqDCoCB1MTYgcXVldWVf aWQgPSBobnMzX2dldF9xdWV1ZShldmVudCk7Cj4+ICvCoMKgwqAgdTE2IGJkZiA9IGhuczNfZ2V0 X2JkZihldmVudCk7Cj4+ICvCoMKgwqAgdTMyIGlkeCA9IGh3Yy0+aWR4Owo+PiArwqDCoMKgIHUz MiB2YWw7Cj4+ICsKPj4gK8KgwqDCoCB2YWwgPSBldmVudF90eXBlOwo+PiArwqDCoMKgIHZhbCB8 PSBzdWJldmVudF9pZCA8PCBITlMzX1BNVV9DVFJMX1NVQkVWRU5UX1M7Cj4+ICvCoMKgwqAgdmFs IHw9IGZpbHRlcl9tb2RlIDw8IEhOUzNfUE1VX0NUUkxfRklMVEVSX01PREVfUzsKPj4gK8KgwqDC oCB2YWwgfD0gSE5TM19QTVVfRVZFTlRfT1ZFUkZMT1dfUkVTVEFSVDsKPj4gK8KgwqDCoCBobnMz X3BtdV93cml0ZWwoaG5zM19wbXUsIEhOUzNfUE1VX1JFR19FVkVOVF9DVFJMX0xPVywgaWR4LCB2 YWwpOwo+PiArCj4+ICvCoMKgwqAgdmFsID0gaG5zM19wbXVfZ2V0X2ZpbHRlcl9jb25kaXRpb24o ZXZlbnQpOwo+PiArwqDCoMKgIGhuczNfcG11X3dyaXRlbChobnMzX3BtdSwgSE5TM19QTVVfUkVH X0VWRU5UX0NUUkxfSElHSCwgaWR4LCB2YWwpOwo+PiArCj4+ICvCoMKgwqAgaWYgKGZpbHRlcl9t b2RlID09IEhOUzNfUE1VX0hXX0ZJTFRFUl9GVU5DX1FVRVVFKQo+PiArwqDCoMKgwqDCoMKgwqAg aG5zM19wbXVfc2V0X3FpZF9wYXJhKGhuczNfcG11LCBpZHgsIGJkZiwgcXVldWVfaWQpOwo+PiAr fQo+PiArCj4+ICtzdGF0aWMgdm9pZCBobnMzX3BtdV9lbmFibGVfY291bnRlcihzdHJ1Y3QgaG5z M19wbXUgKmhuczNfcG11LAo+PiArwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqAgc3RydWN0IGh3X3BlcmZfZXZlbnQgKmh3YykKPj4gK3sKPj4gK8KgwqDCoCB1MzIgaWR4ID0g aHdjLT5pZHg7Cj4+ICvCoMKgwqAgdTMyIHZhbDsKPj4gKwo+PiArwqDCoMKgIHZhbCA9IGhuczNf cG11X3JlYWRsKGhuczNfcG11LCBITlMzX1BNVV9SRUdfRVZFTlRfQ1RSTF9MT1csIGlkeCk7Cj4+ ICvCoMKgwqAgdmFsIHw9IEhOUzNfUE1VX0VWRU5UX0VOOwo+PiArwqDCoMKgIGhuczNfcG11X3dy aXRlbChobnMzX3BtdSwgSE5TM19QTVVfUkVHX0VWRU5UX0NUUkxfTE9XLCBpZHgsIHZhbCk7Cj4+ ICt9Cj4+ICsKPj4gK3N0YXRpYyB2b2lkIGhuczNfcG11X2Rpc2FibGVfY291bnRlcihzdHJ1Y3Qg aG5zM19wbXUgKmhuczNfcG11LAo+PiArwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoCBzdHJ1Y3QgaHdfcGVyZl9ldmVudCAqaHdjKQo+PiArewo+PiArwqDCoMKgIHUzMiBp ZHggPSBod2MtPmlkeDsKPj4gK8KgwqDCoCB1MzIgdmFsOwo+PiArCj4+ICvCoMKgwqAgdmFsID0g aG5zM19wbXVfcmVhZGwoaG5zM19wbXUsIEhOUzNfUE1VX1JFR19FVkVOVF9DVFJMX0xPVywgaWR4 KTsKPj4gK8KgwqDCoCB2YWwgJj0gfkhOUzNfUE1VX0VWRU5UX0VOOwo+PiArwqDCoMKgIGhuczNf cG11X3dyaXRlbChobnMzX3BtdSwgSE5TM19QTVVfUkVHX0VWRU5UX0NUUkxfTE9XLCBpZHgsIHZh bCk7Cj4+ICt9Cj4+ICsKPj4gK3N0YXRpYyB2b2lkIGhuczNfcG11X2VuYWJsZV9pbnRyKHN0cnVj dCBobnMzX3BtdSAqaG5zM19wbXUsCj4+ICvCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oCBzdHJ1Y3QgaHdfcGVyZl9ldmVudCAqaHdjKQo+PiArewo+PiArwqDCoMKgIHUzMiBpZHggPSBo d2MtPmlkeDsKPj4gK8KgwqDCoCB1MzIgdmFsOwo+PiArCj4+ICvCoMKgwqAgdmFsID0gaG5zM19w bXVfcmVhZGwoaG5zM19wbXUsIEhOUzNfUE1VX1JFR19FVkVOVF9JTlRSX01BU0ssIGlkeCk7Cj4+ ICvCoMKgwqAgdmFsICY9IH5ITlMzX1BNVV9JTlRSX01BU0tfT1ZFUkZMT1c7Cj4+ICvCoMKgwqAg aG5zM19wbXVfd3JpdGVsKGhuczNfcG11LCBITlMzX1BNVV9SRUdfRVZFTlRfSU5UUl9NQVNLLCBp ZHgsIHZhbCk7Cj4+ICt9Cj4+ICsKPj4gK3N0YXRpYyB2b2lkIGhuczNfcG11X2Rpc2FibGVfaW50 cihzdHJ1Y3QgaG5zM19wbXUgKmhuczNfcG11LAo+PiArwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoCBzdHJ1Y3QgaHdfcGVyZl9ldmVudCAqaHdjKQo+PiArewo+PiArwqDCoMKgIHUz MiBpZHggPSBod2MtPmlkeDsKPj4gK8KgwqDCoCB1MzIgdmFsOwo+PiArCj4+ICvCoMKgwqAgdmFs ID0gaG5zM19wbXVfcmVhZGwoaG5zM19wbXUsIEhOUzNfUE1VX1JFR19FVkVOVF9JTlRSX01BU0ss IGlkeCk7Cj4+ICvCoMKgwqAgdmFsIHw9IEhOUzNfUE1VX0lOVFJfTUFTS19PVkVSRkxPVzsKPj4g K8KgwqDCoCBobnMzX3BtdV93cml0ZWwoaG5zM19wbXUsIEhOUzNfUE1VX1JFR19FVkVOVF9JTlRS X01BU0ssIGlkeCwgdmFsKTsKPj4gK30KPj4gKwo+PiArc3RhdGljIHZvaWQgaG5zM19wbXVfY2xl YXJfaW50cl9zdGF0dXMoc3RydWN0IGhuczNfcG11ICpobnMzX3BtdSwgdTMyIGlkeCkKPj4gK3sK Pj4gK8KgwqDCoCB1MzIgdmFsOwo+PiArCj4+ICvCoMKgwqAgdmFsID0gaG5zM19wbXVfcmVhZGwo aG5zM19wbXUsIEhOUzNfUE1VX1JFR19FVkVOVF9DVFJMX0xPVywgaWR4KTsKPj4gK8KgwqDCoCB2 YWwgfD0gSE5TM19QTVVfRVZFTlRfU1RBVFVTX1JFU0VUOwo+PiArwqDCoMKgIGhuczNfcG11X3dy aXRlbChobnMzX3BtdSwgSE5TM19QTVVfUkVHX0VWRU5UX0NUUkxfTE9XLCBpZHgsIHZhbCk7Cj4+ ICsKPj4gK8KgwqDCoCB2YWwgPSBobnMzX3BtdV9yZWFkbChobnMzX3BtdSwgSE5TM19QTVVfUkVH X0VWRU5UX0NUUkxfTE9XLCBpZHgpOwo+PiArwqDCoMKgIHZhbCAmPSB+SE5TM19QTVVfRVZFTlRf U1RBVFVTX1JFU0VUOwo+PiArwqDCoMKgIGhuczNfcG11X3dyaXRlbChobnMzX3BtdSwgSE5TM19Q TVVfUkVHX0VWRU5UX0NUUkxfTE9XLCBpZHgsIHZhbCk7Cj4+ICt9Cj4+ICsKPj4gK3N0YXRpYyB1 NjQgaG5zM19wbXVfcmVhZF9jb3VudGVyKHN0cnVjdCBwZXJmX2V2ZW50ICpldmVudCkKPj4gK3sK Pj4gK8KgwqDCoCBzdHJ1Y3QgaG5zM19wbXUgKmhuczNfcG11ID0gdG9faG5zM19wbXUoZXZlbnQt PnBtdSk7Cj4+ICsKPj4gK8KgwqDCoCByZXR1cm4gaG5zM19wbXVfcmVhZHEoaG5zM19wbXUsIGV2 ZW50LT5ody5ldmVudF9iYXNlLCBldmVudC0+aHcuaWR4KTsKPj4gK30KPj4gKwo+PiArc3RhdGlj IHZvaWQgaG5zM19wbXVfd3JpdGVfY291bnRlcihzdHJ1Y3QgcGVyZl9ldmVudCAqZXZlbnQsIHU2 NCB2YWx1ZSkKPj4gK3sKPj4gK8KgwqDCoCBzdHJ1Y3QgaG5zM19wbXUgKmhuczNfcG11ID0gdG9f aG5zM19wbXUoZXZlbnQtPnBtdSk7Cj4+ICvCoMKgwqAgdTMyIGlkeCA9IGV2ZW50LT5ody5pZHg7 Cj4+ICsKPj4gK8KgwqDCoCBobnMzX3BtdV93cml0ZXEoaG5zM19wbXUsIEhOUzNfUE1VX1JFR19F VkVOVF9DT1VOVEVSLCBpZHgsIHZhbHVlKTsKPj4gK8KgwqDCoCBobnMzX3BtdV93cml0ZXEoaG5z M19wbXUsIEhOUzNfUE1VX1JFR19FVkVOVF9FWFRfQ09VTlRFUiwgaWR4LCB2YWx1ZSk7Cj4+ICt9 Cj4+ICsKPj4gK3N0YXRpYyB2b2lkIGhuczNfcG11X2luaXRfY291bnRlcihzdHJ1Y3QgcGVyZl9l dmVudCAqZXZlbnQpCj4+ICt7Cj4+ICvCoMKgwqAgc3RydWN0IGh3X3BlcmZfZXZlbnQgKmh3YyA9 ICZldmVudC0+aHc7Cj4+ICsKPj4gK8KgwqDCoCBsb2NhbDY0X3NldCgmaHdjLT5wcmV2X2NvdW50 LCAwKTsKPj4gK8KgwqDCoCBobnMzX3BtdV93cml0ZV9jb3VudGVyKGV2ZW50LCAwKTsKPj4gK30K Pj4gKwo+PiArc3RhdGljIGludCBobnMzX3BtdV9ldmVudF9pbml0KHN0cnVjdCBwZXJmX2V2ZW50 ICpldmVudCkKPj4gK3sKPj4gK8KgwqDCoCBzdHJ1Y3QgaG5zM19wbXUgKmhuczNfcG11ID0gdG9f aG5zM19wbXUoZXZlbnQtPnBtdSk7Cj4+ICvCoMKgwqAgc3RydWN0IGh3X3BlcmZfZXZlbnQgKmh3 YyA9ICZldmVudC0+aHc7Cj4+ICvCoMKgwqAgaW50IGlkeDsKPj4gK8KgwqDCoCBpbnQgcmV0Owo+ PiArCj4+ICvCoMKgwqAgaWYgKGV2ZW50LT5hdHRyLnR5cGUgIT0gZXZlbnQtPnBtdS0+dHlwZSkK Pj4gK8KgwqDCoMKgwqDCoMKgIHJldHVybiAtRU5PRU5UOwo+PiArCj4+ICvCoMKgwqAgLyogU2Ft cGxpbmcgaXMgbm90IHN1cHBvcnRlZCAqLwo+PiArwqDCoMKgIGlmIChpc19zYW1wbGluZ19ldmVu dChldmVudCkgfHwgZXZlbnQtPmF0dGFjaF9zdGF0ZSAmIFBFUkZfQVRUQUNIX1RBU0spCj4+ICvC oMKgwqDCoMKgwqDCoCByZXR1cm4gLUVPUE5PVFNVUFA7Cj4+ICsKPj4gK8KgwqDCoCBldmVudC0+ Y3B1ID0gaG5zM19wbXUtPm9uX2NwdTsKPj4gKwo+PiArwqDCoMKgIGlkeCA9IGhuczNfcG11X2dl dF9ldmVudF9pZHgoaG5zM19wbXUpOwo+PiArwqDCoMKgIGlmIChpZHggPCAwKSB7Cj4+ICvCoMKg wqDCoMKgwqDCoCBwY2lfZXJyKGhuczNfcG11LT5wZGV2LCAiVXAgdG8gJXUgZXZlbnRzIGFyZSBz dXBwb3J0ZWQhXG4iLAo+PiArwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCBITlMzX1BNVV9NQVhfSFdf RVZFTlRTKTsKPj4gK8KgwqDCoMKgwqDCoMKgIHJldHVybiAtRUJVU1k7Cj4+ICvCoMKgwqAgfQo+ PiArCj4+ICvCoMKgwqAgaHdjLT5pZHggPSBpZHg7Cj4+ICsKPj4gK8KgwqDCoCByZXQgPSBobnMz X3BtdV9zZWxlY3RfZmlsdGVyX21vZGUoZXZlbnQsIGhuczNfcG11KTsKPj4gK8KgwqDCoCBpZiAo cmV0KSB7Cj4+ICvCoMKgwqDCoMKgwqDCoCBwY2lfZXJyKGhuczNfcG11LT5wZGV2LCAiSW52YWxp ZCBmaWx0ZXIsIHJldCA9ICVkLlxuIiwgcmV0KTsKPj4gK8KgwqDCoMKgwqDCoMKgIHJldHVybiBy ZXQ7Cj4+ICvCoMKgwqAgfQo+PiArCj4+ICvCoMKgwqAgaWYgKCFobnMzX3BtdV92YWxpZGF0ZV9l dmVudF9ncm91cChldmVudCkpIHsKPj4gK8KgwqDCoMKgwqDCoMKgIHBjaV9lcnIoaG5zM19wbXUt PnBkZXYsICJJbnZhbGlkIGV2ZW50IGdyb3VwLlxuIik7Cj4+ICvCoMKgwqDCoMKgwqDCoCByZXR1 cm4gLUVJTlZBTDsKPj4gK8KgwqDCoCB9Cj4+ICsKPj4gK8KgwqDCoCBpZiAoaG5zM19nZXRfZXh0 X2NvdW50ZXJfdXNlZChldmVudCkpCj4+ICvCoMKgwqDCoMKgwqDCoCBod2MtPmV2ZW50X2Jhc2Ug PSBITlMzX1BNVV9SRUdfRVZFTlRfRVhUX0NPVU5URVI7Cj4+ICvCoMKgwqAgZWxzZQo+PiArwqDC oMKgwqDCoMKgwqAgaHdjLT5ldmVudF9iYXNlID0gSE5TM19QTVVfUkVHX0VWRU5UX0NPVU5URVI7 Cj4+ICsKPj4gK8KgwqDCoCByZXR1cm4gMDsKPj4gK30KPj4gKwo+PiArc3RhdGljIHZvaWQgaG5z M19wbXVfcmVhZChzdHJ1Y3QgcGVyZl9ldmVudCAqZXZlbnQpCj4+ICt7Cj4+ICvCoMKgwqAgc3Ry dWN0IGh3X3BlcmZfZXZlbnQgKmh3YyA9ICZldmVudC0+aHc7Cj4+ICvCoMKgwqAgdTY0IG5ld19j bnQsIHByZXZfY250LCBkZWx0YTsKPj4gKwo+PiArwqDCoMKgIGRvIHsKPj4gK8KgwqDCoMKgwqDC oMKgIHByZXZfY250ID0gbG9jYWw2NF9yZWFkKCZod2MtPnByZXZfY291bnQpOwo+PiArwqDCoMKg wqDCoMKgwqAgbmV3X2NudCA9IGhuczNfcG11X3JlYWRfY291bnRlcihldmVudCk7Cj4+ICvCoMKg wqAgfSB3aGlsZSAobG9jYWw2NF9jbXB4Y2hnKCZod2MtPnByZXZfY291bnQsIHByZXZfY250LCBu ZXdfY250KSAhPQo+PiArwqDCoMKgwqDCoMKgwqDCoCBwcmV2X2NudCk7Cj4+ICsKPj4gK8KgwqDC oCBkZWx0YSA9IG5ld19jbnQgLSBwcmV2X2NudDsKPj4gK8KgwqDCoCBsb2NhbDY0X2FkZChkZWx0 YSwgJmV2ZW50LT5jb3VudCk7Cj4+ICt9Cj4+ICsKPj4gK3N0YXRpYyB2b2lkIGhuczNfcG11X3N0 YXJ0KHN0cnVjdCBwZXJmX2V2ZW50ICpldmVudCwgaW50IGZsYWdzKQo+PiArewo+PiArwqDCoMKg IHN0cnVjdCBobnMzX3BtdSAqaG5zM19wbXUgPSB0b19obnMzX3BtdShldmVudC0+cG11KTsKPj4g K8KgwqDCoCBzdHJ1Y3QgaHdfcGVyZl9ldmVudCAqaHdjID0gJmV2ZW50LT5odzsKPj4gKwo+PiAr wqDCoMKgIGlmIChXQVJOX09OX09OQ0UoIShod2MtPnN0YXRlICYgUEVSRl9IRVNfU1RPUFBFRCkp KQo+PiArwqDCoMKgwqDCoMKgwqAgcmV0dXJuOwo+PiArCj4+ICvCoMKgwqAgV0FSTl9PTl9PTkNF KCEoaHdjLT5zdGF0ZSAmIFBFUkZfSEVTX1VQVE9EQVRFKSk7Cj4+ICvCoMKgwqAgaHdjLT5zdGF0 ZSA9IDA7Cj4+ICsKPj4gK8KgwqDCoCBobnMzX3BtdV9jb25maWdfZmlsdGVyKGV2ZW50KTsKPj4g K8KgwqDCoCBobnMzX3BtdV9pbml0X2NvdW50ZXIoZXZlbnQpOwo+PiArwqDCoMKgIGhuczNfcG11 X2VuYWJsZV9pbnRyKGhuczNfcG11LCBod2MpOwo+PiArwqDCoMKgIGhuczNfcG11X2VuYWJsZV9j b3VudGVyKGhuczNfcG11LCBod2MpOwo+PiArCj4+ICvCoMKgwqAgcGVyZl9ldmVudF91cGRhdGVf dXNlcnBhZ2UoZXZlbnQpOwo+PiArfQo+PiArCj4+ICtzdGF0aWMgdm9pZCBobnMzX3BtdV9zdG9w KHN0cnVjdCBwZXJmX2V2ZW50ICpldmVudCwgaW50IGZsYWdzKQo+PiArewo+PiArwqDCoMKgIHN0 cnVjdCBobnMzX3BtdSAqaG5zM19wbXUgPSB0b19obnMzX3BtdShldmVudC0+cG11KTsKPj4gK8Kg wqDCoCBzdHJ1Y3QgaHdfcGVyZl9ldmVudCAqaHdjID0gJmV2ZW50LT5odzsKPj4gKwo+PiArwqDC oMKgIGhuczNfcG11X2Rpc2FibGVfY291bnRlcihobnMzX3BtdSwgaHdjKTsKPj4gK8KgwqDCoCBo bnMzX3BtdV9kaXNhYmxlX2ludHIoaG5zM19wbXUsIGh3Yyk7Cj4+ICsKPj4gK8KgwqDCoCBXQVJO X09OX09OQ0UoaHdjLT5zdGF0ZSAmIFBFUkZfSEVTX1NUT1BQRUQpOwo+PiArwqDCoMKgIGh3Yy0+ c3RhdGUgfD0gUEVSRl9IRVNfU1RPUFBFRDsKPj4gKwo+PiArwqDCoMKgIGlmIChod2MtPnN0YXRl ICYgUEVSRl9IRVNfVVBUT0RBVEUpCj4+ICvCoMKgwqDCoMKgwqDCoCByZXR1cm47Cj4+ICsKPj4g K8KgwqDCoCAvKiBSZWFkIGhhcmR3YXJlIGNvdW50ZXIgYW5kIHVwZGF0ZSB0aGUgcGVyZiBjb3Vu dGVyIHN0YXRpc3RpY3MgKi8KPj4gK8KgwqDCoCBobnMzX3BtdV9yZWFkKGV2ZW50KTsKPj4gK8Kg wqDCoCBod2MtPnN0YXRlIHw9IFBFUkZfSEVTX1VQVE9EQVRFOwo+PiArfQo+PiArCj4+ICtzdGF0 aWMgaW50IGhuczNfcG11X2FkZChzdHJ1Y3QgcGVyZl9ldmVudCAqZXZlbnQsIGludCBmbGFncykK Pj4gK3sKPj4gK8KgwqDCoCBzdHJ1Y3QgaG5zM19wbXUgKmhuczNfcG11ID0gdG9faG5zM19wbXUo ZXZlbnQtPnBtdSk7Cj4+ICvCoMKgwqAgc3RydWN0IGh3X3BlcmZfZXZlbnQgKmh3YyA9ICZldmVu dC0+aHc7Cj4+ICvCoMKgwqAgaW50IGlkeDsKPj4gKwo+PiArwqDCoMKgIGh3Yy0+c3RhdGUgPSBQ RVJGX0hFU19TVE9QUEVEIHwgUEVSRl9IRVNfVVBUT0RBVEU7Cj4+ICsKPj4gK8KgwqDCoCAvKiBD aGVjayBhbGwgd29ya2luZyBldmVudHMgdG8gZmluZCBhIHJlbGF0ZWQgZXZlbnQuICovCj4+ICvC oMKgwqAgaWR4ID0gaG5zM19wbXVfZmluZF9yZWxhdGVkX2V2ZW50KGhuczNfcG11LCBldmVudCk7 Cj4+ICvCoMKgwqAgaWYgKGlkeCA8IDApCj4+ICvCoMKgwqDCoMKgwqDCoCByZXR1cm4gaWR4Owo+ PiArCj4+ICvCoMKgwqAgLyogQ3VycmVudCBldmVudCBzaGFyZXMgYW4gZW5hYmxlZCBoYXJkd2Fy ZSBldmVudCB3aXRoIHJlbGF0ZWQgZXZlbnQgKi8KPj4gK8KgwqDCoCBpZiAoaWR4IDwgSE5TM19Q TVVfTUFYX0hXX0VWRU5UUykgewo+PiArwqDCoMKgwqDCoMKgwqAgaHdjLT5pZHggPSBpZHg7Cj4+ ICvCoMKgwqDCoMKgwqDCoCBnb3RvIHN0YXJ0X2NvdW50Owo+PiArwqDCoMKgIH0KPj4gKwo+PiAr wqDCoMKgIGlkeCA9IGhuczNfcG11X2dldF9ldmVudF9pZHgoaG5zM19wbXUpOwo+PiArwqDCoMKg IGlmIChpZHggPCAwKQo+PiArwqDCoMKgwqDCoMKgwqAgcmV0dXJuIGlkeDsKPj4gKwo+PiArwqDC oMKgIGh3Yy0+aWR4ID0gaWR4Owo+PiArwqDCoMKgIGhuczNfcG11LT5od19ldmVudHNbaWR4XSA9 IGV2ZW50Owo+PiArCj4+ICtzdGFydF9jb3VudDoKPj4gK8KgwqDCoCBpZiAoZmxhZ3MgJiBQRVJG X0VGX1NUQVJUKQo+PiArwqDCoMKgwqDCoMKgwqAgaG5zM19wbXVfc3RhcnQoZXZlbnQsIFBFUkZf RUZfUkVMT0FEKTsKPj4gKwo+PiArwqDCoMKgIHJldHVybiAwOwo+PiArfQo+PiArCj4+ICtzdGF0 aWMgdm9pZCBobnMzX3BtdV9kZWwoc3RydWN0IHBlcmZfZXZlbnQgKmV2ZW50LCBpbnQgZmxhZ3Mp Cj4+ICt7Cj4+ICvCoMKgwqAgc3RydWN0IGhuczNfcG11ICpobnMzX3BtdSA9IHRvX2huczNfcG11 KGV2ZW50LT5wbXUpOwo+PiArwqDCoMKgIHN0cnVjdCBod19wZXJmX2V2ZW50ICpod2MgPSAmZXZl bnQtPmh3Owo+PiArCj4+ICvCoMKgwqAgaG5zM19wbXVfc3RvcChldmVudCwgUEVSRl9FRl9VUERB VEUpOwo+PiArwqDCoMKgIGhuczNfcG11LT5od19ldmVudHNbaHdjLT5pZHhdID0gTlVMTDsKPj4g K8KgwqDCoCBwZXJmX2V2ZW50X3VwZGF0ZV91c2VycGFnZShldmVudCk7Cj4+ICt9Cj4+ICsKPj4g K3N0YXRpYyB2b2lkIGhuczNfcG11X2VuYWJsZShzdHJ1Y3QgcG11ICpwbXUpCj4+ICt7Cj4+ICvC oMKgwqAgc3RydWN0IGhuczNfcG11ICpobnMzX3BtdSA9IHRvX2huczNfcG11KHBtdSk7Cj4+ICvC oMKgwqAgdTMyIHZhbDsKPj4gKwo+PiArwqDCoMKgIHZhbCA9IHJlYWRsKGhuczNfcG11LT5iYXNl ICsgSE5TM19QTVVfUkVHX0dMT0JBTF9DVFJMKTsKPj4gK8KgwqDCoCB2YWwgfD0gSE5TM19QTVVf R0xPQkFMX1NUQVJUOwo+PiArwqDCoMKgIHdyaXRlbCh2YWwsIGhuczNfcG11LT5iYXNlICsgSE5T M19QTVVfUkVHX0dMT0JBTF9DVFJMKTsKPj4gK30KPj4gKwo+PiArc3RhdGljIHZvaWQgaG5zM19w bXVfZGlzYWJsZShzdHJ1Y3QgcG11ICpwbXUpCj4+ICt7Cj4+ICvCoMKgwqAgc3RydWN0IGhuczNf cG11ICpobnMzX3BtdSA9IHRvX2huczNfcG11KHBtdSk7Cj4+ICvCoMKgwqAgdTMyIHZhbDsKPj4g Kwo+PiArwqDCoMKgIHZhbCA9IHJlYWRsKGhuczNfcG11LT5iYXNlICsgSE5TM19QTVVfUkVHX0dM T0JBTF9DVFJMKTsKPj4gK8KgwqDCoCB2YWwgJj0gfkhOUzNfUE1VX0dMT0JBTF9TVEFSVDsKPj4g K8KgwqDCoCB3cml0ZWwodmFsLCBobnMzX3BtdS0+YmFzZSArIEhOUzNfUE1VX1JFR19HTE9CQUxf Q1RSTCk7Cj4+ICt9Cj4+ICsKPj4gK3N0YXRpYyBpbnQgaG5zM19wbXVfYWxsb2NfcG11KHN0cnVj dCBwY2lfZGV2ICpwZGV2LCBzdHJ1Y3QgaG5zM19wbXUgKmhuczNfcG11KQo+PiArewo+PiArwqDC oMKgIHUxNiBkZXZpY2VfaWQ7Cj4+ICvCoMKgwqAgY2hhciAqbmFtZTsKPj4gK8KgwqDCoCB1MzIg dmFsOwo+PiArCj4+ICvCoMKgwqAgaG5zM19wbXUtPmJhc2UgPSBwY2ltX2lvbWFwX3RhYmxlKHBk ZXYpW0JBUl8yXTsKPj4gK8KgwqDCoCBpZiAoIWhuczNfcG11LT5iYXNlKSB7Cj4+ICvCoMKgwqDC oMKgwqDCoCBwY2lfZXJyKHBkZXYsICJpb3JlbWFwIGZhaWxlZCBmb3IgaG5zM19wbXUgcmVzb3Vy Y2VcbiIpOwo+PiArwqDCoMKgwqDCoMKgwqAgcmV0dXJuIC1FTk9NRU07Cj4+ICvCoMKgwqAgfQo+ PiArCj4+ICvCoMKgwqAgaG5zM19wbXUtPmh3X2Nsa19mcmVxID0gcmVhZGwoaG5zM19wbXUtPmJh c2UgKyBITlMzX1BNVV9SRUdfQ0xPQ0tfRlJFUSk7Cj4+ICsKPj4gK8KgwqDCoCB2YWwgPSByZWFk bChobnMzX3BtdS0+YmFzZSArIEhOUzNfUE1VX1JFR19CREYpOwo+PiArwqDCoMKgIGhuczNfcG11 LT5iZGZfbWluID0gdmFsICYgMHhmZmZmOwo+PiArwqDCoMKgIGhuczNfcG11LT5iZGZfbWF4ID0g dmFsID4+IDE2Owo+PiArCj4+ICvCoMKgwqAgdmFsID0gcmVhZGwoaG5zM19wbXUtPmJhc2UgKyBI TlMzX1BNVV9SRUdfREVWSUNFX0lEKTsKPj4gK8KgwqDCoCBkZXZpY2VfaWQgPSB2YWwgJiAweGZm ZmY7Cj4+ICvCoMKgwqAgbmFtZSA9IGRldm1fa2FzcHJpbnRmKCZwZGV2LT5kZXYsIEdGUF9LRVJO RUwsICJobnMzX3BtdV9zaWNsXyV1IiwgZGV2aWNlX2lkKTsKPj4gK8KgwqDCoCBpZiAoIW5hbWUp Cj4+ICvCoMKgwqDCoMKgwqDCoCByZXR1cm4gLUVOT01FTTsKPj4gKwo+PiArwqDCoMKgIGhuczNf cG11LT5wZGV2ID0gcGRldjsKPj4gK8KgwqDCoCBobnMzX3BtdS0+b25fY3B1ID0gLTE7Cj4+ICvC oMKgwqAgaG5zM19wbXUtPmlkZW50aWZpZXIgPSByZWFkbChobnMzX3BtdS0+YmFzZSArIEhOUzNf UE1VX1JFR19WRVJTSU9OKTsKPj4gK8KgwqDCoCBobnMzX3BtdS0+cG11ID0gKHN0cnVjdCBwbXUp IHsKPj4gK8KgwqDCoMKgwqDCoMKgIC5uYW1lwqDCoMKgwqDCoMKgwqAgPSBuYW1lLAo+PiArwqDC oMKgwqDCoMKgwqAgLm1vZHVsZcKgwqDCoMKgwqDCoMKgID0gVEhJU19NT0RVTEUsCj4+ICvCoMKg wqDCoMKgwqDCoCAuZXZlbnRfaW5pdMKgwqDCoCA9IGhuczNfcG11X2V2ZW50X2luaXQsCj4+ICvC oMKgwqDCoMKgwqDCoCAucG11X2VuYWJsZcKgwqDCoCA9IGhuczNfcG11X2VuYWJsZSwKPj4gK8Kg wqDCoMKgwqDCoMKgIC5wbXVfZGlzYWJsZcKgwqDCoCA9IGhuczNfcG11X2Rpc2FibGUsCj4+ICvC oMKgwqDCoMKgwqDCoCAuYWRkwqDCoMKgwqDCoMKgwqAgPSBobnMzX3BtdV9hZGQsCj4+ICvCoMKg wqDCoMKgwqDCoCAuZGVswqDCoMKgwqDCoMKgwqAgPSBobnMzX3BtdV9kZWwsCj4+ICvCoMKgwqDC oMKgwqDCoCAuc3RhcnTCoMKgwqDCoMKgwqDCoCA9IGhuczNfcG11X3N0YXJ0LAo+PiArwqDCoMKg wqDCoMKgwqAgLnN0b3DCoMKgwqDCoMKgwqDCoCA9IGhuczNfcG11X3N0b3AsCj4+ICvCoMKgwqDC oMKgwqDCoCAucmVhZMKgwqDCoMKgwqDCoMKgID0gaG5zM19wbXVfcmVhZCwKPj4gK8KgwqDCoMKg wqDCoMKgIC50YXNrX2N0eF9ucsKgwqDCoCA9IHBlcmZfaW52YWxpZF9jb250ZXh0LAo+PiArwqDC oMKgwqDCoMKgwqAgLmF0dHJfZ3JvdXBzwqDCoMKgID0gaG5zM19wbXVfYXR0cl9ncm91cHMsCj4+ ICvCoMKgwqDCoMKgwqDCoCAuY2FwYWJpbGl0aWVzwqDCoMKgID0gUEVSRl9QTVVfQ0FQX05PX0VY Q0xVREUsCj4+ICvCoMKgwqAgfTsKPj4gKwo+PiArwqDCoMKgIHJldHVybiAwOwo+PiArfQo+PiAr Cj4+ICtzdGF0aWMgaXJxcmV0dXJuX3QgaG5zM19wbXVfaXJxKGludCBpcnEsIHZvaWQgKmRhdGEp Cj4+ICt7Cj4+ICvCoMKgwqAgc3RydWN0IGhuczNfcG11ICpobnMzX3BtdSA9IGRhdGE7Cj4+ICvC oMKgwqAgdTMyIGludHJfc3RhdHVzLCBpZHg7Cj4+ICsKPj4gK8KgwqDCoCBmb3IgKGlkeCA9IDA7 IGlkeCA8IEhOUzNfUE1VX01BWF9IV19FVkVOVFM7IGlkeCsrKSB7Cj4+ICvCoMKgwqDCoMKgwqDC oCBpbnRyX3N0YXR1cyA9IGhuczNfcG11X3JlYWRsKGhuczNfcG11LAo+PiArwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIEhOUzNfUE1VX1JFR19FVkVOVF9J TlRSX1NUQVRVUywKPj4gK8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoCBpZHgpOwo+PiArCj4+ICvCoMKgwqDCoMKgwqDCoCAvKgo+PiArwqDCoMKgwqDCoMKg wqDCoCAqIEFzIGVhY2ggY291bnRlciB3aWxsIHJlc3RhcnQgZnJvbSAwIHdoZW4gaXQgaXMgb3Zl cmZsb3dlZCwKPj4gK8KgwqDCoMKgwqDCoMKgwqAgKiBleHRyYSBwcm9jZXNzaW5nIGlzIG5vIG5l ZWQsIGp1c3QgY2xlYXIgaW50ZXJydXB0IHN0YXR1cy4KPj4gK8KgwqDCoMKgwqDCoMKgwqAgKi8K Pj4gK8KgwqDCoMKgwqDCoMKgIGlmIChpbnRyX3N0YXR1cykKPj4gK8KgwqDCoMKgwqDCoMKgwqDC oMKgwqAgaG5zM19wbXVfY2xlYXJfaW50cl9zdGF0dXMoaG5zM19wbXUsIGlkeCk7Cj4+ICvCoMKg wqAgfQo+PiArCj4+ICvCoMKgwqAgcmV0dXJuIElSUV9IQU5ETEVEOwo+PiArfQo+PiArCj4+ICtz dGF0aWMgaW50IGhuczNfcG11X29ubGluZV9jcHUodW5zaWduZWQgaW50IGNwdSwgc3RydWN0IGhs aXN0X25vZGUgKm5vZGUpCj4+ICt7Cj4+ICvCoMKgwqAgc3RydWN0IGhuczNfcG11ICpobnMzX3Bt dTsKPj4gKwo+PiArwqDCoMKgIGhuczNfcG11ID0gaGxpc3RfZW50cnlfc2FmZShub2RlLCBzdHJ1 Y3QgaG5zM19wbXUsIG5vZGUpOwo+PiArwqDCoMKgIGlmICghaG5zM19wbXUpCj4+ICvCoMKgwqDC oMKgwqDCoCByZXR1cm4gLUVOT0RFVjsKPj4gKwo+PiArwqDCoMKgIGlmIChobnMzX3BtdS0+b25f Y3B1ID09IC0xKSB7Cj4+ICvCoMKgwqDCoMKgwqDCoCBobnMzX3BtdS0+b25fY3B1ID0gY3B1Owo+ PiArwqDCoMKgwqDCoMKgwqAgaXJxX3NldF9hZmZpbml0eShobnMzX3BtdS0+aXJxLCBjcHVtYXNr X29mKGNwdSkpOwo+PiArwqDCoMKgIH0KPj4gKwo+PiArwqDCoMKgIHJldHVybiAwOwo+PiArfQo+ PiArCj4+ICtzdGF0aWMgaW50IGhuczNfcG11X29mZmxpbmVfY3B1KHVuc2lnbmVkIGludCBjcHUs IHN0cnVjdCBobGlzdF9ub2RlICpub2RlKQo+PiArewo+PiArwqDCoMKgIHN0cnVjdCBobnMzX3Bt dSAqaG5zM19wbXU7Cj4+ICvCoMKgwqAgdW5zaWduZWQgaW50IHRhcmdldDsKPj4gKwo+PiArwqDC oMKgIGhuczNfcG11ID0gaGxpc3RfZW50cnlfc2FmZShub2RlLCBzdHJ1Y3QgaG5zM19wbXUsIG5v ZGUpOwo+PiArwqDCoMKgIGlmICghaG5zM19wbXUpCj4+ICvCoMKgwqDCoMKgwqDCoCByZXR1cm4g LUVOT0RFVjsKPj4gKwo+PiArwqDCoMKgIC8qIE5vdGhpbmcgdG8gZG8gaWYgdGhpcyBDUFUgZG9l c24ndCBvd24gdGhlIFBNVSAqLwo+PiArwqDCoMKgIGlmIChobnMzX3BtdS0+b25fY3B1ICE9IGNw dSkKPj4gK8KgwqDCoMKgwqDCoMKgIHJldHVybiAwOwo+PiArCj4+ICvCoMKgwqAgLyogQ2hvb3Nl IGEgbmV3IENQVSBmcm9tIGFsbCBvbmxpbmUgY3B1cyAqLwo+PiArwqDCoMKgIHRhcmdldCA9IGNw dW1hc2tfYW55X2J1dChjcHVfb25saW5lX21hc2ssIGNwdSk7Cj4+ICvCoMKgwqAgaWYgKHRhcmdl dCA+PSBucl9jcHVfaWRzKQo+PiArwqDCoMKgwqDCoMKgwqAgcmV0dXJuIDA7Cj4+ICsKPj4gK8Kg wqDCoCBwZXJmX3BtdV9taWdyYXRlX2NvbnRleHQoJmhuczNfcG11LT5wbXUsIGNwdSwgdGFyZ2V0 KTsKPj4gK8KgwqDCoCBobnMzX3BtdS0+b25fY3B1ID0gdGFyZ2V0Owo+PiArwqDCoMKgIGlycV9z ZXRfYWZmaW5pdHkoaG5zM19wbXUtPmlycSwgY3B1bWFza19vZih0YXJnZXQpKTsKPj4gKwo+PiAr wqDCoMKgIHJldHVybiAwOwo+PiArfQo+PiArCj4+ICtzdGF0aWMgdm9pZCBobnMzX3BtdV9mcmVl X2lycSh2b2lkICpkYXRhKQo+PiArewo+PiArwqDCoMKgIHN0cnVjdCBwY2lfZGV2ICpwZGV2ID0g ZGF0YTsKPj4gKwo+PiArwqDCoMKgIHBjaV9mcmVlX2lycV92ZWN0b3JzKHBkZXYpOwo+PiArfQo+ PiArCj4+ICtzdGF0aWMgaW50IGhuczNfcG11X2lycV9yZWdpc3RlcihzdHJ1Y3QgcGNpX2RldiAq cGRldiwKPj4gK8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIHN0cnVjdCBobnMzX3Bt dSAqaG5zM19wbXUpCj4+ICt7Cj4+ICvCoMKgwqAgaW50IGlycSwgcmV0Owo+PiArCj4+ICvCoMKg wqAgcmV0ID0gcGNpX2FsbG9jX2lycV92ZWN0b3JzKHBkZXYsIDEsIDEsIFBDSV9JUlFfTVNJKTsK Pj4gK8KgwqDCoCBpZiAocmV0IDwgMCkgewo+PiArwqDCoMKgwqDCoMKgwqAgcGNpX2VycihwZGV2 LCAiZmFpbGVkIHRvIGVuYWJsZSBNU0kgdmVjdG9ycywgcmV0ID0gJWQuXG4iLCByZXQpOwo+PiAr wqDCoMKgwqDCoMKgwqAgcmV0dXJuIHJldDsKPj4gK8KgwqDCoCB9Cj4+ICsKPj4gK8KgwqDCoCBy ZXQgPSBkZXZtX2FkZF9hY3Rpb24oJnBkZXYtPmRldiwgaG5zM19wbXVfZnJlZV9pcnEsIHBkZXYp Owo+PiArwqDCoMKgIGlmIChyZXQpIHsKPj4gK8KgwqDCoMKgwqDCoMKgIHBjaV9lcnIocGRldiwg ImZhaWxlZCB0byBhZGQgZnJlZSBpcnEgYWN0aW9uLCByZXQgPSAlZC5cbiIsIHJldCk7Cj4+ICvC oMKgwqDCoMKgwqDCoCByZXR1cm4gcmV0Owo+PiArwqDCoMKgIH0KPj4gKwo+PiArwqDCoMKgIGly cSA9IHBjaV9pcnFfdmVjdG9yKHBkZXYsIDApOwo+PiArwqDCoMKgIHJldCA9IGRldm1fcmVxdWVz dF9pcnEoJnBkZXYtPmRldiwgaXJxLCBobnMzX3BtdV9pcnEsIDAsCj4+ICvCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgaG5zM19wbXUtPnBtdS5uYW1lLCBobnMzX3BtdSk7Cj4+ ICvCoMKgwqAgaWYgKHJldCkgewo+PiArwqDCoMKgwqDCoMKgwqAgcGNpX2VycihwZGV2LCAiZmFp bGVkIHRvIHJlZ2lzdGVyIGlycSwgcmV0ID0gJWQuXG4iLCByZXQpOwo+PiArwqDCoMKgwqDCoMKg wqAgcmV0dXJuIHJldDsKPj4gK8KgwqDCoCB9Cj4+ICsKPj4gK8KgwqDCoCBobnMzX3BtdS0+aXJx ID0gaXJxOwo+PiArCj4+ICvCoMKgwqAgcmV0dXJuIDA7Cj4+ICt9Cj4+ICsKPj4gK3N0YXRpYyBp bnQgaG5zM19wbXVfaW5pdF9wbXUoc3RydWN0IHBjaV9kZXYgKnBkZXYsIHN0cnVjdCBobnMzX3Bt dSAqaG5zM19wbXUpCj4+ICt7Cj4+ICvCoMKgwqAgaW50IHJldDsKPj4gKwo+PiArwqDCoMKgIHJl dCA9IGhuczNfcG11X2FsbG9jX3BtdShwZGV2LCBobnMzX3BtdSk7Cj4+ICvCoMKgwqAgaWYgKHJl dCkKPj4gK8KgwqDCoMKgwqDCoMKgIHJldHVybiByZXQ7Cj4+ICsKPj4gK8KgwqDCoCByZXQgPSBo bnMzX3BtdV9pcnFfcmVnaXN0ZXIocGRldiwgaG5zM19wbXUpOwo+PiArwqDCoMKgIGlmIChyZXQp Cj4+ICvCoMKgwqDCoMKgwqDCoCByZXR1cm4gcmV0Owo+PiArCj4+ICvCoMKgwqAgcmV0ID0gY3B1 aHBfc3RhdGVfYWRkX2luc3RhbmNlKENQVUhQX0FQX1BFUkZfQVJNX0hOUzNfUE1VX09OTElORSwK Pj4gK8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgICZobnMzX3Bt dS0+bm9kZSk7Cj4+ICvCoMKgwqAgaWYgKHJldCkgewo+PiArwqDCoMKgwqDCoMKgwqAgcGNpX2Vy cihwZGV2LCAiZmFpbGVkIHRvIHJlZ2lzdGVyIGhvdHBsdWcsIHJldCA9ICVkLlxuIiwgcmV0KTsK Pj4gK8KgwqDCoMKgwqDCoMKgIHJldHVybiByZXQ7Cj4+ICvCoMKgwqAgfQo+PiArCj4+ICvCoMKg wqAgcmV0ID0gcGVyZl9wbXVfcmVnaXN0ZXIoJmhuczNfcG11LT5wbXUsIGhuczNfcG11LT5wbXUu bmFtZSwgLTEpOwo+PiArwqDCoMKgIGlmIChyZXQpIHsKPj4gK8KgwqDCoMKgwqDCoMKgIHBjaV9l cnIocGRldiwgImZhaWxlZCB0byByZWdpc3RlciBwZXJmIFBNVSwgcmV0ID0gJWQuXG4iLCByZXQp Owo+PiArwqDCoMKgwqDCoMKgwqAgY3B1aHBfc3RhdGVfcmVtb3ZlX2luc3RhbmNlKENQVUhQX0FQ X1BFUkZfQVJNX0hOUzNfUE1VX09OTElORSwKPj4gK8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqAgJmhuczNfcG11LT5ub2RlKTsKPj4gK8KgwqDCoCB9Cj4+ICsK Pj4gK8KgwqDCoCByZXR1cm4gcmV0Owo+PiArfQo+PiArCj4+ICtzdGF0aWMgdm9pZCBobnMzX3Bt dV91bmluaXRfcG11KHN0cnVjdCBwY2lfZGV2ICpwZGV2KQo+PiArewo+PiArwqDCoMKgIHN0cnVj dCBobnMzX3BtdSAqaG5zM19wbXUgPSBwY2lfZ2V0X2RydmRhdGEocGRldik7Cj4+ICsKPj4gK8Kg wqDCoCBwZXJmX3BtdV91bnJlZ2lzdGVyKCZobnMzX3BtdS0+cG11KTsKPj4gK8KgwqDCoCBjcHVo cF9zdGF0ZV9yZW1vdmVfaW5zdGFuY2UoQ1BVSFBfQVBfUEVSRl9BUk1fSE5TM19QTVVfT05MSU5F LAo+PiArwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgJmhuczNfcG11LT5u b2RlKTsKPj4gK30KPj4gKwo+PiArc3RhdGljIGludCBobnMzX3BtdV9pbml0X2RldihzdHJ1Y3Qg cGNpX2RldiAqcGRldikKPj4gK3sKPj4gK8KgwqDCoCBpbnQgcmV0Owo+PiArCj4+ICvCoMKgwqAg cmV0ID0gcGNpbV9lbmFibGVfZGV2aWNlKHBkZXYpOwo+PiArwqDCoMKgIGlmIChyZXQpIHsKPj4g K8KgwqDCoMKgwqDCoMKgIHBjaV9lcnIocGRldiwgImZhaWxlZCB0byBlbmFibGUgcGNpIGRldmlj ZSwgcmV0ID0gJWQuXG4iLCByZXQpOwo+PiArwqDCoMKgwqDCoMKgwqAgcmV0dXJuIHJldDsKPj4g K8KgwqDCoCB9Cj4+ICsKPj4gK8KgwqDCoCByZXQgPSBwY2ltX2lvbWFwX3JlZ2lvbnMocGRldiwg QklUKEJBUl8yKSwgImhuczNfcG11Iik7Cj4+ICvCoMKgwqAgaWYgKHJldCA8IDApIHsKPj4gK8Kg wqDCoMKgwqDCoMKgIHBjaV9lcnIocGRldiwgImZhaWxlZCB0byByZXF1ZXN0IHBjaSByZWdpb24s IHJldCA9ICVkLlxuIiwgcmV0KTsKPj4gK8KgwqDCoMKgwqDCoMKgIHJldHVybiByZXQ7Cj4+ICvC oMKgwqAgfQo+PiArCj4+ICvCoMKgwqAgcGNpX3NldF9tYXN0ZXIocGRldik7Cj4+ICsKPj4gK8Kg wqDCoCByZXR1cm4gMDsKPj4gK30KPj4gKwo+PiArc3RhdGljIGludCBobnMzX3BtdV9wcm9iZShz dHJ1Y3QgcGNpX2RldiAqcGRldiwgY29uc3Qgc3RydWN0IHBjaV9kZXZpY2VfaWQgKmlkKQo+PiAr ewo+PiArwqDCoMKgIHN0cnVjdCBobnMzX3BtdSAqaG5zM19wbXU7Cj4+ICvCoMKgwqAgaW50IHJl dDsKPj4gKwo+PiArwqDCoMKgIGhuczNfcG11ID0gZGV2bV9remFsbG9jKCZwZGV2LT5kZXYsIHNp emVvZigqaG5zM19wbXUpLCBHRlBfS0VSTkVMKTsKPj4gK8KgwqDCoCBpZiAoIWhuczNfcG11KQo+ PiArwqDCoMKgwqDCoMKgwqAgcmV0dXJuIC1FTk9NRU07Cj4+ICsKPj4gK8KgwqDCoCByZXQgPSBo bnMzX3BtdV9pbml0X2RldihwZGV2KTsKPj4gK8KgwqDCoCBpZiAocmV0KQo+PiArwqDCoMKgwqDC oMKgwqAgcmV0dXJuIHJldDsKPj4gKwo+PiArwqDCoMKgIHJldCA9IGhuczNfcG11X2luaXRfcG11 KHBkZXYsIGhuczNfcG11KTsKPj4gK8KgwqDCoCBpZiAocmV0KSB7Cj4+ICvCoMKgwqDCoMKgwqDC oCBwY2lfY2xlYXJfbWFzdGVyKHBkZXYpOwo+PiArwqDCoMKgwqDCoMKgwqAgcmV0dXJuIHJldDsK Pj4gK8KgwqDCoCB9Cj4+ICsKPj4gK8KgwqDCoCBwY2lfc2V0X2RydmRhdGEocGRldiwgaG5zM19w bXUpOwo+PiArCj4+ICvCoMKgwqAgcmV0dXJuIHJldDsKPj4gK30KPj4gKwo+PiArc3RhdGljIHZv aWQgaG5zM19wbXVfcmVtb3ZlKHN0cnVjdCBwY2lfZGV2ICpwZGV2KQo+PiArewo+PiArwqDCoMKg IGhuczNfcG11X3VuaW5pdF9wbXUocGRldik7Cj4+ICvCoMKgwqAgcGNpX2NsZWFyX21hc3Rlcihw ZGV2KTsKPj4gK8KgwqDCoCBwY2lfc2V0X2RydmRhdGEocGRldiwgTlVMTCk7Cj4+ICt9Cj4+ICsK Pj4gK3N0YXRpYyBjb25zdCBzdHJ1Y3QgcGNpX2RldmljZV9pZCBobnMzX3BtdV9pZHNbXSA9IHsK Pj4gK8KgwqDCoCB7IFBDSV9ERVZJQ0UoUENJX1ZFTkRPUl9JRF9IVUFXRUksIDB4YTIyYikgfSwK Pj4gK8KgwqDCoCB7IDAsIH0KPj4gK307Cj4+ICtNT0RVTEVfREVWSUNFX1RBQkxFKHBjaSwgaG5z M19wbXVfaWRzKTsKPj4gKwo+PiArc3RhdGljIHN0cnVjdCBwY2lfZHJpdmVyIGhuczNfcG11X2Ry aXZlciA9IHsKPj4gK8KgwqDCoCAubmFtZSA9ICJobnMzX3BtdSIsCj4+ICvCoMKgwqAgLmlkX3Rh YmxlID0gaG5zM19wbXVfaWRzLAo+PiArwqDCoMKgIC5wcm9iZSA9IGhuczNfcG11X3Byb2JlLAo+ PiArwqDCoMKgIC5yZW1vdmUgPSBobnMzX3BtdV9yZW1vdmUsCj4+ICt9Owo+PiArCj4+ICtzdGF0 aWMgaW50IF9faW5pdCBobnMzX3BtdV9tb2R1bGVfaW5pdCh2b2lkKQo+PiArewo+PiArwqDCoMKg IGludCByZXQ7Cj4+ICsKPj4gK8KgwqDCoCByZXQgPSBjcHVocF9zZXR1cF9zdGF0ZV9tdWx0aShD UFVIUF9BUF9QRVJGX0FSTV9ITlMzX1BNVV9PTkxJTkUsCj4+ICvCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgIkFQX1BFUkZfQVJNX0hOUzNfUE1VX09OTElORSIsCj4+ ICvCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgaG5zM19wbXVfb25s aW5lX2NwdSwKPj4gK8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCBo bnMzX3BtdV9vZmZsaW5lX2NwdSk7Cj4+ICvCoMKgwqAgaWYgKHJldCkgewo+PiArwqDCoMKgwqDC oMKgwqAgcHJfZXJyKCJmYWlsZWQgdG8gc2V0dXAgSE5TMyBQTVUgaG90cGx1ZywgcmV0ID0gJWQu XG4iLCByZXQpOwo+PiArwqDCoMKgwqDCoMKgwqAgcmV0dXJuIHJldDsKPj4gK8KgwqDCoCB9Cj4+ ICsKPj4gK8KgwqDCoCByZXQgPSBwY2lfcmVnaXN0ZXJfZHJpdmVyKCZobnMzX3BtdV9kcml2ZXIp Owo+PiArwqDCoMKgIGlmIChyZXQpIHsKPj4gK8KgwqDCoMKgwqDCoMKgIHByX2VycigiZmFpbGVk IHRvIHJlZ2lzdGVyIHBjaSBkcml2ZXIsIHJldCA9ICVkLlxuIiwgcmV0KTsKPj4gK8KgwqDCoMKg wqDCoMKgIGNwdWhwX3JlbW92ZV9tdWx0aV9zdGF0ZShDUFVIUF9BUF9QRVJGX0FSTV9ITlMzX1BN VV9PTkxJTkUpOwo+PiArwqDCoMKgIH0KPj4gKwo+PiArwqDCoMKgIHJldHVybiByZXQ7Cj4+ICt9 Cj4+ICttb2R1bGVfaW5pdChobnMzX3BtdV9tb2R1bGVfaW5pdCk7Cj4+ICsKPj4gK3N0YXRpYyB2 b2lkIF9fZXhpdCBobnMzX3BtdV9tb2R1bGVfZXhpdCh2b2lkKQo+PiArewo+PiArwqDCoMKgIHBj aV91bnJlZ2lzdGVyX2RyaXZlcigmaG5zM19wbXVfZHJpdmVyKTsKPj4gK8KgwqDCoCBjcHVocF9y ZW1vdmVfbXVsdGlfc3RhdGUoQ1BVSFBfQVBfUEVSRl9BUk1fSE5TM19QTVVfT05MSU5FKTsKPj4g K30KPj4gK21vZHVsZV9leGl0KGhuczNfcG11X21vZHVsZV9leGl0KTsKPj4gKwo+PiArTU9EVUxF X0RFU0NSSVBUSU9OKCJITlMzIFBNVSBkcml2ZXIiKTsKPj4gK01PRFVMRV9MSUNFTlNFKCJHUEwg djIiKTsKPj4gZGlmZiAtLWdpdCBhL2luY2x1ZGUvbGludXgvY3B1aG90cGx1Zy5oIGIvaW5jbHVk ZS9saW51eC9jcHVob3RwbHVnLmgKPj4gaW5kZXggNDExYTQyOGFjZTRkLi45YzJjYjA2MDA3NDAg MTAwNjQ0Cj4+IC0tLSBhL2luY2x1ZGUvbGludXgvY3B1aG90cGx1Zy5oCj4+ICsrKyBiL2luY2x1 ZGUvbGludXgvY3B1aG90cGx1Zy5oCj4+IEBAIC0yMjYsNiArMjI2LDcgQEAgZW51bSBjcHVocF9z dGF0ZSB7Cj4+IMKgwqDCoMKgwqAgQ1BVSFBfQVBfUEVSRl9BUk1fSElTSV9QQV9PTkxJTkUsCj4+ IMKgwqDCoMKgwqAgQ1BVSFBfQVBfUEVSRl9BUk1fSElTSV9TTExDX09OTElORSwKPj4gwqDCoMKg wqDCoCBDUFVIUF9BUF9QRVJGX0FSTV9ISVNJX1BDSUVfUE1VX09OTElORSwKPj4gK8KgwqDCoCBD UFVIUF9BUF9QRVJGX0FSTV9ITlMzX1BNVV9PTkxJTkUsCj4+IMKgwqDCoMKgwqAgQ1BVSFBfQVBf UEVSRl9BUk1fTDJYMF9PTkxJTkUsCj4+IMKgwqDCoMKgwqAgQ1BVSFBfQVBfUEVSRl9BUk1fUUNP TV9MMl9PTkxJTkUsCj4+IMKgwqDCoMKgwqAgQ1BVSFBfQVBfUEVSRl9BUk1fUUNPTV9MM19PTkxJ TkUsCj4gCj4gLgoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X18KbGludXgtYXJtLWtlcm5lbCBtYWlsaW5nIGxpc3QKbGludXgtYXJtLWtlcm5lbEBsaXN0cy5p bmZyYWRlYWQub3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8v bGludXgtYXJtLWtlcm5lbAo=