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From: BALATON Zoltan <balaton@eik.bme.hu>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>,
	qemu-devel@nongnu.org, Aurelien Jarno <aurelien@aurel32.net>
Subject: Re: [PATCH RESEND 3/6] hw/mips/gt64xxx: Fix typos in qemu_log_mask() formats
Date: Tue, 9 Mar 2021 16:39:31 +0100 (CET)	[thread overview]
Message-ID: <5fcd9a2a-70f0-e148-e8d4-75bd3b4f752b@eik.bme.hu> (raw)
In-Reply-To: <20210309142630.728014-4-f4bug@amsat.org>

[-- Attachment #1: Type: text/plain, Size: 4679 bytes --]



On Tue, 9 Mar 2021, Philippe Mathieu-Daudé wrote:

> Fix the following typos:
> - GT_PCI1_CFGDATA is not a timer register but a PCI one,
> - zero-padding flag is out of the format
>
> Fixes: 641ca2bfcd5 ("hw/mips/gt64xxx_pci: Use qemu_log_mask() instead of debug printf()")
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>

> ---
> hw/mips/gt64xxx_pci.c | 20 ++++++++++----------
> 1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
> index 99b1690af19..8ff31380d74 100644
> --- a/hw/mips/gt64xxx_pci.c
> +++ b/hw/mips/gt64xxx_pci.c
> @@ -463,7 +463,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
>         /* Read-only registers, do nothing */
>         qemu_log_mask(LOG_GUEST_ERROR,
>                       "gt64120: Read-only register write "
> -                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
> +                      "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
>                       saddr << 2, size, size << 1, val);
>         break;
>
> @@ -473,7 +473,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
>         /* Read-only registers, do nothing */
>         qemu_log_mask(LOG_GUEST_ERROR,
>                       "gt64120: Read-only register write "
> -                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
> +                      "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
>                       saddr << 2, size, size << 1, val);
>         break;
>
> @@ -515,7 +515,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
>         /* Not implemented */
>         qemu_log_mask(LOG_UNIMP,
>                       "gt64120: Unimplemented device register write "
> -                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
> +                      "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
>                       saddr << 2, size, size << 1, val);
>         break;
>
> @@ -528,7 +528,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
>         /* Read-only registers, do nothing */
>         qemu_log_mask(LOG_GUEST_ERROR,
>                       "gt64120: Read-only register write "
> -                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
> +                      "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
>                       saddr << 2, size, size << 1, val);
>         break;
>
> @@ -565,7 +565,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
>         /* Not implemented */
>         qemu_log_mask(LOG_UNIMP,
>                       "gt64120: Unimplemented DMA register write "
> -                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
> +                      "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
>                       saddr << 2, size, size << 1, val);
>         break;
>
> @@ -578,7 +578,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
>         /* Not implemented */
>         qemu_log_mask(LOG_UNIMP,
>                       "gt64120: Unimplemented timer register write "
> -                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
> +                      "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
>                       saddr << 2, size, size << 1, val);
>         break;
>
> @@ -621,8 +621,8 @@ static void gt64120_writel(void *opaque, hwaddr addr,
>     case GT_PCI1_CFGDATA:
>         /* not implemented */
>         qemu_log_mask(LOG_UNIMP,
> -                      "gt64120: Unimplemented timer register write "
> -                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
> +                      "gt64120: Unimplemented PCI register write "
> +                      "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
>                       saddr << 2, size, size << 1, val);
>         break;
>     case GT_PCI0_CFGADDR:
> @@ -682,7 +682,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
>     default:
>         qemu_log_mask(LOG_GUEST_ERROR,
>                       "gt64120: Illegal register write "
> -                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
> +                      "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
>                       saddr << 2, size, size << 1, val);
>         break;
>     }
> @@ -958,7 +958,7 @@ static uint64_t gt64120_readl(void *opaque,
>         val = s->regs[saddr];
>         qemu_log_mask(LOG_GUEST_ERROR,
>                       "gt64120: Illegal register read "
> -                      "reg:0x03%x size:%u value:0x%0*x\n",
> +                      "reg:0x%03x size:%u value:0x%0*x\n",
>                       saddr << 2, size, size << 1, val);
>         break;
>     }
>

  reply	other threads:[~2021-03-09 15:54 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-09 14:26 [PATCH RESEND 0/6] hw/mips/gt64120: Minor fixes Philippe Mathieu-Daudé
2021-03-09 14:26 ` [PATCH RESEND 1/6] hw/mips/gt64xxx: Initialize ISD I/O memory region in DeviceRealize() Philippe Mathieu-Daudé
2021-03-09 15:36   ` BALATON Zoltan
2021-03-09 14:26 ` [PATCH RESEND 2/6] hw/mips/gt64xxx: Simplify ISD MemoryRegion read/write handlers Philippe Mathieu-Daudé
2021-03-09 15:50   ` BALATON Zoltan
2021-03-09 14:26 ` [PATCH RESEND 3/6] hw/mips/gt64xxx: Fix typos in qemu_log_mask() formats Philippe Mathieu-Daudé
2021-03-09 15:39   ` BALATON Zoltan [this message]
2021-03-09 14:26 ` [PATCH RESEND 4/6] hw/mips/gt64xxx: Rename trace events related to interrupt registers Philippe Mathieu-Daudé
2021-03-09 15:41   ` BALATON Zoltan
2021-03-09 14:26 ` [PATCH RESEND 5/6] hw/mips/gt64xxx: Trace accesses to ISD registers Philippe Mathieu-Daudé
2021-03-09 15:42   ` BALATON Zoltan
2021-03-09 15:47   ` BALATON Zoltan
2021-03-09 14:26 ` [PATCH RESEND 6/6] hw/mips/gt64xxx: Let the GT64120 manage the lower 512MiB hole Philippe Mathieu-Daudé
2021-03-09 15:52   ` BALATON Zoltan
2021-03-09 17:14     ` Philippe Mathieu-Daudé
2021-03-11 23:24 ` [PATCH RESEND 0/6] hw/mips/gt64120: Minor fixes Philippe Mathieu-Daudé

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