From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751370AbdAMJak (ORCPT ); Fri, 13 Jan 2017 04:30:40 -0500 Received: from foss.arm.com ([217.140.101.70]:37496 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750923AbdAMJai (ORCPT ); Fri, 13 Jan 2017 04:30:38 -0500 Subject: Re: [PATCH v2 2/2] arm64: cacheinfo: add support to override cache levels via device tree To: Tan Xiaojun , linux-arm-kernel@lists.infradead.org References: <1484245772-31511-1-git-send-email-sudeep.holla@arm.com> <1484245772-31511-2-git-send-email-sudeep.holla@arm.com> <58789899.3080909@huawei.com> Cc: Sudeep Holla , Mark Rutland , devicetree@vger.kernel.org, Catalin Marinas , Will Deacon , linux-kernel@vger.kernel.org, Rob Herring From: Sudeep Holla Organization: ARM Message-ID: <609a80c7-9a85-2786-1e5a-a5c2340900b9@arm.com> Date: Fri, 13 Jan 2017 09:30:28 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 In-Reply-To: <58789899.3080909@huawei.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 13/01/17 09:06, Tan Xiaojun wrote: > On 2017/1/13 2:29, Sudeep Holla wrote: >> The cache hierarchy can be identified through Cache Level ID(CLIDR) >> architected system register. However in some cases it will provide >> only the number of cache levels that are integrated into the processor >> itself. In other words, it can't provide any information about the >> caches that are external and/or transparent. >> >> Some platforms require to export the information about all such external >> caches to the userspace applications via the sysfs interface. >> >> This patch adds support to override the cache levels using device tree >> to take such external non-architected caches into account. >> >> Cc: Catalin Marinas >> Cc: Will Deacon >> Cc: Mark Rutland >> Signed-off-by: Sudeep Holla > > Tested-by: Tan Xiaojun > Thanks for testing. -- Regards, Sudeep From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sudeep Holla Subject: Re: [PATCH v2 2/2] arm64: cacheinfo: add support to override cache levels via device tree Date: Fri, 13 Jan 2017 09:30:28 +0000 Message-ID: <609a80c7-9a85-2786-1e5a-a5c2340900b9@arm.com> References: <1484245772-31511-1-git-send-email-sudeep.holla@arm.com> <1484245772-31511-2-git-send-email-sudeep.holla@arm.com> <58789899.3080909@huawei.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <58789899.3080909-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Tan Xiaojun , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org Cc: Sudeep Holla , Mark Rutland , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Catalin Marinas , Will Deacon , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rob Herring List-Id: devicetree@vger.kernel.org On 13/01/17 09:06, Tan Xiaojun wrote: > On 2017/1/13 2:29, Sudeep Holla wrote: >> The cache hierarchy can be identified through Cache Level ID(CLIDR) >> architected system register. However in some cases it will provide >> only the number of cache levels that are integrated into the processor >> itself. In other words, it can't provide any information about the >> caches that are external and/or transparent. >> >> Some platforms require to export the information about all such external >> caches to the userspace applications via the sysfs interface. >> >> This patch adds support to override the cache levels using device tree >> to take such external non-architected caches into account. >> >> Cc: Catalin Marinas >> Cc: Will Deacon >> Cc: Mark Rutland >> Signed-off-by: Sudeep Holla > > Tested-by: Tan Xiaojun > Thanks for testing. -- Regards, Sudeep -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: sudeep.holla@arm.com (Sudeep Holla) Date: Fri, 13 Jan 2017 09:30:28 +0000 Subject: [PATCH v2 2/2] arm64: cacheinfo: add support to override cache levels via device tree In-Reply-To: <58789899.3080909@huawei.com> References: <1484245772-31511-1-git-send-email-sudeep.holla@arm.com> <1484245772-31511-2-git-send-email-sudeep.holla@arm.com> <58789899.3080909@huawei.com> Message-ID: <609a80c7-9a85-2786-1e5a-a5c2340900b9@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 13/01/17 09:06, Tan Xiaojun wrote: > On 2017/1/13 2:29, Sudeep Holla wrote: >> The cache hierarchy can be identified through Cache Level ID(CLIDR) >> architected system register. However in some cases it will provide >> only the number of cache levels that are integrated into the processor >> itself. In other words, it can't provide any information about the >> caches that are external and/or transparent. >> >> Some platforms require to export the information about all such external >> caches to the userspace applications via the sysfs interface. >> >> This patch adds support to override the cache levels using device tree >> to take such external non-architected caches into account. >> >> Cc: Catalin Marinas >> Cc: Will Deacon >> Cc: Mark Rutland >> Signed-off-by: Sudeep Holla > > Tested-by: Tan Xiaojun > Thanks for testing. -- Regards, Sudeep