From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751227AbcHAIWj (ORCPT ); Mon, 1 Aug 2016 04:22:39 -0400 Received: from mail-ve1eur01on0100.outbound.protection.outlook.com ([104.47.1.100]:7929 "EHLO EUR01-VE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750780AbcHAIWe (ORCPT ); Mon, 1 Aug 2016 04:22:34 -0400 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=peda@axentia.se; Subject: Re: [RFC PATCH 1/1] i2c: i2c-mux-pca954x: Add interrupt controller support. To: Phil Reid , , , References: <1469588756-70579-1-git-send-email-preid@electromag.com.au> <1469588756-70579-2-git-send-email-preid@electromag.com.au> <4ce345bd-c618-eff8-a68e-632dd99e8239@electromag.com.au> <8efb7100-9a19-dd38-f10c-891905fc8e23@electromag.com.au> From: Peter Rosin Organization: Axentia Technologies AB Message-ID: <61f5c328-9bbe-82c1-a969-60d1dae7db22@axentia.se> Date: Mon, 1 Aug 2016 10:22:11 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 In-Reply-To: <8efb7100-9a19-dd38-f10c-891905fc8e23@electromag.com.au> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [217.210.101.82] X-ClientProxiedBy: HE1PR08CA0037.eurprd08.prod.outlook.com (10.161.112.47) To AM4PR02MB1298.eurprd02.prod.outlook.com (10.165.241.148) X-MS-Office365-Filtering-Correlation-Id: 1a364d7b-e737-47c0-fe07-08d3b9e4f1e0 X-Microsoft-Exchange-Diagnostics: 1;AM4PR02MB1298;2:ZGtyVXoWOnP9q1ZWwOBbNa+sZmo8jV/EMCWlT7dlYKcPetmJehAkke2d3T/KOKwZ4T4TWVh+SNv1Q1be95pvP7FKwrjnbznYse5N1awL8G0HOxGjIWlgX/wwANNhjtqG+57lygzK05ZZQK18q4OZ4XTyLI2LlZ0vvbLE2cnIE3Mz507aKLfg6yLfSPf7Vn2e;3:t18WghMs/L5ls6gILcM1OCtbOKXAIigp0zPFa++tcxsk0gt1hGingTwVm5Lf6rONgm3gOecoMb1NBrekLBmXJ24YxMpM+xmMtBFnmFxQoxWd0dqXS1KFb2pXLDyFzFqr X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:AM4PR02MB1298; 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Right? >> >> I think the default should be that the driver assumes sane HW, i.e. the irq inputs >> are not asserted unless some driver is able to clear them. You can then add an >> option to keep irqs disabled when the mask "is wrong". As a bonus, I think this >> "is wrong" test should be configurable so that you specify a bitmask of irqs that >> all has to be unmasked for the irq to be enabled (and use that instead of the 0x3 >> in the pca954x_irq_mask/pca954x_irq_unmask functions). That makes the workaround >> more flexible. > > Correct, It works for my use case at the moment. There would need to be a way to define a mask. > Via device tree for example. Yes, some optional property in DT was my vision also. > I think sane devices that have irq masking don't really need the pca954x to be a irq source. > They could be configured with a shared IRQ as the pCA954x just ANDs then incoming lines together. Right. And I suppose we don't know if this is already happening... AFAIU, that approach would still work even if pca954x is made an interrupt source. Or? I mean, as you say, the pca954x functions as an electrical AND, and if interrupt clients register with whatever the parent interrupt controller is, they would be not be affected if there is also an interrupt controller for pca954x? Yes, such imaginary uses could have just wired all the irq lines together, but we don't know if they actually did that or if they possibly went via the irq routing in the pca954x for whatever reason... > So does my use case and workaround justify the complexity added to the driver? > > Thou there is possibly a performance benefit from reading the pca954x to dispatch the appropriate > irq, which would save alot of i2c transactions to probe each possible irq source device and assocaited > i2c mux switching. > > WDYR? It was the last bit that I also realized, and it would be nice to not have to dig through all irq devices on the child side of the mux (and other clients sharing the irq line with the pca954x for that matter). In theory there could be quite a few... So, yes, I think it might be worthwhile to make it an interrupt controller. And then the tweak with your mask is no longer the big part of it... BTW, you also need to change bindings docs in Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt I also noticed that you are using irq_domain_add_legacy which is marked as, *tada* legacy, and that most drivers should use a linear domain. Sounds like a linear domain fits the use case here, no? And another note, the workaround for your limited hw is rather non-generic. I mean, if the irq line from the pca954x to the parent interrupt controller is shared with something else, then there would still be a flood even with the workaround. Or am I misunderstanding that? Cheers, Peter From mboxrd@z Thu Jan 1 00:00:00 1970 From: Peter Rosin Subject: Re: [RFC PATCH 1/1] i2c: i2c-mux-pca954x: Add interrupt controller support. Date: Mon, 1 Aug 2016 10:22:11 +0200 Message-ID: <61f5c328-9bbe-82c1-a969-60d1dae7db22@axentia.se> References: <1469588756-70579-1-git-send-email-preid@electromag.com.au> <1469588756-70579-2-git-send-email-preid@electromag.com.au> <4ce345bd-c618-eff8-a68e-632dd99e8239@electromag.com.au> <8efb7100-9a19-dd38-f10c-891905fc8e23@electromag.com.au> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ve1eur01on0100.outbound.protection.outlook.com ([104.47.1.100]:7929 "EHLO EUR01-VE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750780AbcHAIWe (ORCPT ); Mon, 1 Aug 2016 04:22:34 -0400 In-Reply-To: <8efb7100-9a19-dd38-f10c-891905fc8e23@electromag.com.au> Sender: linux-i2c-owner@vger.kernel.org List-Id: linux-i2c@vger.kernel.org To: Phil Reid , wsa@the-dreams.de, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org On 2016-08-01 08:25, Phil Reid wrote: > On 29/07/2016 13:48, Peter Rosin wrote: >> Ok, I think I get the problem, but I too am at a loss and see no elegant solution. >> One sad thing about your workaround is that it is not working at all unless there >> is an irq user on all mux child segments that unmasks the corresponding irq. Right? >> >> I think the default should be that the driver assumes sane HW, i.e. the irq inputs >> are not asserted unless some driver is able to clear them. You can then add an >> option to keep irqs disabled when the mask "is wrong". As a bonus, I think this >> "is wrong" test should be configurable so that you specify a bitmask of irqs that >> all has to be unmasked for the irq to be enabled (and use that instead of the 0x3 >> in the pca954x_irq_mask/pca954x_irq_unmask functions). That makes the workaround >> more flexible. > > Correct, It works for my use case at the moment. There would need to be a way to define a mask. > Via device tree for example. Yes, some optional property in DT was my vision also. > I think sane devices that have irq masking don't really need the pca954x to be a irq source. > They could be configured with a shared IRQ as the pCA954x just ANDs then incoming lines together. Right. And I suppose we don't know if this is already happening... AFAIU, that approach would still work even if pca954x is made an interrupt source. Or? I mean, as you say, the pca954x functions as an electrical AND, and if interrupt clients register with whatever the parent interrupt controller is, they would be not be affected if there is also an interrupt controller for pca954x? Yes, such imaginary uses could have just wired all the irq lines together, but we don't know if they actually did that or if they possibly went via the irq routing in the pca954x for whatever reason... > So does my use case and workaround justify the complexity added to the driver? > > Thou there is possibly a performance benefit from reading the pca954x to dispatch the appropriate > irq, which would save alot of i2c transactions to probe each possible irq source device and assocaited > i2c mux switching. > > WDYR? It was the last bit that I also realized, and it would be nice to not have to dig through all irq devices on the child side of the mux (and other clients sharing the irq line with the pca954x for that matter). In theory there could be quite a few... So, yes, I think it might be worthwhile to make it an interrupt controller. And then the tweak with your mask is no longer the big part of it... BTW, you also need to change bindings docs in Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt I also noticed that you are using irq_domain_add_legacy which is marked as, *tada* legacy, and that most drivers should use a linear domain. Sounds like a linear domain fits the use case here, no? And another note, the workaround for your limited hw is rather non-generic. I mean, if the irq line from the pca954x to the parent interrupt controller is shared with something else, then there would still be a flood even with the workaround. Or am I misunderstanding that? Cheers, Peter