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[88.21.202.17]) by smtp.gmail.com with ESMTPSA id q5sm13828341wra.36.2020.05.17.10.54.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 17 May 2020 10:54:06 -0700 (PDT) Subject: Re: [PATCH] ati-vga: Do not allow unaligned access via index register To: BALATON Zoltan References: <20200516132352.39E9374594E@zero.eik.bme.hu> <20200516144706.zz54mgs7k7anq3cj@mozz.bu.edu> <16020f02-5fe3-a7d9-ca30-759a2ba69307@amsat.org> <2aa3e473-4de3-253b-37b6-f61b13969329@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <620e0537-6a38-21b8-4ec1-9c12eb010399@amsat.org> Date: Sun, 17 May 2020 19:54:06 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexander Bulekov , qemu-devel@nongnu.org, Gerd Hoffmann Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/17/20 4:30 PM, BALATON Zoltan wrote: > On Sun, 17 May 2020, Philippe Mathieu-Daudé wrote: >> On 5/17/20 12:40 PM, Philippe Mathieu-Daudé wrote: >>> On 5/16/20 5:33 PM, BALATON Zoltan wrote: >>>> On Sat, 16 May 2020, Alexander Bulekov wrote: >>>>> On 200516 1513, BALATON Zoltan wrote: >>> Finally, there is a tag documented for bug fixes: >>> https://wiki.qemu.org/Contribute/SubmitAPatch#Write_a_meaningful_commit_message >>> >>> If your patch addresses a bug in a public bug tracker, please add a >>> line with "Buglink: " there, too. >>> >>> Buglink: https://bugs.launchpad.net/qemu/+bug/1878134 > > Does this reply add that tag already or do I need to submit a v2 with it > (or the maintainer could add it when merging)? If he doesn't have time he can reply to your patch :) > >>> Now, looking at your device implementation, it seems >>> >>> 1/ The device isn't supposed to have 64-bit accesses >>> >>> So this might be a more generic fix to Alexander issue: >>> >>> -- >8 -- >>> @@ -879,6 +879,7 @@ static void ati_mm_write(void *opaque, hwaddr addr, >>>   static const MemoryRegionOps ati_mm_ops = { >>>       .read = ati_mm_read, >>>       .write = ati_mm_write, >>> +    .valid.max_access_size = 4, >>>       .endianness = DEVICE_LITTLE_ENDIAN, >>>   }; >>> --- > > I've tried that first but it does not work. The reason is that > ati_mm_read is recursively called for indexed access via MM_DATA which > causes the problem that happens when MM_INDEX is set to a non-aligned > value. No 64 bit access, just 32 bit with offset of 2 bytes as can be > seen from the stach trace I've attached to the bug. Fortunately indexed > access is documented to only support aligned access by not allowing > setting low bits of MM_INDEX so unless we find a client needing it my > patch should do it. OK, so this is another device affected by the memory.c lacking of unaligned access (Gerd saw another one with USB). > >>> 2/ All the registers are 32-bit aligned >>> >>> So you can simplify the implementation by letting >>> access_with_adjusted_size() handle the 8/16-bit accesses by using: >>> >>> @@ -879,6 +879,8 @@ static void ati_mm_write(void *opaque, hwaddr addr, >>>   static const MemoryRegionOps ati_mm_ops = { >>>       .read = ati_mm_read, >>>       .write = ati_mm_write, >>> +    .min.min_access_size = 4, >> >> I meant '.impl.min_access_size'. > > I think this would not work either because not all registers are the > same, some only can be read all 32 bits, some also 16 or 8 bits and > clients do access these with less than 32 bits and accessing parts of > the reg may trigger actions so the current way is probably better and > necessary to correctly support different valid and invalid unaligned > accessses. .valid.xxx_access_size is what the guest are allowed to use, .impl.xxx_access_size is what the developer had in mind when writing the model. .impl.min_access_size = 4 doesn't forbid 8/16-bit guest accesses. Moreover, it overloads you the burden of handling short accesses. Anyway this was just a suggested simplification. > > Regards, > BALATON Zoltan