From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from kirsty.vergenet.net ([202.4.237.240]:34748 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726680AbeIMOT0 (ORCPT ); Thu, 13 Sep 2018 10:19:26 -0400 From: Simon Horman To: linux-renesas-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Magnus Damm , Dien Pham , Takeshi Kihara , Yoshihiro Kaneko , Simon Horman Subject: [PATCH 17/58] arm64: dts: renesas: r8a77965: Add OPPs table for cpu devices Date: Thu, 13 Sep 2018 11:09:12 +0200 Message-Id: <62531104428b39e2794a015af17154415fc33c4f.1536828567.git.horms+renesas@verge.net.au> In-Reply-To: References: Sender: linux-renesas-soc-owner@vger.kernel.org List-ID: From: Dien Pham This patch adds OPPs table for CA57{0,1} cpu devices Signed-off-by: Dien Pham Signed-off-by: Takeshi Kihara Signed-off-by: Yoshihiro Kaneko Tested-by: Simon Horman [simon: do not give nodes unit names as they have no bus addresses] Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 44 +++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index e7128fb65e33..5ce978502ee9 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -60,6 +60,46 @@ clock-frequency = <0>; }; + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <900000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <900000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <960000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -71,6 +111,8 @@ power-domains = <&sysc R8A77965_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A77965_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; }; a57_1: cpu@1 { @@ -80,6 +122,8 @@ power-domains = <&sysc R8A77965_PD_CA57_CPU1>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A77965_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; }; L2_CA57: cache-controller-0 { -- 2.11.0 From mboxrd@z Thu Jan 1 00:00:00 1970 From: horms+renesas@verge.net.au (Simon Horman) Date: Thu, 13 Sep 2018 11:09:12 +0200 Subject: [PATCH 17/58] arm64: dts: renesas: r8a77965: Add OPPs table for cpu devices In-Reply-To: References: Message-ID: <62531104428b39e2794a015af17154415fc33c4f.1536828567.git.horms+renesas@verge.net.au> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org From: Dien Pham This patch adds OPPs table for CA57{0,1} cpu devices Signed-off-by: Dien Pham Signed-off-by: Takeshi Kihara Signed-off-by: Yoshihiro Kaneko Tested-by: Simon Horman [simon: do not give nodes unit names as they have no bus addresses] Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 44 +++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index e7128fb65e33..5ce978502ee9 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -60,6 +60,46 @@ clock-frequency = <0>; }; + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <900000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <900000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <960000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -71,6 +111,8 @@ power-domains = <&sysc R8A77965_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A77965_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; }; a57_1: cpu at 1 { @@ -80,6 +122,8 @@ power-domains = <&sysc R8A77965_PD_CA57_CPU1>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A77965_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; }; L2_CA57: cache-controller-0 { -- 2.11.0