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[80.182.176.248]) by smtp.gmail.com with ESMTPSA id p13-20020a50d88d000000b0041cd1a083f7sm328292edj.1.2022.04.12.15.10.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Apr 2022 15:10:49 -0700 (PDT) Message-ID: <6255f8e9.1c69fb81.2cc35.1d5b@mx.google.com> X-Google-Original-Message-ID: Date: Tue, 12 Apr 2022 21:43:46 +0200 From: Ansuel Smith To: Bjorn Andersson Cc: Andy Gross , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan McDowell Subject: Re: [PATCH v3 01/18] ARM: dts: qcom: add multiple missing pin definition for ipq8064 References: <20220309190152.7998-1-ansuelsmth@gmail.com> <20220309190152.7998-2-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Tue, Apr 12, 2022 at 02:55:04PM -0500, Bjorn Andersson wrote: > On Wed 09 Mar 13:01 CST 2022, Ansuel Smith wrote: > > > Add missing definition for mdio0 pins used for gpio-bitbang driver,i2c4 > > pins and rgmii2 pins for ipq8064. > > > > I'm probably not looking hard enough, but I don't see where these are > used. Could they be introduced as they are being wired into their client > devices? > > Thanks, > Bjorn > mdio0 pins are used for by the switch connected to the SoC. i2c4 are used by rpm but in theory should never be used. rgmii2 i think were added for as some request for some devices that use them but not present upstream. Is it that bad to declare pin even if they are not used? They are used by any device downstream. > > Signed-off-by: Ansuel Smith > > Tested-by: Jonathan McDowell > > --- > > arch/arm/boot/dts/qcom-ipq8064.dtsi | 34 +++++++++++++++++++++++++++++ > > 1 file changed, 34 insertions(+) > > > > diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi > > index 11481313bdb6..cc6ca9013ab1 100644 > > --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi > > +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi > > @@ -382,6 +382,15 @@ mux { > > }; > > }; > > > > + i2c4_pins: i2c4_pinmux { > > + mux { > > + pins = "gpio12", "gpio13"; > > + function = "gsbi4"; > > + drive-strength = <12>; > > + bias-disable; > > + }; > > + }; > > + > > spi_pins: spi_pins { > > mux { > > pins = "gpio18", "gpio19", "gpio21"; > > @@ -424,6 +433,8 @@ mux { > > > > pullups { > > pins = "gpio39"; > > + function = "nand"; > > + drive-strength = <10>; > > bias-pull-up; > > }; > > > > @@ -431,9 +442,32 @@ hold { > > pins = "gpio40", "gpio41", "gpio42", > > "gpio43", "gpio44", "gpio45", > > "gpio46", "gpio47"; > > + function = "nand"; > > + drive-strength = <10>; > > bias-bus-hold; > > }; > > }; > > + > > + mdio0_pins: mdio0_pins { > > + mux { > > + pins = "gpio0", "gpio1"; > > + function = "mdio"; > > + drive-strength = <8>; > > + bias-disable; > > + }; > > + }; > > + > > + rgmii2_pins: rgmii2_pins { > > + mux { > > + pins = "gpio27", "gpio28", "gpio29", > > + "gpio30", "gpio31", "gpio32", > > + "gpio51", "gpio52", "gpio59", > > + "gpio60", "gpio61", "gpio62"; > > + function = "rgmii2"; > > + drive-strength = <8>; > > + bias-disable; > > + }; > > + }; > > }; > > > > intc: interrupt-controller@2000000 { > > -- > > 2.34.1 > > -- Ansuel