From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Tian, Kevin" Subject: RE: [PATCH 23/31] nVMX: Correct handling of interrupt injection Date: Wed, 25 May 2011 16:45:15 +0800 Message-ID: <625BA99ED14B2D499DC4E29D8138F1505C9BFA3A7F@shsmsx502.ccr.corp.intel.com> References: <1305575004-nyh@il.ibm.com> <201105161955.p4GJtgKc001996@rice.haifa.ibm.com> <625BA99ED14B2D499DC4E29D8138F1505C9BFA3A70@shsmsx502.ccr.corp.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Cc: "gleb@redhat.com" , "avi@redhat.com" To: "Tian, Kevin" , Nadav Har'El , "kvm@vger.kernel.org" Return-path: Received: from mga14.intel.com ([143.182.124.37]:22228 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932931Ab1EYIpe convert rfc822-to-8bit (ORCPT ); Wed, 25 May 2011 04:45:34 -0400 In-Reply-To: <625BA99ED14B2D499DC4E29D8138F1505C9BFA3A70@shsmsx502.ccr.corp.intel.com> Content-Language: en-US Sender: kvm-owner@vger.kernel.org List-ID: > From: Tian, Kevin > Sent: Wednesday, May 25, 2011 4:40 PM > > If L1 turns on VM_EXIT_ACK_INTR_ON_EXIT (again, no hypervisor that I know > > does), things look very different from the description above: L1 expects > > Type-1 bare metal hypervisor may enable this bit, such as Xen. This bit is > really prepared for L2 hypervisor since normally L2 hypervisor is tricky to > touch generic interrupt logic, and thus better to not ack it until interrupt > is enabled and then hardware will gear to the kernel interrupt handler > automatically. > > > to see an exit from L2 with the interrupt vector already filled in the exit > > information, and does not expect to be interrupted again with this interrupt. > > The current code does not (yet) support this case, so we do not allow the > > VM_EXIT_ACK_INTR_ON_EXIT exit-control to be turned on by L1. > > Then just fill the interrupt vector field with the highest unmasked bit > from pending vIRR. > And also ack virtual irqchip accordingly... Thanks Kevin