Re: [igt-dev] [PATCH i-g-t v9 1/3] include: bump drm uAPI headers

[Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>]

On 09/03/2018 14:50, Lionel Landwerlin wrote:
> Taken from drm-tip :
> 
> commit 1e6aa7e55c28ecd842b8b4599e4273c2429ee061
> Author: Jani Nikula <jani.nikula@intel.com>
> Date:   Tue Mar 6 12:41:55 2018 +0200
> 
>      drm/i915/icl: do not save DDI A/E sharing bit for ICL
> 
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> ---
>   include/drm-uapi/amdgpu_drm.h |   4 +
>   include/drm-uapi/drm_fourcc.h |  38 +++++----
>   include/drm-uapi/drm_mode.h   |  34 ++++++--
>   include/drm-uapi/exynos_drm.h | 192 +-----------------------------------------
>   include/drm-uapi/i915_drm.h   | 152 ++++++++++++++++++++++++++++++++-
>   include/drm-uapi/vc4_drm.h    |  76 +++++++++++++++++
>   lib/igt_perf.h                |   7 --
>   7 files changed, 277 insertions(+), 226 deletions(-)
> 
> diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h
> index 4d21191a..1816bd82 100644
> --- a/include/drm-uapi/amdgpu_drm.h
> +++ b/include/drm-uapi/amdgpu_drm.h
> @@ -664,6 +664,10 @@ struct drm_amdgpu_cs_chunk_data {
>   	#define AMDGPU_INFO_SENSOR_VDDNB		0x6
>   	/* Subquery id: Query graphics voltage */
>   	#define AMDGPU_INFO_SENSOR_VDDGFX		0x7
> +	/* Subquery id: Query GPU stable pstate shader clock */
> +	#define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK		0x8
> +	/* Subquery id: Query GPU stable pstate memory clock */
> +	#define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK		0x9
>   /* Number of VRAM page faults on CPU access. */
>   #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS	0x1E
>   #define AMDGPU_INFO_VRAM_LOST_COUNTER		0x1F
> diff --git a/include/drm-uapi/drm_fourcc.h b/include/drm-uapi/drm_fourcc.h
> index 3ad838d3..e04613d3 100644
> --- a/include/drm-uapi/drm_fourcc.h
> +++ b/include/drm-uapi/drm_fourcc.h
> @@ -178,7 +178,7 @@ extern "C" {
>   #define DRM_FORMAT_MOD_VENDOR_NONE    0
>   #define DRM_FORMAT_MOD_VENDOR_INTEL   0x01
>   #define DRM_FORMAT_MOD_VENDOR_AMD     0x02
> -#define DRM_FORMAT_MOD_VENDOR_NV      0x03
> +#define DRM_FORMAT_MOD_VENDOR_NVIDIA  0x03
>   #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
>   #define DRM_FORMAT_MOD_VENDOR_QCOM    0x05
>   #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
> @@ -188,7 +188,7 @@ extern "C" {
>   #define DRM_FORMAT_RESERVED	      ((1ULL << 56) - 1)
>   
>   #define fourcc_mod_code(vendor, val) \
> -	((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffULL))
> +	((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
>   
>   /*
>    * Format Modifier tokens:
> @@ -338,29 +338,17 @@ extern "C" {
>    */
>   #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
>   
> -/* NVIDIA Tegra frame buffer modifiers */
> -
> -/*
> - * Some modifiers take parameters, for example the number of vertical GOBs in
> - * a block. Reserve the lower 32 bits for parameters
> - */
> -#define __fourcc_mod_tegra_mode_shift 32
> -#define fourcc_mod_tegra_code(val, params) \
> -	fourcc_mod_code(NV, ((((__u64)val) << __fourcc_mod_tegra_mode_shift) | params))
> -#define fourcc_mod_tegra_mod(m) \
> -	(m & ~((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
> -#define fourcc_mod_tegra_param(m) \
> -	(m & ((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
> +/* NVIDIA frame buffer modifiers */
>   
>   /*
>    * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
>    *
>    * Pixels are arranged in simple tiles of 16 x 16 bytes.
>    */
> -#define NV_FORMAT_MOD_TEGRA_TILED fourcc_mod_tegra_code(1, 0)
> +#define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
>   
>   /*
> - * Tegra 16Bx2 Block Linear layout, used by TK1/TX1
> + * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later
>    *
>    * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
>    * vertically by a power of 2 (1 to 32 GOBs) to form a block.
> @@ -380,7 +368,21 @@ extern "C" {
>    * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
>    * in full detail.
>    */
> -#define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v)
> +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
> +	fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf))
> +
> +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
> +	fourcc_mod_code(NVIDIA, 0x10)
> +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
> +	fourcc_mod_code(NVIDIA, 0x11)
> +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
> +	fourcc_mod_code(NVIDIA, 0x12)
> +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
> +	fourcc_mod_code(NVIDIA, 0x13)
> +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
> +	fourcc_mod_code(NVIDIA, 0x14)
> +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
> +	fourcc_mod_code(NVIDIA, 0x15)
>   
>   /*
>    * Broadcom VC4 "T" format
> diff --git a/include/drm-uapi/drm_mode.h b/include/drm-uapi/drm_mode.h
> index 5597a871..2c575794 100644
> --- a/include/drm-uapi/drm_mode.h
> +++ b/include/drm-uapi/drm_mode.h
> @@ -38,14 +38,18 @@ extern "C" {
>   #define DRM_DISPLAY_MODE_LEN	32
>   #define DRM_PROP_NAME_LEN	32
>   
> -#define DRM_MODE_TYPE_BUILTIN	(1<<0)
> -#define DRM_MODE_TYPE_CLOCK_C	((1<<1) | DRM_MODE_TYPE_BUILTIN)
> -#define DRM_MODE_TYPE_CRTC_C	((1<<2) | DRM_MODE_TYPE_BUILTIN)
> +#define DRM_MODE_TYPE_BUILTIN	(1<<0) /* deprecated */
> +#define DRM_MODE_TYPE_CLOCK_C	((1<<1) | DRM_MODE_TYPE_BUILTIN) /* deprecated */
> +#define DRM_MODE_TYPE_CRTC_C	((1<<2) | DRM_MODE_TYPE_BUILTIN) /* deprecated */
>   #define DRM_MODE_TYPE_PREFERRED	(1<<3)
> -#define DRM_MODE_TYPE_DEFAULT	(1<<4)
> +#define DRM_MODE_TYPE_DEFAULT	(1<<4) /* deprecated */
>   #define DRM_MODE_TYPE_USERDEF	(1<<5)
>   #define DRM_MODE_TYPE_DRIVER	(1<<6)
>   
> +#define DRM_MODE_TYPE_ALL	(DRM_MODE_TYPE_PREFERRED |	\
> +				 DRM_MODE_TYPE_USERDEF |	\
> +				 DRM_MODE_TYPE_DRIVER)
> +
>   /* Video mode flags */
>   /* bit compatible with the xrandr RR_ definitions (bits 0-13)
>    *
> @@ -66,8 +70,8 @@ extern "C" {
>   #define DRM_MODE_FLAG_PCSYNC			(1<<7)
>   #define DRM_MODE_FLAG_NCSYNC			(1<<8)
>   #define DRM_MODE_FLAG_HSKEW			(1<<9) /* hskew provided */
> -#define DRM_MODE_FLAG_BCAST			(1<<10)
> -#define DRM_MODE_FLAG_PIXMUX			(1<<11)
> +#define DRM_MODE_FLAG_BCAST			(1<<10) /* deprecated */
> +#define DRM_MODE_FLAG_PIXMUX			(1<<11) /* deprecated */
>   #define DRM_MODE_FLAG_DBLCLK			(1<<12)
>   #define DRM_MODE_FLAG_CLKDIV2			(1<<13)
>    /*
> @@ -99,6 +103,20 @@ extern "C" {
>   #define  DRM_MODE_FLAG_PIC_AR_16_9 \
>   			(DRM_MODE_PICTURE_ASPECT_16_9<<19)
>   
> +#define  DRM_MODE_FLAG_ALL	(DRM_MODE_FLAG_PHSYNC |		\
> +				 DRM_MODE_FLAG_NHSYNC |		\
> +				 DRM_MODE_FLAG_PVSYNC |		\
> +				 DRM_MODE_FLAG_NVSYNC |		\
> +				 DRM_MODE_FLAG_INTERLACE |	\
> +				 DRM_MODE_FLAG_DBLSCAN |	\
> +				 DRM_MODE_FLAG_CSYNC |		\
> +				 DRM_MODE_FLAG_PCSYNC |		\
> +				 DRM_MODE_FLAG_NCSYNC |		\
> +				 DRM_MODE_FLAG_HSKEW |		\
> +				 DRM_MODE_FLAG_DBLCLK |		\
> +				 DRM_MODE_FLAG_CLKDIV2 |	\
> +				 DRM_MODE_FLAG_3D_MASK)
> +
>   /* DPMS flags */
>   /* bit compatible with the xorg definitions. */
>   #define DRM_MODE_DPMS_ON	0
> @@ -173,6 +191,10 @@ extern "C" {
>   		DRM_MODE_REFLECT_X | \
>   		DRM_MODE_REFLECT_Y)
>   
> +/* Content Protection Flags */
> +#define DRM_MODE_CONTENT_PROTECTION_UNDESIRED	0
> +#define DRM_MODE_CONTENT_PROTECTION_DESIRED     1
> +#define DRM_MODE_CONTENT_PROTECTION_ENABLED     2
>   
>   struct drm_mode_modeinfo {
>   	__u32 clock;
> diff --git a/include/drm-uapi/exynos_drm.h b/include/drm-uapi/exynos_drm.h
> index 76c34dd5..a00116b5 100644
> --- a/include/drm-uapi/exynos_drm.h
> +++ b/include/drm-uapi/exynos_drm.h
> @@ -135,172 +135,6 @@ struct drm_exynos_g2d_exec {
>   	__u64					async;
>   };
>   
> -enum drm_exynos_ops_id {
> -	EXYNOS_DRM_OPS_SRC,
> -	EXYNOS_DRM_OPS_DST,
> -	EXYNOS_DRM_OPS_MAX,
> -};
> -
> -struct drm_exynos_sz {
> -	__u32	hsize;
> -	__u32	vsize;
> -};
> -
> -struct drm_exynos_pos {
> -	__u32	x;
> -	__u32	y;
> -	__u32	w;
> -	__u32	h;
> -};
> -
> -enum drm_exynos_flip {
> -	EXYNOS_DRM_FLIP_NONE = (0 << 0),
> -	EXYNOS_DRM_FLIP_VERTICAL = (1 << 0),
> -	EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1),
> -	EXYNOS_DRM_FLIP_BOTH = EXYNOS_DRM_FLIP_VERTICAL |
> -			EXYNOS_DRM_FLIP_HORIZONTAL,
> -};
> -
> -enum drm_exynos_degree {
> -	EXYNOS_DRM_DEGREE_0,
> -	EXYNOS_DRM_DEGREE_90,
> -	EXYNOS_DRM_DEGREE_180,
> -	EXYNOS_DRM_DEGREE_270,
> -};
> -
> -enum drm_exynos_planer {
> -	EXYNOS_DRM_PLANAR_Y,
> -	EXYNOS_DRM_PLANAR_CB,
> -	EXYNOS_DRM_PLANAR_CR,
> -	EXYNOS_DRM_PLANAR_MAX,
> -};
> -
> -/**
> - * A structure for ipp supported property list.
> - *
> - * @version: version of this structure.
> - * @ipp_id: id of ipp driver.
> - * @count: count of ipp driver.
> - * @writeback: flag of writeback supporting.
> - * @flip: flag of flip supporting.
> - * @degree: flag of degree information.
> - * @csc: flag of csc supporting.
> - * @crop: flag of crop supporting.
> - * @scale: flag of scale supporting.
> - * @refresh_min: min hz of refresh.
> - * @refresh_max: max hz of refresh.
> - * @crop_min: crop min resolution.
> - * @crop_max: crop max resolution.
> - * @scale_min: scale min resolution.
> - * @scale_max: scale max resolution.
> - */
> -struct drm_exynos_ipp_prop_list {
> -	__u32	version;
> -	__u32	ipp_id;
> -	__u32	count;
> -	__u32	writeback;
> -	__u32	flip;
> -	__u32	degree;
> -	__u32	csc;
> -	__u32	crop;
> -	__u32	scale;
> -	__u32	refresh_min;
> -	__u32	refresh_max;
> -	__u32	reserved;
> -	struct drm_exynos_sz	crop_min;
> -	struct drm_exynos_sz	crop_max;
> -	struct drm_exynos_sz	scale_min;
> -	struct drm_exynos_sz	scale_max;
> -};
> -
> -/**
> - * A structure for ipp config.
> - *
> - * @ops_id: property of operation directions.
> - * @flip: property of mirror, flip.
> - * @degree: property of rotation degree.
> - * @fmt: property of image format.
> - * @sz: property of image size.
> - * @pos: property of image position(src-cropped,dst-scaler).
> - */
> -struct drm_exynos_ipp_config {
> -	__u32 ops_id;
> -	__u32 flip;
> -	__u32 degree;
> -	__u32	fmt;
> -	struct drm_exynos_sz	sz;
> -	struct drm_exynos_pos	pos;
> -};
> -
> -enum drm_exynos_ipp_cmd {
> -	IPP_CMD_NONE,
> -	IPP_CMD_M2M,
> -	IPP_CMD_WB,
> -	IPP_CMD_OUTPUT,
> -	IPP_CMD_MAX,
> -};
> -
> -/**
> - * A structure for ipp property.
> - *
> - * @config: source, destination config.
> - * @cmd: definition of command.
> - * @ipp_id: id of ipp driver.
> - * @prop_id: id of property.
> - * @refresh_rate: refresh rate.
> - */
> -struct drm_exynos_ipp_property {
> -	struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX];
> -	__u32	cmd;
> -	__u32	ipp_id;
> -	__u32	prop_id;
> -	__u32	refresh_rate;
> -};
> -
> -enum drm_exynos_ipp_buf_type {
> -	IPP_BUF_ENQUEUE,
> -	IPP_BUF_DEQUEUE,
> -};
> -
> -/**
> - * A structure for ipp buffer operations.
> - *
> - * @ops_id: operation directions.
> - * @buf_type: definition of buffer.
> - * @prop_id: id of property.
> - * @buf_id: id of buffer.
> - * @handle: Y, Cb, Cr each planar handle.
> - * @user_data: user data.
> - */
> -struct drm_exynos_ipp_queue_buf {
> -	__u32	ops_id;
> -	__u32	buf_type;
> -	__u32	prop_id;
> -	__u32	buf_id;
> -	__u32	handle[EXYNOS_DRM_PLANAR_MAX];
> -	__u32	reserved;
> -	__u64	user_data;
> -};
> -
> -enum drm_exynos_ipp_ctrl {
> -	IPP_CTRL_PLAY,
> -	IPP_CTRL_STOP,
> -	IPP_CTRL_PAUSE,
> -	IPP_CTRL_RESUME,
> -	IPP_CTRL_MAX,
> -};
> -
> -/**
> - * A structure for ipp start/stop operations.
> - *
> - * @prop_id: id of property.
> - * @ctrl: definition of control.
> - */
> -struct drm_exynos_ipp_cmd_ctrl {
> -	__u32	prop_id;
> -	__u32	ctrl;
> -};
> -
>   #define DRM_EXYNOS_GEM_CREATE		0x00
>   #define DRM_EXYNOS_GEM_MAP		0x01
>   /* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */
> @@ -312,11 +146,7 @@ struct drm_exynos_ipp_cmd_ctrl {
>   #define DRM_EXYNOS_G2D_SET_CMDLIST	0x21
>   #define DRM_EXYNOS_G2D_EXEC		0x22
>   
> -/* IPP - Image Post Processing */
> -#define DRM_EXYNOS_IPP_GET_PROPERTY	0x30
> -#define DRM_EXYNOS_IPP_SET_PROPERTY	0x31
> -#define DRM_EXYNOS_IPP_QUEUE_BUF	0x32
> -#define DRM_EXYNOS_IPP_CMD_CTRL	0x33
> +/* Reserved 0x30 ~ 0x33 for obsolete Exynos IPP ioctls */
>   
>   #define DRM_IOCTL_EXYNOS_GEM_CREATE		DRM_IOWR(DRM_COMMAND_BASE + \
>   		DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
> @@ -335,18 +165,8 @@ struct drm_exynos_ipp_cmd_ctrl {
>   #define DRM_IOCTL_EXYNOS_G2D_EXEC		DRM_IOWR(DRM_COMMAND_BASE + \
>   		DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
>   
> -#define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY	DRM_IOWR(DRM_COMMAND_BASE + \
> -		DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list)
> -#define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY	DRM_IOWR(DRM_COMMAND_BASE + \
> -		DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property)
> -#define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF	DRM_IOWR(DRM_COMMAND_BASE + \
> -		DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf)
> -#define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL		DRM_IOWR(DRM_COMMAND_BASE + \
> -		DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl)
> -
>   /* EXYNOS specific events */
>   #define DRM_EXYNOS_G2D_EVENT		0x80000000
> -#define DRM_EXYNOS_IPP_EVENT		0x80000001
>   
>   struct drm_exynos_g2d_event {
>   	struct drm_event	base;
> @@ -357,16 +177,6 @@ struct drm_exynos_g2d_event {
>   	__u32			reserved;
>   };
>   
> -struct drm_exynos_ipp_event {
> -	struct drm_event	base;
> -	__u64			user_data;
> -	__u32			tv_sec;
> -	__u32			tv_usec;
> -	__u32			prop_id;
> -	__u32			reserved;
> -	__u32			buf_id[EXYNOS_DRM_OPS_MAX];
> -};
> -
>   #if defined(__cplusplus)
>   }
>   #endif
> diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
> index 7f28eea4..16e452aa 100644
> --- a/include/drm-uapi/i915_drm.h
> +++ b/include/drm-uapi/i915_drm.h
> @@ -102,6 +102,46 @@ enum drm_i915_gem_engine_class {
>   	I915_ENGINE_CLASS_INVALID	= -1
>   };
>   
> +/**
> + * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
> + *
> + */
> +
> +enum drm_i915_pmu_engine_sample {
> +	I915_SAMPLE_BUSY = 0,
> +	I915_SAMPLE_WAIT = 1,
> +	I915_SAMPLE_SEMA = 2
> +};
> +
> +#define I915_PMU_SAMPLE_BITS (4)
> +#define I915_PMU_SAMPLE_MASK (0xf)
> +#define I915_PMU_SAMPLE_INSTANCE_BITS (8)
> +#define I915_PMU_CLASS_SHIFT \
> +	(I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS)
> +
> +#define __I915_PMU_ENGINE(class, instance, sample) \
> +	((class) << I915_PMU_CLASS_SHIFT | \
> +	(instance) << I915_PMU_SAMPLE_BITS | \
> +	(sample))
> +
> +#define I915_PMU_ENGINE_BUSY(class, instance) \
> +	__I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY)
> +
> +#define I915_PMU_ENGINE_WAIT(class, instance) \
> +	__I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT)
> +
> +#define I915_PMU_ENGINE_SEMA(class, instance) \
> +	__I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)
> +
> +#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x))
> +
> +#define I915_PMU_ACTUAL_FREQUENCY	__I915_PMU_OTHER(0)
> +#define I915_PMU_REQUESTED_FREQUENCY	__I915_PMU_OTHER(1)
> +#define I915_PMU_INTERRUPTS		__I915_PMU_OTHER(2)
> +#define I915_PMU_RC6_RESIDENCY		__I915_PMU_OTHER(3)
> +
> +#define I915_PMU_LAST I915_PMU_RC6_RESIDENCY
> +
>   /* Each region is a minimum of 16k, and there are at most 255 of them.
>    */
>   #define I915_NR_TEX_REGIONS 255	/* table size 2k - maximum due to use
> @@ -278,6 +318,7 @@ typedef struct _drm_i915_sarea {
>   #define DRM_I915_PERF_OPEN		0x36
>   #define DRM_I915_PERF_ADD_CONFIG	0x37
>   #define DRM_I915_PERF_REMOVE_CONFIG	0x38
> +#define DRM_I915_QUERY			0x39
>   
>   #define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
>   #define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
> @@ -335,6 +376,7 @@ typedef struct _drm_i915_sarea {
>   #define DRM_IOCTL_I915_PERF_OPEN	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
>   #define DRM_IOCTL_I915_PERF_ADD_CONFIG	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
>   #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
> +#define DRM_IOCTL_I915_QUERY			DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
>   
>   /* Allow drivers to submit batchbuffers directly to hardware, relying
>    * on the security mechanisms provided by hardware.
> @@ -1318,7 +1360,9 @@ struct drm_intel_overlay_attrs {
>    * active on a given plane.
>    */
>   
> -#define I915_SET_COLORKEY_NONE		(1<<0) /* disable color key matching */
> +#define I915_SET_COLORKEY_NONE		(1<<0) /* Deprecated. Instead set
> +						* flags==0 to disable colorkeying.
> +						*/
>   #define I915_SET_COLORKEY_DESTINATION	(1<<1)
>   #define I915_SET_COLORKEY_SOURCE	(1<<2)
>   struct drm_intel_sprite_colorkey {
> @@ -1564,15 +1608,115 @@ struct drm_i915_perf_oa_config {
>   	__u32 n_flex_regs;
>   
>   	/*
> -	 * These fields are pointers to tuples of u32 values (register
> -	 * address, value). For example the expected length of the buffer
> -	 * pointed by mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
> +	 * These fields are pointers to tuples of u32 values (register address,
> +	 * value). For example the expected length of the buffer pointed by
> +	 * mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
>   	 */
>   	__u64 mux_regs_ptr;
>   	__u64 boolean_regs_ptr;
>   	__u64 flex_regs_ptr;
>   };
>   
> +struct drm_i915_query_item {
> +	__u64 query_id;
> +#define DRM_I915_QUERY_TOPOLOGY_INFO    1
> +
> +	/*
> +	 * When set to zero by userspace, this is filled with the size of the
> +	 * data to be written at the data_ptr pointer. The kernel sets this
> +	 * value to a negative value to signal an error on a particular query
> +	 * item.
> +	 */
> +	__s32 length;
> +
> +	/*
> +	 * Unused for now. Must be cleared to zero.
> +	 */
> +	__u32 flags;
> +
> +	/*
> +	 * Data will be written at the location pointed by data_ptr when the
> +	 * value of length matches the length of the data to be written by the
> +	 * kernel.
> +	 */
> +	__u64 data_ptr;
> +};
> +
> +struct drm_i915_query {
> +	__u32 num_items;
> +
> +	/*
> +	 * Unused for now. Must be cleared to zero.
> +	 */
> +	__u32 flags;
> +
> +	/*
> +	 * This points to an array of num_items drm_i915_query_item structures.
> +	 */
> +	__u64 items_ptr;
> +};
> +
> +/*
> + * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
> + *
> + * data: contains the 3 pieces of information :
> + *
> + * - the slice mask with one bit per slice telling whether a slice is
> + *   available. The availability of slice X can be queried with the following
> + *   formula :
> + *
> + *           (data[X / 8] >> (X % 8)) & 1
> + *
> + * - the subslice mask for each slice with one bit per subslice telling
> + *   whether a subslice is available. The availability of subslice Y in slice
> + *   X can be queried with the following formula :
> + *
> + *           (data[subslice_offset +
> + *                 X * subslice_stride +
> + *                 Y / 8] >> (Y % 8)) & 1
> + *
> + * - the EU mask for each subslice in each slice with one bit per EU telling
> + *   whether an EU is available. The availability of EU Z in subslice Y in
> + *   slice X can be queried with the following formula :
> + *
> + *           (data[eu_offset +
> + *                 (X * max_subslices + Y) * eu_stride +
> + *                 Z / 8] >> (Z % 8)) & 1
> + */
> +struct drm_i915_query_topology_info {
> +	/*
> +	 * Unused for now. Must be cleared to zero.
> +	 */
> +	__u16 flags;
> +
> +	__u16 max_slices;
> +	__u16 max_subslices;
> +	__u16 max_eus_per_subslice;
> +
> +	/*
> +	 * Offset in data[] at which the subslice masks are stored.
> +	 */
> +	__u16 subslice_offset;
> +
> +	/*
> +	 * Stride at which each of the subslice masks for each slice are
> +	 * stored.
> +	 */
> +	__u16 subslice_stride;
> +
> +	/*
> +	 * Offset in data[] at which the EU masks are stored.
> +	 */
> +	__u16 eu_offset;
> +
> +	/*
> +	 * Stride at which each of the EU masks for each subslice are stored.
> +	 */
> +	__u16 eu_stride;
> +
> +	__u8 data[];
> +};
> +
>   #if defined(__cplusplus)
>   }
>   #endif
> diff --git a/include/drm-uapi/vc4_drm.h b/include/drm-uapi/vc4_drm.h
> index 3415a4b7..4117117b 100644
> --- a/include/drm-uapi/vc4_drm.h
> +++ b/include/drm-uapi/vc4_drm.h
> @@ -42,6 +42,9 @@ extern "C" {
>   #define DRM_VC4_GET_TILING                        0x09
>   #define DRM_VC4_LABEL_BO                          0x0a
>   #define DRM_VC4_GEM_MADVISE                       0x0b
> +#define DRM_VC4_PERFMON_CREATE                    0x0c
> +#define DRM_VC4_PERFMON_DESTROY                   0x0d
> +#define DRM_VC4_PERFMON_GET_VALUES                0x0e
>   
>   #define DRM_IOCTL_VC4_SUBMIT_CL           DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
>   #define DRM_IOCTL_VC4_WAIT_SEQNO          DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
> @@ -55,6 +58,9 @@ extern "C" {
>   #define DRM_IOCTL_VC4_GET_TILING          DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling)
>   #define DRM_IOCTL_VC4_LABEL_BO            DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo)
>   #define DRM_IOCTL_VC4_GEM_MADVISE         DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GEM_MADVISE, struct drm_vc4_gem_madvise)
> +#define DRM_IOCTL_VC4_PERFMON_CREATE      DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_CREATE, struct drm_vc4_perfmon_create)
> +#define DRM_IOCTL_VC4_PERFMON_DESTROY     DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_DESTROY, struct drm_vc4_perfmon_destroy)
> +#define DRM_IOCTL_VC4_PERFMON_GET_VALUES  DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_GET_VALUES, struct drm_vc4_perfmon_get_values)
>   
>   struct drm_vc4_submit_rcl_surface {
>   	__u32 hindex; /* Handle index, or ~0 if not present. */
> @@ -173,6 +179,15 @@ struct drm_vc4_submit_cl {
>   	 * wait ioctl).
>   	 */
>   	__u64 seqno;
> +
> +	/* ID of the perfmon to attach to this job. 0 means no perfmon. */
> +	__u32 perfmonid;
> +
> +	/* Unused field to align this struct on 64 bits. Must be set to 0.
> +	 * If one ever needs to add an u32 field to this struct, this field
> +	 * can be used.
> +	 */
> +	__u32 pad2;
>   };
>   
>   /**
> @@ -308,6 +323,7 @@ struct drm_vc4_get_hang_state {
>   #define DRM_VC4_PARAM_SUPPORTS_THREADED_FS	5
>   #define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER	6
>   #define DRM_VC4_PARAM_SUPPORTS_MADVISE		7
> +#define DRM_VC4_PARAM_SUPPORTS_PERFMON		8
>   
>   struct drm_vc4_get_param {
>   	__u32 param;
> @@ -352,6 +368,66 @@ struct drm_vc4_gem_madvise {
>   	__u32 pad;
>   };
>   
> +enum {
> +	VC4_PERFCNT_FEP_VALID_PRIMS_NO_RENDER,
> +	VC4_PERFCNT_FEP_VALID_PRIMS_RENDER,
> +	VC4_PERFCNT_FEP_CLIPPED_QUADS,
> +	VC4_PERFCNT_FEP_VALID_QUADS,
> +	VC4_PERFCNT_TLB_QUADS_NOT_PASSING_STENCIL,
> +	VC4_PERFCNT_TLB_QUADS_NOT_PASSING_Z_AND_STENCIL,
> +	VC4_PERFCNT_TLB_QUADS_PASSING_Z_AND_STENCIL,
> +	VC4_PERFCNT_TLB_QUADS_ZERO_COVERAGE,
> +	VC4_PERFCNT_TLB_QUADS_NON_ZERO_COVERAGE,
> +	VC4_PERFCNT_TLB_QUADS_WRITTEN_TO_COLOR_BUF,
> +	VC4_PERFCNT_PLB_PRIMS_OUTSIDE_VIEWPORT,
> +	VC4_PERFCNT_PLB_PRIMS_NEED_CLIPPING,
> +	VC4_PERFCNT_PSE_PRIMS_REVERSED,
> +	VC4_PERFCNT_QPU_TOTAL_IDLE_CYCLES,
> +	VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_VERTEX_COORD_SHADING,
> +	VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_FRAGMENT_SHADING,
> +	VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_EXEC_VALID_INST,
> +	VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_TMUS,
> +	VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_SCOREBOARD,
> +	VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_VARYINGS,
> +	VC4_PERFCNT_QPU_TOTAL_INST_CACHE_HIT,
> +	VC4_PERFCNT_QPU_TOTAL_INST_CACHE_MISS,
> +	VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_HIT,
> +	VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_MISS,
> +	VC4_PERFCNT_TMU_TOTAL_TEXT_QUADS_PROCESSED,
> +	VC4_PERFCNT_TMU_TOTAL_TEXT_CACHE_MISS,
> +	VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VDW_STALLED,
> +	VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VCD_STALLED,
> +	VC4_PERFCNT_L2C_TOTAL_L2_CACHE_HIT,
> +	VC4_PERFCNT_L2C_TOTAL_L2_CACHE_MISS,
> +	VC4_PERFCNT_NUM_EVENTS,
> +};
> +
> +#define DRM_VC4_MAX_PERF_COUNTERS	16
> +
> +struct drm_vc4_perfmon_create {
> +	__u32 id;
> +	__u32 ncounters;
> +	__u8 events[DRM_VC4_MAX_PERF_COUNTERS];
> +};
> +
> +struct drm_vc4_perfmon_destroy {
> +	__u32 id;
> +};
> +
> +/*
> + * Returns the values of the performance counters tracked by this
> + * perfmon (as an array of ncounters u64 values).
> + *
> + * No implicit synchronization is performed, so the user has to
> + * guarantee that any jobs using this perfmon have already been
> + * completed  (probably by blocking on the seqno returned by the
> + * last exec that used the perfmon).
> + */
> +struct drm_vc4_perfmon_get_values {
> +	__u32 id;
> +	__u64 values_ptr;
> +};
> +
>   #if defined(__cplusplus)
>   }
>   #endif
> diff --git a/lib/igt_perf.h b/lib/igt_perf.h
> index 7b66fc58..105b8cd9 100644
> --- a/lib/igt_perf.h
> +++ b/lib/igt_perf.h
> @@ -31,13 +31,6 @@
>   
>   #include "igt_gt.h"
>   
> -enum drm_i915_pmu_engine_sample {
> -	I915_SAMPLE_BUSY = 0,
> -	I915_SAMPLE_WAIT = 1,
> -	I915_SAMPLE_SEMA = 2,
> -	I915_ENGINE_SAMPLE_MAX /* non-ABI */
> -};
> -
>   #define I915_PMU_SAMPLE_BITS (4)
>   #define I915_PMU_SAMPLE_MASK (0xf)
>   #define I915_PMU_SAMPLE_INSTANCE_BITS (8)
> 

I think all up to (and including) I915_PMU_LAST should be nuked from 
this file. If you can do that while pushing great, if not I can do it later.

Either way:

Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev