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Sun, 27 Feb 2022 13:43:24 -0800 (PST) Received: from [192.168.1.211] ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id e10-20020ac24e0a000000b00443145afc25sm740873lfr.126.2022.02.27.13.43.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 27 Feb 2022 13:43:24 -0800 (PST) Message-ID: <62ebb074-b8de-0dc3-2bbc-e43dca9d2ced@linaro.org> Date: Mon, 28 Feb 2022 00:43:23 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.6.0 Subject: Re: [PATCH v2 2/3] dt-bindings: clock: add QCOM SM6125 display clock bindings Content-Language: en-GB To: Krzysztof Kozlowski , Marijn Suijten , phone-devel@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Konrad Dybcio , Martin Botka , Jami Kettunen , Pavel Dubrova , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20220226200911.230030-1-marijn.suijten@somainline.org> <20220226200911.230030-3-marijn.suijten@somainline.org> From: Dmitry Baryshkov In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 27/02/2022 13:03, Krzysztof Kozlowski wrote: > On 26/02/2022 21:09, Marijn Suijten wrote: >> From: Martin Botka >> >> Add device tree bindings for display clock controller for >> Qualcomm Technology Inc's SM6125 SoC. >> >> Signed-off-by: Martin Botka >> --- >> .../bindings/clock/qcom,dispcc-sm6125.yaml | 87 +++++++++++++++++++ >> .../dt-bindings/clock/qcom,dispcc-sm6125.h | 41 +++++++++ >> 2 files changed, 128 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml >> create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm6125.h >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml >> new file mode 100644 >> index 000000000000..3465042d0d9f >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml >> @@ -0,0 +1,87 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6125.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm Display Clock Controller Binding for SM6125 >> + >> +maintainers: >> + - Martin Botka >> + >> +description: | >> + Qualcomm display clock control module which supports the clocks and >> + power domains on SM6125. >> + >> + See also: >> + dt-bindings/clock/qcom,dispcc-sm6125.h >> + >> +properties: >> + compatible: >> + enum: >> + - qcom,sm6125-dispcc >> + >> + clocks: >> + items: >> + - description: Board XO source >> + - description: Byte clock from DSI PHY0 >> + - description: Pixel clock from DSI PHY0 >> + - description: Pixel clock from DSI PHY1 >> + - description: Link clock from DP PHY >> + - description: VCO DIV clock from DP PHY >> + - description: AHB config clock from GCC >> + >> + clock-names: >> + items: >> + - const: bi_tcxo >> + - const: dsi0_phy_pll_out_byteclk >> + - const: dsi0_phy_pll_out_dsiclk >> + - const: dsi1_phy_pll_out_dsiclk >> + - const: dp_phy_pll_link_clk >> + - const: dp_phy_pll_vco_div_clk >> + - const: cfg_ahb_clk >> + >> + '#clock-cells': >> + const: 1 >> + >> + '#power-domain-cells': >> + const: 1 >> + >> + reg: >> + maxItems: 1 >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - clock-names >> + - '#clock-cells' >> + - '#power-domain-cells' >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include >> + #include >> + clock-controller@5f00000 { >> + compatible = "qcom,sm6125-dispcc"; >> + reg = <0x5f00000 0x20000>; >> + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, >> + <&dsi0_phy 0>, >> + <&dsi0_phy 1>, >> + <0>, > > This does not look like a valid phandle. This clock is required, isn't it? Not, it's not required for general dispcc support. dispcc uses DSI and DP PHY clocks to provide respective pixel/byte/etc clocks. However if support for DP is not enabled, the dispcc can work w/o DP phy clock. Thus we typically add 0 phandles as placeholders for DSI/DP clock sources and populate them as support for respective interfaces gets implemented. > > > Best regards, > Krzysztof -- With best wishes Dmitry