From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:48271) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QRPJu-0005Dj-8U for qemu-devel@nongnu.org; Tue, 31 May 2011 09:49:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QRPJq-0003tX-Bj for qemu-devel@nongnu.org; Tue, 31 May 2011 09:49:18 -0400 Received: from cantor.suse.de ([195.135.220.2]:41260 helo=mx1.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QRPJq-0003tR-0V for qemu-devel@nongnu.org; Tue, 31 May 2011 09:49:14 -0400 Mime-Version: 1.0 (Apple Message framework v1084) Content-Type: text/plain; charset=us-ascii From: Alexander Graf In-Reply-To: <4DE4EE92.6070202@freebsd.org> Date: Tue, 31 May 2011 15:49:11 +0200 Content-Transfer-Encoding: quoted-printable Message-Id: <632F236C-3E24-4106-B281-5FC2E60CC28B@suse.de> References: <20110526160930.15535.57397.malonedeb@soybean.canonical.com> <20110526160931.15535.77446.malone@soybean.canonical.com> <589FAE95-5CD6-482C-83F3-AF1FF301D854@suse.de> <4DDEE33A.3080100@freebsd.org> <4DE4EE92.6070202@freebsd.org> Subject: Re: [Qemu-devel] [Bug 788697] Re: [PowerPC] [patch] mtmsr does not preserve high bits of MSR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Bug 788697 <788697@bugs.launchpad.net> Cc: qemu-devel@nongnu.org On 31.05.2011, at 15:35, Nathan Whitehorn wrote: > On 05/26/11 18:47, agraf wrote: >> On 27.05.2011, at 01:33, Nathan Whitehorn wrote: >>=20 >>> On 05/26/11 11:45, agraf wrote: >>>> On 26.05.2011, at 18:09, Nathan Whitehorn wrote: >>>>=20 >>>>> ** Patch added: "mtmstr.diff" >>>>> = https://bugs.launchpad.net/bugs/788697/+attachment/2143748/+files/mtmstr.d= iff >>>>>=20 >>>>> -- >>>>> You received this bug notification because you are a member of = qemu- >>>>> devel-ml, which is subscribed to QEMU. >>>>> https://bugs.launchpad.net/bugs/788697 >>>>>=20 >>>>> Title: >>>>> [PowerPC] [patch] mtmsr does not preserve high bits of MSR >>>>>=20 >>>>> Status in QEMU: >>>>> New >>>>>=20 >>>>> Bug description: >>>>> The mtmsr instruction on 64-bit PPC does not preserve the = high-order >>>>> 32-bits of the MSR the way it is supposed to, instead setting = them to >>>>> 0, which takes 64-bit code out of 64-bit mode. There is some code = that >>>>> does the right thing, but it brokenly only preserves these bits = when >>>>> the thread is not in 64-bit mode (i.e. when it doesn't matter). = The >>>>> attached patch unconditionally enables this code when = TARGET_PPC64 is >>>>> set, per the ISA spec, which fixes early boot failures trying to = start >>>>> FreeBSD/powerpc64 under qemu. >>>>>=20 >>>> Please send the patch as proper patch to the ML and CC me. >>> What isn't proper about the patch? I'm happy to re-email it, but = don't >>> want things to be in the wrong format. >>> -Nathan >> The patch needs a patch description in its header and a subject line >> (all of which are present in the bug, so it's a simple matter of >> copy&paste). Basically at the end of the day, I should be able to = save >> the mail and "git am" on it and simply have it in my tree :). >>=20 >> Also, does this get FreeBSD booting up to anything useful, so I can >> verify it helps? >=20 > OK, I'll send this one out to today. The other issue I'm having (aside=20= > from our own bugs), is that SPR_PIR is not implemented for the POWER7=20= > target. The architecture manual claims it is implemented on all = Book-3S=20 > compliant CPUs, but it seems to be implemented sort of ad-hoc in=20 > target-ppc.c (e.g. the 604, 620, and 7400 have it, but not the 750, = 970,=20 > or POWER7). So the reason POWER7 doesn't have it is probably because it simply does = the same as 970. Why 970 doesn't register PIR, I don't know, but to me = it sounds like a plain bug :). Just send a patch, CC me and David = Gibson. Alex