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Content-Language: en-US To: Jason Wang , Peter Xu Cc: Peter Maydell , QEMU Developers , Paolo Bonzini , Richard Henderson , Eduardo Habkost , "Michael S. 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envelope-from=Wei.Huang2@amd.com; helo=NAM10-MW2-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 3/31/22 21:09, Jason Wang wrote: > On Fri, Apr 1, 2022 at 2:30 AM Peter Xu wrote: >> >> On Thu, Mar 31, 2022 at 05:01:52PM +0100, Peter Maydell wrote: >>> Coverity points out some problems with hw/i386/amd_iommu.c's event >>> logging code -- specifically, CID 1487115 1487116 1487190 1487200 >>> 1487232 1487258 are all the same basic problem, which is that various >>> functions declare a local "uint64_t evt[4]", populate only some >>> bits of it and then write it to guest memory, so we end up using >>> uninitialized host data and leaking it to the guest. I was going to >>> write a fix for this, but in looking at the code I noticed that >>> it has more extensive problems: >>> >>> (1) these functions allocate an array of 4 64-bit values, >>> but we only copy 2 to the guest, because AMDVI_EVENT_LEN is 16. >>> Looking at the spec, I think that the length is right and it's >>> really 4 32-bit values (or 2 64-bit values, if you like). Yes, amd event log entry size is 16 bytes. This should be easy to fixed. >>> >>> (2) There are host-endianness bugs, because we assemble the >>> event as a set of host-endianness values but then write them >>> to guest memory as a bag-of-bytes with dma_memory_write() I doubt people will enable AMD IOMMUs in QEMU on non-x86 host. Nevertheless this can be problematic and should be addressed. >>> >>> (3) amdvi_encode_event() is throwing away most of its >>> "addr" argument, because it calls >>> amdvi_setevent_bits(evt, addr, 63, 64) apparently intending >>> that to write 64 bits starting at 63 bits into the packet, but >>> the amdvi_setevent_bits() function only ever updates one >>> uint64_t in the array, so it will in fact write bit 63 and >>> nothing else. Agreed >>> >>> (4) The claimed bit layout of the event structure doesn't >>> match up with the one in the spec document I found. This >>> could be because I found a document for some other bit >>> of hardware, of course. Could you elaborate? Are you referring to amdvi_setevent_bits(evt, info, 55, 8)? >>> >>> Anyway, adding all these up, the event logging probably >>> needs a bit of a restructuring, and that should ideally be >>> done by somebody who (a) knows the hardware we're emulating >>> here and (b) is in a position to test things. Any volunteers? >> >> Copying some AMD developers (from where I saw the last patches from)... > > Btw, the AMD IOMMU seems not to work for a while (just boot it with > virtio-blk and it still doesn't work). > This can be related to address space notifier problem I encountered. We will take care of these issues mentioned in this email thread. > Thanks > >> >> -- >> Peter Xu >> >