From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F070FC43219 for ; Wed, 16 Nov 2022 02:17:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231464AbiKPCRs (ORCPT ); Tue, 15 Nov 2022 21:17:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42702 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230175AbiKPCRq (ORCPT ); Tue, 15 Nov 2022 21:17:46 -0500 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0468D12ACB; Tue, 15 Nov 2022 18:17:44 -0800 (PST) Received: from kwepemi500011.china.huawei.com (unknown [172.30.72.56]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4NBmnD0gTXzqSSy; Wed, 16 Nov 2022 10:13:52 +0800 (CST) Received: from [10.67.103.39] (10.67.103.39) by kwepemi500011.china.huawei.com (7.221.188.124) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Wed, 16 Nov 2022 10:17:36 +0800 Message-ID: <6374483F.3060604@hisilicon.com> Date: Wed, 16 Nov 2022 10:17:35 +0800 From: Wei Xu User-Agent: Mozilla/5.0 (Windows NT 6.3; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 MIME-Version: 1.0 To: Pierre Gondois , CC: Rob Herring , Krzysztof Kozlowski , Florian Fainelli , Broadcom internal kernel review list , Ray Jui , Scott Branden , Tsahee Zidenberg , Antoine Tenart , Brijesh Singh , Suravee Suthikulpanit , Tom Lendacky , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Khuong Dinh , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , William Zhang , Anand Gore , Kursad Oney , =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= , Alim Akhtar , Shawn Guo , Li Yang , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Chester Lin , =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= , Matthias Brugger , NXP S32 Linux Team , Chanho Min , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Lars Povlsen , Steen Hegelund , Daniel Machon , , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Thierry Reding , Jonathan Hunter , Andy Gross , Bjorn Andersson , Konrad Dybcio , Geert Uytterhoeven , Magnus Damm , Heiko Stuebner , Kunihiko Hayashi , Masami Hiramatsu , Jisheng Zhang , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Viorel Suman , Abel Vesa , Ming Qian , Shijie Qin , Peng Fan , Shenwei Wang , Tim Harvey , Lucas Stach , Adam Ford , Richard Zhu , Li Jun , Markus Niebel , Joakim Zhang , Marek Vasut , Laurent Pinchart , Alexander Stein , Paul Elder , Martin Kepplinger , David Heidelberg , Oliver Graute , Liu Ying , Jacky Bai , Clark Wang , Wei Fang , Chris Packham , Vadym Kochan , Sameer Pujar , Akhil R , Mikko Perttunen , Prathamesh Shete , Sumit Gupta , Diogo Ivo , Vidya Sagar , Ashish Mhetre , Johan Jonker , Christopher Obbard , Ezequiel Garcia , Aswani Reddy , Shashank Prashar , Andi Shyti , , , , , , , , , , , , Subject: Re: [PATCH v2 09/23] arm64: dts: Update cache properties for hisilicon References: <20221107155825.1644604-1-pierre.gondois@arm.com> <20221107155825.1644604-10-pierre.gondois@arm.com> In-Reply-To: <20221107155825.1644604-10-pierre.gondois@arm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.67.103.39] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To kwepemi500011.china.huawei.com (7.221.188.124) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Hi Pierre, On 2022/11/7 23:57, Pierre Gondois wrote: > The DeviceTree Specification v0.3 specifies that the cache node > 'compatible' and 'cache-level' properties are 'required'. Cf. > s3.8 Multi-level and Shared Cache Nodes > The 'cache-unified' property should be present if one of the > properties for unified cache is present ('cache-size', ...). > > Update the Device Trees accordingly. > > Signed-off-by: Pierre Gondois Applied to the HiSilicon arm64 dt tree. Thanks! Best Regards, Wei > --- > arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 2 ++ > arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 2 ++ > arch/arm64/boot/dts/hisilicon/hip05.dtsi | 4 ++++ > arch/arm64/boot/dts/hisilicon/hip06.dtsi | 4 ++++ > arch/arm64/boot/dts/hisilicon/hip07.dtsi | 16 ++++++++++++++++ > 5 files changed, 28 insertions(+) > > diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi > index 8343d0cedde3..a57f35eb5ef6 100644 > --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi > +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi > @@ -203,10 +203,12 @@ CLUSTER_SLEEP_1: cluster-sleep-1 { > > A53_L2: l2-cache0 { > compatible = "cache"; > + cache-level = <2>; > }; > > A73_L2: l2-cache1 { > compatible = "cache"; > + cache-level = <2>; > }; > }; > > diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi > index ae0a7cfeeb47..f6d3202b0d1a 100644 > --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi > +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi > @@ -186,10 +186,12 @@ cpu7: cpu@103 { > > CLUSTER0_L2: l2-cache0 { > compatible = "cache"; > + cache-level = <2>; > }; > > CLUSTER1_L2: l2-cache1 { > compatible = "cache"; > + cache-level = <2>; > }; > }; > > diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi > index 7b2abd10d3d6..5b2b1bfd0d2a 100644 > --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi > +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi > @@ -211,18 +211,22 @@ cpu15: cpu@20303 { > > cluster0_l2: l2-cache0 { > compatible = "cache"; > + cache-level = <2>; > }; > > cluster1_l2: l2-cache1 { > compatible = "cache"; > + cache-level = <2>; > }; > > cluster2_l2: l2-cache2 { > compatible = "cache"; > + cache-level = <2>; > }; > > cluster3_l2: l2-cache3 { > compatible = "cache"; > + cache-level = <2>; > }; > }; > > diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi > index 2f8b03b0d365..291c2ee38288 100644 > --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi > +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi > @@ -211,18 +211,22 @@ cpu15: cpu@10303 { > > cluster0_l2: l2-cache0 { > compatible = "cache"; > + cache-level = <2>; > }; > > cluster1_l2: l2-cache1 { > compatible = "cache"; > + cache-level = <2>; > }; > > cluster2_l2: l2-cache2 { > compatible = "cache"; > + cache-level = <2>; > }; > > cluster3_l2: l2-cache3 { > compatible = "cache"; > + cache-level = <2>; > }; > }; > > diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi > index 1a16662f8867..b8746fb959b5 100644 > --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi > +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi > @@ -842,66 +842,82 @@ cpu63: cpu@70303 { > > cluster0_l2: l2-cache0 { > compatible = "cache"; > + cache-level = <2>; > }; > > cluster1_l2: l2-cache1 { > compatible = "cache"; > + cache-level = <2>; > }; > > cluster2_l2: l2-cache2 { > compatible = "cache"; > + cache-level = <2>; > }; > > cluster3_l2: l2-cache3 { > compatible = "cache"; > + cache-level = <2>; > }; > > cluster4_l2: l2-cache4 { > compatible = "cache"; > + cache-level = <2>; > }; > > cluster5_l2: l2-cache5 { > compatible = "cache"; > + cache-level = <2>; > }; > > cluster6_l2: l2-cache6 { > compatible = "cache"; > + cache-level = <2>; > }; > > cluster7_l2: l2-cache7 { > compatible = "cache"; > + cache-level = <2>; > }; > > cluster8_l2: l2-cache8 { > compatible = "cache"; > + cache-level = <2>; > }; > > cluster9_l2: l2-cache9 { > compatible = "cache"; > + cache-level = <2>; > }; > > cluster10_l2: l2-cache10 { > compatible = "cache"; > + cache-level = <2>; > }; > > cluster11_l2: l2-cache11 { > compatible = "cache"; > + cache-level = <2>; > }; > > cluster12_l2: l2-cache12 { > compatible = "cache"; > + cache-level = <2>; > }; > > cluster13_l2: l2-cache13 { > compatible = "cache"; > + cache-level = <2>; > }; > > cluster14_l2: l2-cache14 { > compatible = "cache"; > + cache-level = <2>; > }; > > cluster15_l2: l2-cache15 { > compatible = "cache"; > + cache-level = <2>; > }; > }; > >