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From: Jon Hunter <jonathanh@nvidia.com>
To: Marc Zyngier <maz@kernel.org>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Bjorn Helgaas <bhelgaas@google.com>
Cc: Frank Wunderlich <frank-w@public-files.de>,
	Thierry Reding <treding@nvidia.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Rob Herring <robh@kernel.org>, Will Deacon <will@kernel.org>,
	"K. Y. Srinivasan" <kys@microsoft.com>,
	Haiyang Zhang <haiyangz@microsoft.com>,
	"Stephen Hemminger" <sthemmin@microsoft.com>,
	Michael Kelley <mikelley@microsoft.com>,
	Wei Liu <wei.liu@kernel.org>,
	Thierry Reding <thierry.reding@gmail.com>,
	Ryder Lee <ryder.lee@mediatek.com>,
	Marek Vasut <marek.vasut+renesas@gmail.com>,
	Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
	Michal Simek <michal.simek@xilinx.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Bharat Kumar Gogada <bharatku@xilinx.com>,
	<linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-hyperv@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
	<linux-mediatek@lists.infradead.org>,
	<linux-renesas-soc@vger.kernel.org>, <kernel-team@android.com>
Subject: Re: [PATCH v3 01/14] PCI: tegra: Convert to MSI domains
Date: Mon, 19 Apr 2021 21:02:10 +0100	[thread overview]
Message-ID: <638a9996-c762-fa11-b740-6a41d4a83bcc@nvidia.com> (raw)
In-Reply-To: <316e8be4-fa70-75e8-8483-ae38036306e0@nvidia.com>


On 19/04/2021 20:19, Jon Hunter wrote:
> Hi Marc,
> 
> On 30/03/2021 16:11, Marc Zyngier wrote:
>> In anticipation of the removal of the msi_controller structure, convert
>> the Tegra host controller driver to MSI domains.
>>
>> We end-up with the usual two domain structure, the top one being a
>> generic PCI/MSI domain, the bottom one being Tegra-specific and handling
>> the actual HW interrupt allocation.
>>
>> While at it, convert the normal interrupt handler to a chained handler,
>> handle the controller's MSI IRQ edge triggered, support multiple MSIs
>> per device and use the AFI_MSI_EN_VEC* registers to provide MSI masking.
>>
>> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
>> [treding@nvidia.com: fix, clean up and address TODOs from Marc's draft]
>> Signed-off-by: Thierry Reding <treding@nvidia.com>
>> Signed-off-by: Marc Zyngier <maz@kernel.org>
> 
> 
> This change is breaking a suspend test that we are running on Tegra124
> Jetson-TK1. The Tegra124 Jetson TK1 uses a PCI based ethernet device ...
> 
> $ lspci
> 00:02.0 PCI bridge: NVIDIA Corporation TegraK1 PCIe x1 Bridge (rev a1)
> 01:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd.
> RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 0c)
> 
> After resuming from suspend, networking is no longer working. The reason
> why this breaks our suspend test is because that setup is using NFS for
> the rootfs. I am looking into it, but if anyone has any thoughts please
> let me know.


So the following does appear to fix it ...

diff --git a/drivers/pci/controller/pci-tegra.c
b/drivers/pci/controller/pci-tegra.c
index eaba7b2fab4a..558f02e0693d 100644
--- a/drivers/pci/controller/pci-tegra.c
+++ b/drivers/pci/controller/pci-tegra.c
@@ -1802,13 +1802,17 @@ static void tegra_pcie_enable_msi(struct
tegra_pcie *pcie)
 {
        const struct tegra_pcie_soc *soc = pcie->soc;
        struct tegra_msi *msi = &pcie->msi;
-       u32 reg;
+       u32 i, reg;

        afi_writel(pcie, msi->phys >> soc->msi_base_shift,
AFI_MSI_FPCI_BAR_ST);
        afi_writel(pcie, msi->phys, AFI_MSI_AXI_BAR_ST);
        /* this register is in 4K increments */
        afi_writel(pcie, 1, AFI_MSI_BAR_SZ);

+       /* enable all MSI vectors */
+       for (i = 0; i < 8; i++)
+               afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC(i));
+
        /* and unmask the MSI interrupt */
        reg = afi_readl(pcie, AFI_INTR_MASK);
        reg |= AFI_INTR_MASK_MSI_MASK;
@@ -1837,13 +1841,17 @@ static void tegra_pcie_msi_teardown(struct
tegra_pcie *pcie)

 static int tegra_pcie_disable_msi(struct tegra_pcie *pcie)
 {
-       u32 value;
+       u32 i, value;

        /* mask the MSI interrupt */
        value = afi_readl(pcie, AFI_INTR_MASK);
        value &= ~AFI_INTR_MASK_MSI_MASK;
        afi_writel(pcie, value, AFI_INTR_MASK);

+       /* disable all MSI vectors */
+       for (i = 0; i < 8; i++)
+               afi_writel(pcie, 0, AFI_MSI_EN_VEC(i));
+
        return 0;
 }


Any reason why that code was removed?

Thanks
Jon

-- 
nvpublic

WARNING: multiple messages have this Message-ID (diff)
From: Jon Hunter <jonathanh@nvidia.com>
To: Marc Zyngier <maz@kernel.org>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Bjorn Helgaas <bhelgaas@google.com>
Cc: Frank Wunderlich <frank-w@public-files.de>,
	Thierry Reding <treding@nvidia.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Rob Herring <robh@kernel.org>, Will Deacon <will@kernel.org>,
	"K. Y. Srinivasan" <kys@microsoft.com>,
	Haiyang Zhang <haiyangz@microsoft.com>,
	"Stephen Hemminger" <sthemmin@microsoft.com>,
	Michael Kelley <mikelley@microsoft.com>,
	 Wei Liu <wei.liu@kernel.org>,
	Thierry Reding <thierry.reding@gmail.com>,
	Ryder Lee <ryder.lee@mediatek.com>,
	Marek Vasut <marek.vasut+renesas@gmail.com>,
	Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
	Michal Simek <michal.simek@xilinx.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Bharat Kumar Gogada <bharatku@xilinx.com>,
	<linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-hyperv@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
	<linux-mediatek@lists.infradead.org>,
	<linux-renesas-soc@vger.kernel.org>, <kernel-team@android.com>
Subject: Re: [PATCH v3 01/14] PCI: tegra: Convert to MSI domains
Date: Mon, 19 Apr 2021 21:02:10 +0100	[thread overview]
Message-ID: <638a9996-c762-fa11-b740-6a41d4a83bcc@nvidia.com> (raw)
In-Reply-To: <316e8be4-fa70-75e8-8483-ae38036306e0@nvidia.com>


On 19/04/2021 20:19, Jon Hunter wrote:
> Hi Marc,
> 
> On 30/03/2021 16:11, Marc Zyngier wrote:
>> In anticipation of the removal of the msi_controller structure, convert
>> the Tegra host controller driver to MSI domains.
>>
>> We end-up with the usual two domain structure, the top one being a
>> generic PCI/MSI domain, the bottom one being Tegra-specific and handling
>> the actual HW interrupt allocation.
>>
>> While at it, convert the normal interrupt handler to a chained handler,
>> handle the controller's MSI IRQ edge triggered, support multiple MSIs
>> per device and use the AFI_MSI_EN_VEC* registers to provide MSI masking.
>>
>> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
>> [treding@nvidia.com: fix, clean up and address TODOs from Marc's draft]
>> Signed-off-by: Thierry Reding <treding@nvidia.com>
>> Signed-off-by: Marc Zyngier <maz@kernel.org>
> 
> 
> This change is breaking a suspend test that we are running on Tegra124
> Jetson-TK1. The Tegra124 Jetson TK1 uses a PCI based ethernet device ...
> 
> $ lspci
> 00:02.0 PCI bridge: NVIDIA Corporation TegraK1 PCIe x1 Bridge (rev a1)
> 01:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd.
> RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 0c)
> 
> After resuming from suspend, networking is no longer working. The reason
> why this breaks our suspend test is because that setup is using NFS for
> the rootfs. I am looking into it, but if anyone has any thoughts please
> let me know.


So the following does appear to fix it ...

diff --git a/drivers/pci/controller/pci-tegra.c
b/drivers/pci/controller/pci-tegra.c
index eaba7b2fab4a..558f02e0693d 100644
--- a/drivers/pci/controller/pci-tegra.c
+++ b/drivers/pci/controller/pci-tegra.c
@@ -1802,13 +1802,17 @@ static void tegra_pcie_enable_msi(struct
tegra_pcie *pcie)
 {
        const struct tegra_pcie_soc *soc = pcie->soc;
        struct tegra_msi *msi = &pcie->msi;
-       u32 reg;
+       u32 i, reg;

        afi_writel(pcie, msi->phys >> soc->msi_base_shift,
AFI_MSI_FPCI_BAR_ST);
        afi_writel(pcie, msi->phys, AFI_MSI_AXI_BAR_ST);
        /* this register is in 4K increments */
        afi_writel(pcie, 1, AFI_MSI_BAR_SZ);

+       /* enable all MSI vectors */
+       for (i = 0; i < 8; i++)
+               afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC(i));
+
        /* and unmask the MSI interrupt */
        reg = afi_readl(pcie, AFI_INTR_MASK);
        reg |= AFI_INTR_MASK_MSI_MASK;
@@ -1837,13 +1841,17 @@ static void tegra_pcie_msi_teardown(struct
tegra_pcie *pcie)

 static int tegra_pcie_disable_msi(struct tegra_pcie *pcie)
 {
-       u32 value;
+       u32 i, value;

        /* mask the MSI interrupt */
        value = afi_readl(pcie, AFI_INTR_MASK);
        value &= ~AFI_INTR_MASK_MSI_MASK;
        afi_writel(pcie, value, AFI_INTR_MASK);

+       /* disable all MSI vectors */
+       for (i = 0; i < 8; i++)
+               afi_writel(pcie, 0, AFI_MSI_EN_VEC(i));
+
        return 0;
 }


Any reason why that code was removed?

Thanks
Jon

-- 
nvpublic

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

WARNING: multiple messages have this Message-ID (diff)
From: Jon Hunter <jonathanh@nvidia.com>
To: Marc Zyngier <maz@kernel.org>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Bjorn Helgaas <bhelgaas@google.com>
Cc: Frank Wunderlich <frank-w@public-files.de>,
	Thierry Reding <treding@nvidia.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Rob Herring <robh@kernel.org>, Will Deacon <will@kernel.org>,
	"K. Y. Srinivasan" <kys@microsoft.com>,
	Haiyang Zhang <haiyangz@microsoft.com>,
	"Stephen Hemminger" <sthemmin@microsoft.com>,
	Michael Kelley <mikelley@microsoft.com>,
	 Wei Liu <wei.liu@kernel.org>,
	Thierry Reding <thierry.reding@gmail.com>,
	Ryder Lee <ryder.lee@mediatek.com>,
	Marek Vasut <marek.vasut+renesas@gmail.com>,
	Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
	Michal Simek <michal.simek@xilinx.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Bharat Kumar Gogada <bharatku@xilinx.com>,
	<linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-hyperv@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
	<linux-mediatek@lists.infradead.org>,
	<linux-renesas-soc@vger.kernel.org>, <kernel-team@android.com>
Subject: Re: [PATCH v3 01/14] PCI: tegra: Convert to MSI domains
Date: Mon, 19 Apr 2021 21:02:10 +0100	[thread overview]
Message-ID: <638a9996-c762-fa11-b740-6a41d4a83bcc@nvidia.com> (raw)
In-Reply-To: <316e8be4-fa70-75e8-8483-ae38036306e0@nvidia.com>


On 19/04/2021 20:19, Jon Hunter wrote:
> Hi Marc,
> 
> On 30/03/2021 16:11, Marc Zyngier wrote:
>> In anticipation of the removal of the msi_controller structure, convert
>> the Tegra host controller driver to MSI domains.
>>
>> We end-up with the usual two domain structure, the top one being a
>> generic PCI/MSI domain, the bottom one being Tegra-specific and handling
>> the actual HW interrupt allocation.
>>
>> While at it, convert the normal interrupt handler to a chained handler,
>> handle the controller's MSI IRQ edge triggered, support multiple MSIs
>> per device and use the AFI_MSI_EN_VEC* registers to provide MSI masking.
>>
>> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
>> [treding@nvidia.com: fix, clean up and address TODOs from Marc's draft]
>> Signed-off-by: Thierry Reding <treding@nvidia.com>
>> Signed-off-by: Marc Zyngier <maz@kernel.org>
> 
> 
> This change is breaking a suspend test that we are running on Tegra124
> Jetson-TK1. The Tegra124 Jetson TK1 uses a PCI based ethernet device ...
> 
> $ lspci
> 00:02.0 PCI bridge: NVIDIA Corporation TegraK1 PCIe x1 Bridge (rev a1)
> 01:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd.
> RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 0c)
> 
> After resuming from suspend, networking is no longer working. The reason
> why this breaks our suspend test is because that setup is using NFS for
> the rootfs. I am looking into it, but if anyone has any thoughts please
> let me know.


So the following does appear to fix it ...

diff --git a/drivers/pci/controller/pci-tegra.c
b/drivers/pci/controller/pci-tegra.c
index eaba7b2fab4a..558f02e0693d 100644
--- a/drivers/pci/controller/pci-tegra.c
+++ b/drivers/pci/controller/pci-tegra.c
@@ -1802,13 +1802,17 @@ static void tegra_pcie_enable_msi(struct
tegra_pcie *pcie)
 {
        const struct tegra_pcie_soc *soc = pcie->soc;
        struct tegra_msi *msi = &pcie->msi;
-       u32 reg;
+       u32 i, reg;

        afi_writel(pcie, msi->phys >> soc->msi_base_shift,
AFI_MSI_FPCI_BAR_ST);
        afi_writel(pcie, msi->phys, AFI_MSI_AXI_BAR_ST);
        /* this register is in 4K increments */
        afi_writel(pcie, 1, AFI_MSI_BAR_SZ);

+       /* enable all MSI vectors */
+       for (i = 0; i < 8; i++)
+               afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC(i));
+
        /* and unmask the MSI interrupt */
        reg = afi_readl(pcie, AFI_INTR_MASK);
        reg |= AFI_INTR_MASK_MSI_MASK;
@@ -1837,13 +1841,17 @@ static void tegra_pcie_msi_teardown(struct
tegra_pcie *pcie)

 static int tegra_pcie_disable_msi(struct tegra_pcie *pcie)
 {
-       u32 value;
+       u32 i, value;

        /* mask the MSI interrupt */
        value = afi_readl(pcie, AFI_INTR_MASK);
        value &= ~AFI_INTR_MASK_MSI_MASK;
        afi_writel(pcie, value, AFI_INTR_MASK);

+       /* disable all MSI vectors */
+       for (i = 0; i < 8; i++)
+               afi_writel(pcie, 0, AFI_MSI_EN_VEC(i));
+
        return 0;
 }


Any reason why that code was removed?

Thanks
Jon

-- 
nvpublic

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2021-04-19 20:02 UTC|newest]

Thread overview: 83+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-30 15:11 [PATCH v3 00/14] PCI/MSI: Getting rid of msi_controller, and other cleanups Marc Zyngier
2021-03-30 15:11 ` Marc Zyngier
2021-03-30 15:11 ` Marc Zyngier
2021-03-30 15:11 ` [PATCH v3 01/14] PCI: tegra: Convert to MSI domains Marc Zyngier
2021-03-30 15:11   ` Marc Zyngier
2021-03-30 15:11   ` Marc Zyngier
2021-04-19 19:19   ` Jon Hunter
2021-04-19 19:19     ` Jon Hunter
2021-04-19 19:19     ` Jon Hunter
2021-04-19 20:02     ` Jon Hunter [this message]
2021-04-19 20:02       ` Jon Hunter
2021-04-19 20:02       ` Jon Hunter
2021-04-20  8:39       ` Marc Zyngier
2021-04-20  8:39         ` Marc Zyngier
2021-04-20 12:45         ` Jon Hunter
2021-04-20 12:45           ` Jon Hunter
2021-04-20 12:45           ` Jon Hunter
2021-03-30 15:11 ` [PATCH v3 02/14] PCI: rcar: Don't allocate extra memory for the MSI capture address Marc Zyngier
2021-03-30 15:11   ` Marc Zyngier
2021-03-30 15:11   ` Marc Zyngier
2021-03-30 15:28   ` Lorenzo Pieralisi
2021-03-30 15:28     ` Lorenzo Pieralisi
2021-03-30 15:28     ` Lorenzo Pieralisi
2021-04-01 10:59     ` Yoshihiro Shimoda
2021-04-01 10:59       ` Yoshihiro Shimoda
2021-04-01 10:59       ` Yoshihiro Shimoda
2021-03-30 15:11 ` [PATCH v3 03/14] PCI: rcar: Convert to MSI domains Marc Zyngier
2021-03-30 15:11   ` Marc Zyngier
2021-03-30 15:11   ` Marc Zyngier
2021-04-01 10:19   ` Lorenzo Pieralisi
2021-04-01 10:19     ` Lorenzo Pieralisi
2021-04-01 10:19     ` Lorenzo Pieralisi
2021-04-01 10:38     ` Marc Zyngier
2021-04-01 10:38       ` Marc Zyngier
2021-04-01 10:38       ` Marc Zyngier
2021-04-01 11:03       ` Lorenzo Pieralisi
2021-04-01 11:03         ` Lorenzo Pieralisi
2021-04-01 11:03         ` Lorenzo Pieralisi
2021-03-30 15:11 ` [PATCH v3 04/14] PCI: xilinx: Don't allocate extra memory for the MSI capture address Marc Zyngier
2021-03-30 15:11   ` Marc Zyngier
2021-03-30 15:11   ` Marc Zyngier
2021-03-30 15:11 ` [PATCH v3 05/14] PCI: xilinx: Convert to MSI domains Marc Zyngier
2021-03-30 15:11   ` Marc Zyngier
2021-03-30 15:11   ` Marc Zyngier
2021-03-30 15:11 ` [PATCH v3 06/14] PCI: hv: Drop msi_controller structure Marc Zyngier
2021-03-30 15:11   ` Marc Zyngier
2021-03-30 15:11   ` Marc Zyngier
2021-03-30 15:11 ` [PATCH v3 07/14] PCI/MSI: Drop use of msi_controller from core code Marc Zyngier
2021-03-30 15:11   ` Marc Zyngier
2021-03-30 15:11   ` Marc Zyngier
2021-03-30 15:11 ` [PATCH v3 08/14] PCI/MSI: Kill msi_controller structure Marc Zyngier
2021-03-30 15:11   ` Marc Zyngier
2021-03-30 15:11   ` Marc Zyngier
2021-03-30 15:11 ` [PATCH v3 09/14] PCI/MSI: Kill default_teardown_msi_irqs() Marc Zyngier
2021-03-30 15:11   ` Marc Zyngier
2021-03-30 15:11   ` Marc Zyngier
2021-03-30 15:11 ` [PATCH v3 10/14] PCI/MSI: Let PCI host bridges declare their reliance on MSI domains Marc Zyngier
2021-03-30 15:11   ` Marc Zyngier
2021-03-30 15:11   ` Marc Zyngier
2021-03-30 15:11 ` [PATCH v3 11/14] PCI/MSI: Make pci_host_common_probe() declare its " Marc Zyngier
2021-03-30 15:11   ` Marc Zyngier
2021-03-30 15:11   ` Marc Zyngier
2021-03-30 15:11 ` [PATCH v3 12/14] PCI: mediatek: Advertise lack of built-in MSI handling Marc Zyngier
2021-03-30 15:11   ` Marc Zyngier
2021-03-30 15:11   ` Marc Zyngier
2021-03-30 15:11 ` [PATCH v3 13/14] PCI/MSI: Document the various ways of ending up with NO_MSI Marc Zyngier
2021-03-30 15:11   ` Marc Zyngier
2021-03-30 15:11   ` Marc Zyngier
2021-05-18  4:28   ` Jeremy Linton
2021-05-18  4:28     ` Jeremy Linton
2021-05-18  4:28     ` Jeremy Linton
2021-05-18  8:59     ` Marc Zyngier
2021-05-18  8:59       ` Marc Zyngier
2021-05-18  8:59       ` Marc Zyngier
2021-03-30 15:11 ` [PATCH v3 14/14] PCI: Refactor HT advertising of NO_MSI flag Marc Zyngier
2021-03-30 15:11   ` Marc Zyngier
2021-03-30 15:11   ` Marc Zyngier
2021-04-01 11:27 ` [PATCH v3 00/14] PCI/MSI: Getting rid of msi_controller, and other cleanups Lorenzo Pieralisi
2021-04-01 11:27   ` Lorenzo Pieralisi
2021-04-01 11:27   ` Lorenzo Pieralisi
2021-04-01 12:07   ` Marc Zyngier
2021-04-01 12:07     ` Marc Zyngier
2021-04-01 12:07     ` Marc Zyngier

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