* [PATCH 0/8] drm/i915/dsi: i2c/gpio
@ 2016-02-04 10:50 Jani Nikula
2016-02-04 10:50 ` [PATCH 1/8] drm/i915/dsi: defend gpio table against out of bounds access Jani Nikula
` (9 more replies)
0 siblings, 10 replies; 36+ messages in thread
From: Jani Nikula @ 2016-02-04 10:50 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Sme fixes to i2c/gpio elements in dsi. I think patches 1-4 are needed
for bxt at this time. The remaining patches don't really help, since the
sideband code is vlv/chv specific anyway.
BR,
Jani.
Deepak M (2):
drm/i915: Extend gpio read/write to other cores
drm/i915/dsi: Added the generic gpio sequence support and gpio table
Jani Nikula (5):
drm/i915/dsi: defend gpio table against out of bounds access
drm/i915/dsi: don't pass arbitrary data to sideband
drm/i915/dsi: skip gpio element execution when not supported
drm/i915: put the IOSF port defines in numerical order
drm/i915/vlv: drop unused vlv_gps_core_read/write functions
vkorjani (1):
drm/i915: Adding the parsing logic for the i2c element
drivers/gpu/drm/i915/i915_drv.h | 6 +-
drivers/gpu/drm/i915/i915_reg.h | 13 +-
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 669 +++++++++++++++++++++++++++--
drivers/gpu/drm/i915/intel_sideband.c | 23 +-
4 files changed, 641 insertions(+), 70 deletions(-)
--
2.1.4
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^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 1/8] drm/i915/dsi: defend gpio table against out of bounds access
2016-02-04 10:50 [PATCH 0/8] drm/i915/dsi: i2c/gpio Jani Nikula
@ 2016-02-04 10:50 ` Jani Nikula
2016-02-04 15:40 ` Ville Syrjälä
2016-02-04 10:50 ` [PATCH 2/8] drm/i915/dsi: don't pass arbitrary data to sideband Jani Nikula
` (8 subsequent siblings)
9 siblings, 1 reply; 36+ messages in thread
From: Jani Nikula @ 2016-02-04 10:50 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Do not blindly trust the VBT data used for indexing.
Cc: stable@vger.kernel.org
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 1d43e6f37fc1..4775aa5462e8 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -209,6 +209,11 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
/* pull up/down */
action = *data++;
+ if (gpio >= ARRAY_SIZE(gtable)) {
+ DRM_DEBUG_KMS("unknown gpio %u\n", gpio);
+ goto out;
+ }
+
function = gtable[gpio].function_reg;
pad = gtable[gpio].pad_reg;
@@ -226,6 +231,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
vlv_gpio_nc_write(dev_priv, pad, val);
mutex_unlock(&dev_priv->sb_lock);
+out:
return data;
}
--
2.1.4
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^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 2/8] drm/i915/dsi: don't pass arbitrary data to sideband
2016-02-04 10:50 [PATCH 0/8] drm/i915/dsi: i2c/gpio Jani Nikula
2016-02-04 10:50 ` [PATCH 1/8] drm/i915/dsi: defend gpio table against out of bounds access Jani Nikula
@ 2016-02-04 10:50 ` Jani Nikula
2016-02-04 15:41 ` Ville Syrjälä
2016-02-04 10:50 ` [PATCH 3/8] drm/i915: Adding the parsing logic for the i2c element Jani Nikula
` (7 subsequent siblings)
9 siblings, 1 reply; 36+ messages in thread
From: Jani Nikula @ 2016-02-04 10:50 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Since sequence block v2 the second byte contains flags other than just
pull up/down. Don't pass arbitrary data to the sideband interface.
The rest may or may not work for sequence block v2, but there should be
no harm done.
Cc: stable@vger.kernel.org
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 4775aa5462e8..6f013efba45b 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -207,7 +207,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
gpio = *data++;
/* pull up/down */
- action = *data++;
+ action = *data++ & 1;
if (gpio >= ARRAY_SIZE(gtable)) {
DRM_DEBUG_KMS("unknown gpio %u\n", gpio);
--
2.1.4
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 3/8] drm/i915: Adding the parsing logic for the i2c element
2016-02-04 10:50 [PATCH 0/8] drm/i915/dsi: i2c/gpio Jani Nikula
2016-02-04 10:50 ` [PATCH 1/8] drm/i915/dsi: defend gpio table against out of bounds access Jani Nikula
2016-02-04 10:50 ` [PATCH 2/8] drm/i915/dsi: don't pass arbitrary data to sideband Jani Nikula
@ 2016-02-04 10:50 ` Jani Nikula
2016-02-04 15:28 ` Ville Syrjälä
2016-02-04 10:50 ` [PATCH 4/8] drm/i915/dsi: skip gpio element execution when not supported Jani Nikula
` (6 subsequent siblings)
9 siblings, 1 reply; 36+ messages in thread
From: Jani Nikula @ 2016-02-04 10:50 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: vkorjani <vikas.korjani@intel.com>
New sequence element for i2c is been added in the
mipi sequence block of the VBT. This patch parses
and executes the i2c sequence.
v2: Add i2c_put_adapter call(Jani), rebase
v3: corrected the retry loop(Jani), rebase
v4 by Jani:
- don't put the adapter if get fails
- print an error message if all retries exhausted
- use a for loop
- fix warnings for unused variables
v5 by Jani:
- rebase on the skip i2c element patch
v6: by Jani:
- ignore the gmbus i2c elements (Ville)
Signed-off-by: vkorjani <vikas.korjani@intel.com>
Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 64 ++++++++++++++++++++++++++++--
1 file changed, 61 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 6f013efba45b..f4d303ee538b 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -31,6 +31,7 @@
#include <drm/drm_panel.h>
#include <linux/slab.h>
#include <video/mipi_display.h>
+#include <linux/i2c.h>
#include <asm/intel-mid.h>
#include <video/mipi_display.h>
#include "i915_drv.h"
@@ -235,9 +236,66 @@ out:
return data;
}
-static const u8 *mipi_exec_i2c_skip(struct intel_dsi *intel_dsi, const u8 *data)
+static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
{
- return data + *(data + 6) + 7;
+ struct i2c_adapter *adapter;
+ int ret, i;
+ u8 reg_offset, payload_size;
+ struct i2c_msg msg;
+ u8 *transmit_buffer;
+ u8 flag, resource_id, bus_number;
+ u16 slave_add;
+
+ flag = *data++;
+ resource_id = *data++;
+ bus_number = *data++;
+ slave_add = *(u16 *)(data);
+ data += 2;
+ reg_offset = *data++;
+ payload_size = *data++;
+
+ if (resource_id == 0xff || bus_number == 0xff) {
+ DRM_DEBUG_KMS("ignoring gmbus (resource id %02x, bus %02x)\n",
+ resource_id, bus_number);
+ goto out;
+ }
+
+ adapter = i2c_get_adapter(bus_number);
+ if (!adapter) {
+ DRM_ERROR("i2c_get_adapter(%u)\n", bus_number);
+ goto out;
+ }
+
+ transmit_buffer = kmalloc(1 + payload_size, GFP_TEMPORARY);
+ if (!transmit_buffer)
+ goto out_put;
+
+ transmit_buffer[0] = reg_offset;
+ memcpy(&transmit_buffer[1], data, payload_size);
+
+ msg.addr = slave_add;
+ msg.flags = 0;
+ msg.len = payload_size + 1;
+ msg.buf = &transmit_buffer[0];
+
+ for (i = 0; i < 6; i++) {
+ ret = i2c_transfer(adapter, &msg, 1);
+ if (ret == 1) {
+ goto out_free;
+ } else if (ret == -EAGAIN) {
+ usleep_range(1000, 2500);
+ } else {
+ break;
+ }
+ }
+
+ DRM_ERROR("i2c transfer failed: %d\n", ret);
+out_free:
+ kfree(transmit_buffer);
+out_put:
+ i2c_put_adapter(adapter);
+out:
+ return data + payload_size;
}
typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
@@ -246,7 +304,7 @@ static const fn_mipi_elem_exec exec_elem[] = {
[MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet,
[MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay,
[MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio,
- [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c_skip,
+ [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c,
};
/*
--
2.1.4
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 4/8] drm/i915/dsi: skip gpio element execution when not supported
2016-02-04 10:50 [PATCH 0/8] drm/i915/dsi: i2c/gpio Jani Nikula
` (2 preceding siblings ...)
2016-02-04 10:50 ` [PATCH 3/8] drm/i915: Adding the parsing logic for the i2c element Jani Nikula
@ 2016-02-04 10:50 ` Jani Nikula
2016-02-04 15:36 ` Ville Syrjälä
2016-02-04 16:52 ` [PATCH v2] " Jani Nikula
2016-02-04 10:50 ` [PATCH 5/8] drm/i915: put the IOSF port defines in numerical order Jani Nikula
` (5 subsequent siblings)
9 siblings, 2 replies; 36+ messages in thread
From: Jani Nikula @ 2016-02-04 10:50 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Skip v3 gpio element because the support is not there, and skip gpio
element on non-vlv/chv because the sideband code is vlv/chv specific.
Cc: drm-intel-fixes@lists.freedesktop.org
Fixes: 2a33d93486f2 ("drm/i915/bios: add support for MIPI sequence block v3")
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index f4d303ee538b..3e1e70f81506 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -205,6 +205,9 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
struct drm_device *dev = intel_dsi->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ if (dev_priv->vbt.dsi.seq_version >= 3)
+ data++;
+
gpio = *data++;
/* pull up/down */
@@ -215,6 +218,16 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
goto out;
}
+ if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
+ DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
+ goto out;
+ }
+
+ if (dev_priv->vbt.dsi.seq_version >= 3) {
+ DRM_DEBUG_KMS("GPIO element v3 not supported\n");
+ goto out;
+ }
+
function = gtable[gpio].function_reg;
pad = gtable[gpio].pad_reg;
--
2.1.4
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 5/8] drm/i915: put the IOSF port defines in numerical order
2016-02-04 10:50 [PATCH 0/8] drm/i915/dsi: i2c/gpio Jani Nikula
` (3 preceding siblings ...)
2016-02-04 10:50 ` [PATCH 4/8] drm/i915/dsi: skip gpio element execution when not supported Jani Nikula
@ 2016-02-04 10:50 ` Jani Nikula
2016-02-04 16:05 ` Ville Syrjälä
2016-02-04 10:50 ` [PATCH 6/8] drm/i915/vlv: drop unused vlv_gps_core_read/write functions Jani Nikula
` (4 subsequent siblings)
9 siblings, 1 reply; 36+ messages in thread
From: Jani Nikula @ 2016-02-04 10:50 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Make it easier to spot duplicates.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c0bd691b41f8..f3b4b19198b9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -610,16 +610,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define IOSF_BYTE_ENABLES_SHIFT 4
#define IOSF_BAR_SHIFT 1
#define IOSF_SB_BUSY (1<<0)
-#define IOSF_PORT_BUNIT 0x3
-#define IOSF_PORT_PUNIT 0x4
+#define IOSF_PORT_BUNIT 0x03
+#define IOSF_PORT_PUNIT 0x04
#define IOSF_PORT_NC 0x11
#define IOSF_PORT_DPIO 0x12
-#define IOSF_PORT_DPIO_2 0x1a
#define IOSF_PORT_GPIO_NC 0x13
#define IOSF_PORT_CCK 0x14
-#define IOSF_PORT_CCU 0xA9
+#define IOSF_PORT_DPIO_2 0x1a
+#define IOSF_PORT_FLISDSI 0x1b
#define IOSF_PORT_GPS_CORE 0x48
-#define IOSF_PORT_FLISDSI 0x1B
+#define IOSF_PORT_CCU 0xa9
#define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
#define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
--
2.1.4
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^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 6/8] drm/i915/vlv: drop unused vlv_gps_core_read/write functions
2016-02-04 10:50 [PATCH 0/8] drm/i915/dsi: i2c/gpio Jani Nikula
` (4 preceding siblings ...)
2016-02-04 10:50 ` [PATCH 5/8] drm/i915: put the IOSF port defines in numerical order Jani Nikula
@ 2016-02-04 10:50 ` Jani Nikula
2016-02-04 16:12 ` Ville Syrjälä
2016-02-04 10:50 ` [PATCH 7/8] drm/i915: Extend gpio read/write to other cores Jani Nikula
` (3 subsequent siblings)
9 siblings, 1 reply; 36+ messages in thread
From: Jani Nikula @ 2016-02-04 10:50 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Not needed.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/i915_reg.h | 1 -
drivers/gpu/drm/i915/intel_sideband.c | 14 --------------
3 files changed, 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 77227a39f3d5..af601be8b490 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3483,8 +3483,6 @@ u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
-u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
-void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f3b4b19198b9..c761fa2f3b8b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -618,7 +618,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define IOSF_PORT_CCK 0x14
#define IOSF_PORT_DPIO_2 0x1a
#define IOSF_PORT_FLISDSI 0x1b
-#define IOSF_PORT_GPS_CORE 0x48
#define IOSF_PORT_CCU 0xa9
#define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
#define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 8831fc579ade..f5b0ab6f5942 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -171,20 +171,6 @@ void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
SB_CRWRDA_NP, reg, &val);
}
-u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg)
-{
- u32 val = 0;
- vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPS_CORE,
- SB_CRRDDA_NP, reg, &val);
- return val;
-}
-
-void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
-{
- vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPS_CORE,
- SB_CRWRDA_NP, reg, &val);
-}
-
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
{
u32 val = 0;
--
2.1.4
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^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 7/8] drm/i915: Extend gpio read/write to other cores
2016-02-04 10:50 [PATCH 0/8] drm/i915/dsi: i2c/gpio Jani Nikula
` (5 preceding siblings ...)
2016-02-04 10:50 ` [PATCH 6/8] drm/i915/vlv: drop unused vlv_gps_core_read/write functions Jani Nikula
@ 2016-02-04 10:50 ` Jani Nikula
2016-02-04 15:39 ` Ville Syrjälä
2016-02-04 16:55 ` [PATCH v5] " Jani Nikula
2016-02-04 10:50 ` [PATCH 8/8] drm/i915/dsi: Added the generic gpio sequence support and gpio table Jani Nikula
` (2 subsequent siblings)
9 siblings, 2 replies; 36+ messages in thread
From: Jani Nikula @ 2016-02-04 10:50 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Deepak M <m.deepak@intel.com>
Make the gpio read/write functions more generic iosf sideband read/write
functions, taking the iosf port as argument.
v2: rebase
v3: rebase
v4 by Jani: address Ville's review
Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 5 +++--
drivers/gpu/drm/i915/intel_sideband.c | 9 +++++----
4 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index af601be8b490..47da528c16d0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3475,8 +3475,8 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
-u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
-void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
+u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
+void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c761fa2f3b8b..d00e5b8e5469 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -618,6 +618,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define IOSF_PORT_CCK 0x14
#define IOSF_PORT_DPIO_2 0x1a
#define IOSF_PORT_FLISDSI 0x1b
+#define IOSF_PORT_GPIO_SC 0x48
+#define IOSF_PORT_GPIO_SUS 0xa8
#define IOSF_PORT_CCU 0xa9
#define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
#define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 3e1e70f81506..de1966552a33 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -235,14 +235,15 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
if (!gtable[gpio].init) {
/* program the function */
/* FIXME: remove constant below */
- vlv_gpio_nc_write(dev_priv, function, 0x2000CC00);
+ vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, function,
+ 0x2000CC00);
gtable[gpio].init = 1;
}
val = 0x4 | action;
/* pull up/down */
- vlv_gpio_nc_write(dev_priv, pad, val);
+ vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, pad, val);
mutex_unlock(&dev_priv->sb_lock);
out:
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index f5b0ab6f5942..78c3d93fd963 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -129,17 +129,18 @@ u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
return val;
}
-u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg)
+u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg)
{
u32 val = 0;
- vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,
+ vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), port,
SB_CRRDDA_NP, reg, &val);
return val;
}
-void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
+void vlv_iosf_sb_write(struct drm_i915_private *dev_priv,
+ u8 port, u32 reg, u32 val)
{
- vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,
+ vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), port,
SB_CRWRDA_NP, reg, &val);
}
--
2.1.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 8/8] drm/i915/dsi: Added the generic gpio sequence support and gpio table
2016-02-04 10:50 [PATCH 0/8] drm/i915/dsi: i2c/gpio Jani Nikula
` (6 preceding siblings ...)
2016-02-04 10:50 ` [PATCH 7/8] drm/i915: Extend gpio read/write to other cores Jani Nikula
@ 2016-02-04 10:50 ` Jani Nikula
2016-02-04 17:51 ` Ville Syrjälä
2016-02-04 12:46 ` ✓ Fi.CI.BAT: success for drm/i915/dsi: i2c/gpio Patchwork
2016-02-05 7:31 ` ✗ Fi.CI.BAT: failure for drm/i915/dsi: i2c/gpio (rev3) Patchwork
9 siblings, 1 reply; 36+ messages in thread
From: Jani Nikula @ 2016-02-04 10:50 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Deepak M <m.deepak@intel.com>
The generic gpio is sequence is parsed from the VBT and the
GPIO table is updated with the North core, South core and
SUS core elements.
v2: Move changes in sideband.c file to new patch(Jani), rebase
v3: Moved the Macro`s to intel_dsi_panel_vbt.c (Jani)
v3 by Jani
- rebase on previous patches
- don't return null on errors
Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
Mmmh, the gpio table actually has some pretty scary stuff. We shouldn't
trust the vbt not to clobber some of the GPIOs listed in the table!
Also, is this really vlv specific as noted by Ville? What about chv, not
to mention bxt?!
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 589 +++++++++++++++++++++++++++--
1 file changed, 548 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index de1966552a33..b85d935617ef 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -59,30 +59,360 @@ static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel)
#define NS_KHZ_RATIO 1000000
-#define GPI0_NC_0_HV_DDI0_HPD 0x4130
-#define GPIO_NC_0_HV_DDI0_PAD 0x4138
-#define GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
-#define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD 0x4128
-#define GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
-#define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD 0x4118
-#define GPIO_NC_3_PANEL0_VDDEN 0x4140
-#define GPIO_NC_3_PANEL0_VDDEN_PAD 0x4148
-#define GPIO_NC_4_PANEL0_BLKEN 0x4150
-#define GPIO_NC_4_PANEL0_BLKEN_PAD 0x4158
-#define GPIO_NC_5_PANEL0_BLKCTL 0x4160
-#define GPIO_NC_5_PANEL0_BLKCTL_PAD 0x4168
-#define GPIO_NC_6_PCONF0 0x4180
-#define GPIO_NC_6_PAD 0x4188
-#define GPIO_NC_7_PCONF0 0x4190
-#define GPIO_NC_7_PAD 0x4198
-#define GPIO_NC_8_PCONF0 0x4170
-#define GPIO_NC_8_PAD 0x4178
-#define GPIO_NC_9_PCONF0 0x4100
-#define GPIO_NC_9_PAD 0x4108
-#define GPIO_NC_10_PCONF0 0x40E0
-#define GPIO_NC_10_PAD 0x40E8
-#define GPIO_NC_11_PCONF0 0x40F0
-#define GPIO_NC_11_PAD 0x40F8
+#define MAX_GPIO_NUM_NC 26
+#define MAX_GPIO_NUM_SC 128
+#define MAX_GPIO_NUM 172
+
+#define HV_DDI0_HPD_GPIONC_0_PCONF0 0x4130
+#define HV_DDI0_HPD_GPIONC_0_PAD 0x4138
+#define HV_DDI0_DDC_SDA_GPIONC_1_PCONF0 0x4120
+#define HV_DDI0_DDC_SDA_GPIONC_1_PAD 0x4128
+#define HV_DDI0_DDC_SCL_GPIONC_2_PCONF0 0x4110
+#define HV_DDI0_DDC_SCL_GPIONC_2_PAD 0x4118
+#define PANEL0_VDDEN_GPIONC_3_PCONF0 0x4140
+#define PANEL0_VDDEN_GPIONC_3_PAD 0x4148
+#define PANEL0_BKLTEN_GPIONC_4_PCONF0 0x4150
+#define PANEL0_BKLTEN_GPIONC_4_PAD 0x4158
+#define PANEL0_BKLTCTL_GPIONC_5_PCONF0 0x4160
+#define PANEL0_BKLTCTL_GPIONC_5_PAD 0x4168
+#define HV_DDI1_HPD_GPIONC_6_PCONF0 0x4180
+#define HV_DDI1_HPD_GPIONC_6_PAD 0x4188
+#define HV_DDI1_DDC_SDA_GPIONC_7_PCONF0 0x4190
+#define HV_DDI1_DDC_SDA_GPIONC_7_PAD 0x4198
+#define HV_DDI1_DDC_SCL_GPIONC_8_PCONF0 0x4170
+#define HV_DDI1_DDC_SCL_GPIONC_8_PAD 0x4178
+#define PANEL1_VDDEN_GPIONC_9_PCONF0 0x4100
+#define PANEL1_VDDEN_GPIONC_9_PAD 0x4108
+#define PANEL1_BKLTEN_GPIONC_10_PCONF0 0x40E0
+#define PANEL1_BKLTEN_GPIONC_10_PAD 0x40E8
+#define PANEL1_BKLTCTL_GPIONC_11_PCONF0 0x40F0
+#define PANEL1_BKLTCTL_GPIONC_11_PAD 0x40F8
+#define GP_INTD_DSI_TE1_GPIONC_12_PCONF0 0x40C0
+#define GP_INTD_DSI_TE1_GPIONC_12_PAD 0x40C8
+#define HV_DDI2_DDC_SDA_GPIONC_13_PCONF0 0x41A0
+#define HV_DDI2_DDC_SDA_GPIONC_13_PAD 0x41A8
+#define HV_DDI2_DDC_SCL_GPIONC_14_PCONF0 0x41B0
+#define HV_DDI2_DDC_SCL_GPIONC_14_PAD 0x41B8
+#define GP_CAMERASB00_GPIONC_15_PCONF0 0x4010
+#define GP_CAMERASB00_GPIONC_15_PAD 0x4018
+#define GP_CAMERASB01_GPIONC_16_PCONF0 0x4040
+#define GP_CAMERASB01_GPIONC_16_PAD 0x4048
+#define GP_CAMERASB02_GPIONC_17_PCONF0 0x4080
+#define GP_CAMERASB02_GPIONC_17_PAD 0x4088
+#define GP_CAMERASB03_GPIONC_18_PCONF0 0x40B0
+#define GP_CAMERASB03_GPIONC_18_PAD 0x40B8
+#define GP_CAMERASB04_GPIONC_19_PCONF0 0x4000
+#define GP_CAMERASB04_GPIONC_19_PAD 0x4008
+#define GP_CAMERASB05_GPIONC_20_PCONF0 0x4030
+#define GP_CAMERASB05_GPIONC_20_PAD 0x4038
+#define GP_CAMERASB06_GPIONC_21_PCONF0 0x4060
+#define GP_CAMERASB06_GPIONC_21_PAD 0x4068
+#define GP_CAMERASB07_GPIONC_22_PCONF0 0x40A0
+#define GP_CAMERASB07_GPIONC_22_PAD 0x40A8
+#define GP_CAMERASB08_GPIONC_23_PCONF0 0x40D0
+#define GP_CAMERASB08_GPIONC_23_PAD 0x40D8
+#define GP_CAMERASB09_GPIONC_24_PCONF0 0x4020
+#define GP_CAMERASB09_GPIONC_24_PAD 0x4028
+#define GP_CAMERASB10_GPIONC_25_PCONF0 0x4050
+#define GP_CAMERASB10_GPIONC_25_PAD 0x4058
+#define GP_CAMERASB11_GPIONC_26_PCONF0 0x4090
+#define GP_CAMERASB11_GPIONC_26_PAD 0x4098
+
+#define SATA_GP0_GPIOC_0_PCONF0 0x4550
+#define SATA_GP0_GPIOC_0_PAD 0x4558
+#define SATA_GP1_GPIOC_1_PCONF0 0x4590
+#define SATA_GP1_GPIOC_1_PAD 0x4598
+#define SATA_LEDN_GPIOC_2_PCONF0 0x45D0
+#define SATA_LEDN_GPIOC_2_PAD 0x45D8
+#define PCIE_CLKREQ0B_GPIOC_3_PCONF0 0x4600
+#define PCIE_CLKREQ0B_GPIOC_3_PAD 0x4608
+#define PCIE_CLKREQ1B_GPIOC_4_PCONF0 0x4630
+#define PCIE_CLKREQ1B_GPIOC_4_PAD 0x4638
+#define PCIE_CLKREQ2B_GPIOC_5_PCONF0 0x4660
+#define PCIE_CLKREQ2B_GPIOC_5_PAD 0x4668
+#define PCIE_CLKREQ3B_GPIOC_6_PCONF0 0x4620
+#define PCIE_CLKREQ3B_GPIOC_6_PAD 0x4628
+#define PCIE_CLKREQ4B_GPIOC_7_PCONF0 0x4650
+#define PCIE_CLKREQ4B_GPIOC_7_PAD 0x4658
+#define HDA_RSTB_GPIOC_8_PCONF0 0x4220
+#define HDA_RSTB_GPIOC_8_PAD 0x4228
+#define HDA_SYNC_GPIOC_9_PCONF0 0x4250
+#define HDA_SYNC_GPIOC_9_PAD 0x4258
+#define HDA_CLK_GPIOC_10_PCONF0 0x4240
+#define HDA_CLK_GPIOC_10_PAD 0x4248
+#define HDA_SDO_GPIOC_11_PCONF0 0x4260
+#define HDA_SDO_GPIOC_11_PAD 0x4268
+#define HDA_SDI0_GPIOC_12_PCONF0 0x4270
+#define HDA_SDI0_GPIOC_12_PAD 0x4278
+#define HDA_SDI1_GPIOC_13_PCONF0 0x4230
+#define HDA_SDI1_GPIOC_13_PAD 0x4238
+#define HDA_DOCKRSTB_GPIOC_14_PCONF0 0x4280
+#define HDA_DOCKRSTB_GPIOC_14_PAD 0x4288
+#define HDA_DOCKENB_GPIOC_15_PCONF0 0x4540
+#define HDA_DOCKENB_GPIOC_15_PAD 0x4548
+#define SDMMC1_CLK_GPIOC_16_PCONF0 0x43E0
+#define SDMMC1_CLK_GPIOC_16_PAD 0x43E8
+#define SDMMC1_D0_GPIOC_17_PCONF0 0x43D0
+#define SDMMC1_D0_GPIOC_17_PAD 0x43D8
+#define SDMMC1_D1_GPIOC_18_PCONF0 0x4400
+#define SDMMC1_D1_GPIOC_18_PAD 0x4408
+#define SDMMC1_D2_GPIOC_19_PCONF0 0x43B0
+#define SDMMC1_D2_GPIOC_19_PAD 0x43B8
+#define SDMMC1_D3_CD_B_GPIOC_20_PCONF0 0x4360
+#define SDMMC1_D3_CD_B_GPIOC_20_PAD 0x4368
+#define MMC1_D4_SD_WE_GPIOC_21_PCONF0 0x4380
+#define MMC1_D4_SD_WE_GPIOC_21_PAD 0x4388
+#define MMC1_D5_GPIOC_22_PCONF0 0x43C0
+#define MMC1_D5_GPIOC_22_PAD 0x43C8
+#define MMC1_D6_GPIOC_23_PCONF0 0x4370
+#define MMC1_D6_GPIOC_23_PAD 0x4378
+#define MMC1_D7_GPIOC_24_PCONF0 0x43F0
+#define MMC1_D7_GPIOC_24_PAD 0x43F8
+#define SDMMC1_CMD_GPIOC_25_PCONF0 0x4390
+#define SDMMC1_CMD_GPIOC_25_PAD 0x4398
+#define MMC1_RESET_B_GPIOC_26_PCONF0 0x4330
+#define MMC1_RESET_B_GPIOC_26_PAD 0x4338
+#define SDMMC2_CLK_GPIOC_27_PCONF0 0x4320
+#define SDMMC2_CLK_GPIOC_27_PAD 0x4328
+#define SDMMC2_D0_GPIOC_28_PCONF0 0x4350
+#define SDMMC2_D0_GPIOC_28_PAD 0x4358
+#define SDMMC2_D1_GPIOC_29_PCONF0 0x42F0
+#define SDMMC2_D1_GPIOC_29_PAD 0x42F8
+#define SDMMC2_D2_GPIOC_30_PCONF0 0x4340
+#define SDMMC2_D2_GPIOC_30_PAD 0x4348
+#define SDMMC2_D3_CD_B_GPIOC_31_PCONF0 0x4310
+#define SDMMC2_D3_CD_B_GPIOC_31_PAD 0x4318
+#define SDMMC2_CMD_GPIOC_32_PCONF0 0x4300
+#define SDMMC2_CMD_GPIOC_32_PAD 0x4308
+#define SDMMC3_CLK_GPIOC_33_PCONF0 0x42B0
+#define SDMMC3_CLK_GPIOC_33_PAD 0x42B8
+#define SDMMC3_D0_GPIOC_34_PCONF0 0x42E0
+#define SDMMC3_D0_GPIOC_34_PAD 0x42E8
+#define SDMMC3_D1_GPIOC_35_PCONF0 0x4290
+#define SDMMC3_D1_GPIOC_35_PAD 0x4298
+#define SDMMC3_D2_GPIOC_36_PCONF0 0x42D0
+#define SDMMC3_D2_GPIOC_36_PAD 0x42D8
+#define SDMMC3_D3_GPIOC_37_PCONF0 0x42A0
+#define SDMMC3_D3_GPIOC_37_PAD 0x42A8
+#define SDMMC3_CD_B_GPIOC_38_PCONF0 0x43A0
+#define SDMMC3_CD_B_GPIOC_38_PAD 0x43A8
+#define SDMMC3_CMD_GPIOC_39_PCONF0 0x42C0
+#define SDMMC3_CMD_GPIOC_39_PAD 0x42C8
+#define SDMMC3_1P8_EN_GPIOC_40_PCONF0 0x45F0
+#define SDMMC3_1P8_EN_GPIOC_40_PAD 0x45F8
+#define SDMMC3_PWR_EN_B_GPIOC_41_PCONF0 0x4690
+#define SDMMC3_PWR_EN_B_GPIOC_41_PAD 0x4698
+#define LPC_AD0_GPIOC_42_PCONF0 0x4460
+#define LPC_AD0_GPIOC_42_PAD 0x4468
+#define LPC_AD1_GPIOC_43_PCONF0 0x4440
+#define LPC_AD1_GPIOC_43_PAD 0x4448
+#define LPC_AD2_GPIOC_44_PCONF0 0x4430
+#define LPC_AD2_GPIOC_44_PAD 0x4438
+#define LPC_AD3_GPIOC_45_PCONF0 0x4420
+#define LPC_AD3_GPIOC_45_PAD 0x4428
+#define LPC_FRAMEB_GPIOC_46_PCONF0 0x4450
+#define LPC_FRAMEB_GPIOC_46_PAD 0x4458
+#define LPC_CLKOUT0_GPIOC_47_PCONF0 0x4470
+#define LPC_CLKOUT0_GPIOC_47_PAD 0x4478
+#define LPC_CLKOUT1_GPIOC_48_PCONF0 0x4410
+#define LPC_CLKOUT1_GPIOC_48_PAD 0x4418
+#define LPC_CLKRUNB_GPIOC_49_PCONF0 0x4480
+#define LPC_CLKRUNB_GPIOC_49_PAD 0x4488
+#define ILB_SERIRQ_GPIOC_50_PCONF0 0x4560
+#define ILB_SERIRQ_GPIOC_50_PAD 0x4568
+#define SMB_DATA_GPIOC_51_PCONF0 0x45A0
+#define SMB_DATA_GPIOC_51_PAD 0x45A8
+#define SMB_CLK_GPIOC_52_PCONF0 0x4580
+#define SMB_CLK_GPIOC_52_PAD 0x4588
+#define SMB_ALERTB_GPIOC_53_PCONF0 0x45C0
+#define SMB_ALERTB_GPIOC_53_PAD 0x45C8
+#define SPKR_GPIOC_54_PCONF0 0x4670
+#define SPKR_GPIOC_54_PAD 0x4678
+#define MHSI_ACDATA_GPIOC_55_PCONF0 0x44D0
+#define MHSI_ACDATA_GPIOC_55_PAD 0x44D8
+#define MHSI_ACFLAG_GPIOC_56_PCONF0 0x44F0
+#define MHSI_ACFLAG_GPIOC_56_PAD 0x44F8
+#define MHSI_ACREADY_GPIOC_57_PCONF0 0x4530
+#define MHSI_ACREADY_GPIOC_57_PAD 0x4538
+#define MHSI_ACWAKE_GPIOC_58_PCONF0 0x44E0
+#define MHSI_ACWAKE_GPIOC_58_PAD 0x44E8
+#define MHSI_CADATA_GPIOC_59_PCONF0 0x4510
+#define MHSI_CADATA_GPIOC_59_PAD 0x4518
+#define MHSI_CAFLAG_GPIOC_60_PCONF0 0x4500
+#define MHSI_CAFLAG_GPIOC_60_PAD 0x4508
+#define MHSI_CAREADY_GPIOC_61_PCONF0 0x4520
+#define MHSI_CAREADY_GPIOC_61_PAD 0x4528
+#define GP_SSP_2_CLK_GPIOC_62_PCONF0 0x40D0
+#define GP_SSP_2_CLK_GPIOC_62_PAD 0x40D8
+#define GP_SSP_2_FS_GPIOC_63_PCONF0 0x40C0
+#define GP_SSP_2_FS_GPIOC_63_PAD 0x40C8
+#define GP_SSP_2_RXD_GPIOC_64_PCONF0 0x40F0
+#define GP_SSP_2_RXD_GPIOC_64_PAD 0x40F8
+#define GP_SSP_2_TXD_GPIOC_65_PCONF0 0x40E0
+#define GP_SSP_2_TXD_GPIOC_65_PAD 0x40E8
+#define SPI1_CS0_B_GPIOC_66_PCONF0 0x4110
+#define SPI1_CS0_B_GPIOC_66_PAD 0x4118
+#define SPI1_MISO_GPIOC_67_PCONF0 0x4120
+#define SPI1_MISO_GPIOC_67_PAD 0x4128
+#define SPI1_MOSI_GPIOC_68_PCONF0 0x4130
+#define SPI1_MOSI_GPIOC_68_PAD 0x4138
+#define SPI1_CLK_GPIOC_69_PCONF0 0x4100
+#define SPI1_CLK_GPIOC_69_PAD 0x4108
+#define UART1_RXD_GPIOC_70_PCONF0 0x4020
+#define UART1_RXD_GPIOC_70_PAD 0x4028
+#define UART1_TXD_GPIOC_71_PCONF0 0x4010
+#define UART1_TXD_GPIOC_71_PAD 0x4018
+#define UART1_RTS_B_GPIOC_72_PCONF0 0x4000
+#define UART1_RTS_B_GPIOC_72_PAD 0x4008
+#define UART1_CTS_B_GPIOC_73_PCONF0 0x4040
+#define UART1_CTS_B_GPIOC_73_PAD 0x4048
+#define UART2_RXD_GPIOC_74_PCONF0 0x4060
+#define UART2_RXD_GPIOC_74_PAD 0x4068
+#define UART2_TXD_GPIOC_75_PCONF0 0x4070
+#define UART2_TXD_GPIOC_75_PAD 0x4078
+#define UART2_RTS_B_GPIOC_76_PCONF0 0x4090
+#define UART2_RTS_B_GPIOC_76_PAD 0x4098
+#define UART2_CTS_B_GPIOC_77_PCONF0 0x4080
+#define UART2_CTS_B_GPIOC_77_PAD 0x4088
+#define I2C0_SDA_GPIOC_78_PCONF0 0x4210
+#define I2C0_SDA_GPIOC_78_PAD 0x4218
+#define I2C0_SCL_GPIOC_79_PCONF0 0x4200
+#define I2C0_SCL_GPIOC_79_PAD 0x4208
+#define I2C1_SDA_GPIOC_80_PCONF0 0x41F0
+#define I2C1_SDA_GPIOC_80_PAD 0x41F8
+#define I2C1_SCL_GPIOC_81_PCONF0 0x41E0
+#define I2C1_SCL_GPIOC_81_PAD 0x41E8
+#define I2C2_SDA_GPIOC_82_PCONF0 0x41D0
+#define I2C2_SDA_GPIOC_82_PAD 0x41D8
+#define I2C2_SCL_GPIOC_83_PCONF0 0x41B0
+#define I2C2_SCL_GPIOC_83_PAD 0x41B8
+#define I2C3_SDA_GPIOC_84_PCONF0 0x4190
+#define I2C2_SCL_GPIOC_83_PAD 0x41B8
+#define I2C3_SDA_GPIOC_84_PCONF0 0x4190
+#define I2C3_SDA_GPIOC_84_PAD 0x4198
+#define I2C3_SCL_GPIOC_85_PCONF0 0x41C0
+#define I2C3_SCL_GPIOC_85_PAD 0x41C8
+#define I2C4_SDA_GPIOC_86_PCONF0 0x41A0
+#define I2C4_SDA_GPIOC_86_PAD 0x41A8
+#define I2C4_SCL_GPIOC_87_PCONF0 0x4170
+#define I2C4_SCL_GPIOC_87_PAD 0x4178
+#define I2C5_SDA_GPIOC_88_PCONF0 0x4150
+#define I2C5_SDA_GPIOC_88_PAD 0x4158
+#define I2C5_SCL_GPIOC_89_PCONF0 0x4140
+#define I2C5_SCL_GPIOC_89_PAD 0x4148
+#define I2C6_SDA_GPIOC_90_PCONF0 0x4180
+#define I2C6_SDA_GPIOC_90_PAD 0x4188
+#define I2C6_SCL_GPIOC_91_PCONF0 0x4160
+#define I2C6_SCL_GPIOC_91_PAD 0x4168
+#define I2C_NFC_SDA_GPIOC_92_PCONF0 0x4050
+#define I2C_NFC_SDA_GPIOC_92_PAD 0x4058
+#define I2C_NFC_SCL_GPIOC_93_PCONF0 0x4030
+#define I2C_NFC_SCL_GPIOC_93_PAD 0x4038
+#define PWM0_GPIOC_94_PCONF0 0x40A0
+#define PWM0_GPIOC_94_PAD 0x40A8
+#define PWM1_GPIOC_95_PCONF0 0x40B0
+#define PWM1_GPIOC_95_PAD 0x40B8
+#define PLT_CLK0_GPIOC_96_PCONF0 0x46A0
+#define PLT_CLK0_GPIOC_96_PAD 0x46A8
+#define PLT_CLK1_GPIOC_97_PCONF0 0x4570
+#define PLT_CLK1_GPIOC_97_PAD 0x4578
+#define PLT_CLK2_GPIOC_98_PCONF0 0x45B0
+#define PLT_CLK2_GPIOC_98_PAD 0x45B8
+#define PLT_CLK3_GPIOC_99_PCONF0 0x4680
+#define PLT_CLK3_GPIOC_99_PAD 0x4688
+#define PLT_CLK4_GPIOC_100_PCONF0 0x4610
+#define PLT_CLK4_GPIOC_100_PAD 0x4618
+#define PLT_CLK5_GPIOC_101_PCONF0 0x4640
+#define PLT_CLK5_GPIOC_101_PAD 0x4648
+
+#define GPIO_SUS0_GPIO_SUS0_PCONF0 0x41D0
+#define GPIO_SUS0_GPIO_SUS0_PAD 0x41D8
+#define GPIO_SUS1_GPIO_SUS1_PCONF0 0x4210
+#define GPIO_SUS1_GPIO_SUS1_PAD 0x4218
+#define GPIO_SUS2_GPIO_SUS2_PCONF0 0x41E0
+#define GPIO_SUS2_GPIO_SUS2_PAD 0x41E8
+#define GPIO_SUS3_GPIO_SUS3_PCONF0 0x41F0
+#define GPIO_SUS3_GPIO_SUS3_PAD 0x41F8
+#define GPIO_SUS4_GPIO_SUS4_PCONF0 0x4200
+#define GPIO_SUS4_GPIO_SUS4_PAD 0x4208
+#define GPIO_SUS5_GPIO_SUS5_PCONF0 0x4220
+#define GPIO_SUS5_GPIO_SUS5_PAD 0x4228
+#define GPIO_SUS6_GPIO_SUS6_PCONF0 0x4240
+#define GPIO_SUS6_GPIO_SUS6_PAD 0x4248
+#define GPIO_SUS7_GPIO_SUS7_PCONF0 0x4230
+#define GPIO_SUS7_GPIO_SUS7_PAD 0x4238
+#define SEC_GPIO_SUS8_GPIO_SUS8_PCONF0 0x4260
+#define SEC_GPIO_SUS8_GPIO_SUS8_PAD 0x4268
+#define SEC_GPIO_SUS9_GPIO_SUS9_PCONF0 0x4250
+#define SEC_GPIO_SUS9_GPIO_SUS9_PAD 0x4258
+#define SEC_GPIO_SUS10_GPIO_SUS10_PCONF0 0x4120
+#define SEC_GPIO_SUS10_GPIO_SUS10_PAD 0x4128
+#define SUSPWRDNACK_GPIOS_11_PCONF0 0x4070
+#define SUSPWRDNACK_GPIOS_11_PAD 0x4078
+#define PMU_SUSCLK_GPIOS_12_PCONF0 0x40B0
+#define PMU_SUSCLK_GPIOS_12_PAD 0x40B8
+#define PMU_SLP_S0IX_B_GPIOS_13_PCONF0 0x4140
+#define PMU_SLP_S0IX_B_GPIOS_13_PAD 0x4148
+#define PMU_SLP_LAN_B_GPIOS_14_PCONF0 0x4110
+#define PMU_SLP_LAN_B_GPIOS_14_PAD 0x4118
+#define PMU_WAKE_B_GPIOS_15_PCONF0 0x4010
+#define PMU_WAKE_B_GPIOS_15_PAD 0x4018
+#define PMU_PWRBTN_B_GPIOS_16_PCONF0 0x4080
+#define PMU_PWRBTN_B_GPIOS_16_PAD 0x4088
+#define PMU_WAKE_LAN_B_GPIOS_17_PCONF0 0x40A0
+#define PMU_WAKE_LAN_B_GPIOS_17_PAD 0x40A8
+#define SUS_STAT_B_GPIOS_18_PCONF0 0x4130
+#define SUS_STAT_B_GPIOS_18_PAD 0x4138
+#define USB_OC0_B_GPIOS_19_PCONF0 0x40C0
+#define USB_OC0_B_GPIOS_19_PAD 0x40C8
+#define USB_OC1_B_GPIOS_20_PCONF0 0x4000
+#define USB_OC1_B_GPIOS_20_PAD 0x4008
+#define SPI_CS1_B_GPIOS_21_PCONF0 0x4020
+#define SPI_CS1_B_GPIOS_21_PAD 0x4028
+#define GPIO_DFX0_GPIOS_22_PCONF0 0x4170
+#define GPIO_DFX0_GPIOS_22_PAD 0x4178
+#define GPIO_DFX1_GPIOS_23_PCONF0 0x4270
+#define GPIO_DFX1_GPIOS_23_PAD 0x4278
+#define GPIO_DFX2_GPIOS_24_PCONF0 0x41C0
+#define GPIO_DFX2_GPIOS_24_PAD 0x41C8
+#define GPIO_DFX3_GPIOS_25_PCONF0 0x41B0
+#define GPIO_DFX3_GPIOS_25_PAD 0x41B8
+#define GPIO_DFX4_GPIOS_26_PCONF0 0x4160
+#define GPIO_DFX4_GPIOS_26_PAD 0x4168
+#define GPIO_DFX5_GPIOS_27_PCONF0 0x4150
+#define GPIO_DFX5_GPIOS_27_PAD 0x4158
+#define GPIO_DFX6_GPIOS_28_PCONF0 0x4180
+#define GPIO_DFX6_GPIOS_28_PAD 0x4188
+#define GPIO_DFX7_GPIOS_29_PCONF0 0x4190
+#define GPIO_DFX7_GPIOS_29_PAD 0x4198
+#define GPIO_DFX8_GPIOS_30_PCONF0 0x41A0
+#define GPIO_DFX8_GPIOS_30_PAD 0x41A8
+#define USB_ULPI_0_CLK_GPIOS_31_PCONF0 0x4330
+#define USB_ULPI_0_CLK_GPIOS_31_PAD 0x4338
+#define USB_ULPI_0_DATA0_GPIOS_32_PCONF0 0x4380
+#define USB_ULPI_0_DATA0_GPIOS_32_PAD 0x4388
+#define USB_ULPI_0_DATA1_GPIOS_33_PCONF0 0x4360
+#define USB_ULPI_0_DATA1_GPIOS_33_PAD 0x4368
+#define USB_ULPI_0_DATA2_GPIOS_34_PCONF0 0x4310
+#define USB_ULPI_0_DATA2_GPIOS_34_PAD 0x4318
+#define USB_ULPI_0_DATA3_GPIOS_35_PCONF0 0x4370
+#define USB_ULPI_0_DATA3_GPIOS_35_PAD 0x4378
+#define USB_ULPI_0_DATA4_GPIOS_36_PCONF0 0x4300
+#define USB_ULPI_0_DATA4_GPIOS_36_PAD 0x4308
+#define USB_ULPI_0_DATA5_GPIOS_37_PCONF0 0x4390
+#define USB_ULPI_0_DATA5_GPIOS_37_PAD 0x4398
+#define USB_ULPI_0_DATA6_GPIOS_38_PCONF0 0x4320
+#define USB_ULPI_0_DATA6_GPIOS_38_PAD 0x4328
+#define USB_ULPI_0_DATA7_GPIOS_39_PCONF0 0x43A0
+#define USB_ULPI_0_DATA7_GPIOS_39_PAD 0x43A8
+#define USB_ULPI_0_DIR_GPIOS_40_PCONF0 0x4340
+#define USB_ULPI_0_DIR_GPIOS_40_PAD 0x4348
+#define USB_ULPI_0_NXT_GPIOS_41_PCONF0 0x4350
+#define USB_ULPI_0_NXT_GPIOS_41_PAD 0x4358
+#define USB_ULPI_0_STP_GPIOS_42_PCONF0 0x43B0
+#define USB_ULPI_0_STP_GPIOS_42_PAD 0x43B8
+#define USB_ULPI_0_REFCLK_GPIOS_43_PCONF0 0x4280
+#define USB_ULPI_0_REFCLK_GPIOS_43_PAD 0x4288
struct gpio_table {
u16 function_reg;
@@ -91,18 +421,181 @@ struct gpio_table {
};
static struct gpio_table gtable[] = {
- { GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 },
- { GPIO_NC_1_HV_DDI0_DDC_SDA, GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 },
- { GPIO_NC_2_HV_DDI0_DDC_SCL, GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 },
- { GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD, 0 },
- { GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0 },
- { GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0 },
- { GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 },
- { GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 },
- { GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 },
- { GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 },
- { GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0},
- { GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
+ { HV_DDI0_HPD_GPIONC_0_PCONF0, HV_DDI0_HPD_GPIONC_0_PAD, 0},
+ { HV_DDI0_DDC_SDA_GPIONC_1_PCONF0, HV_DDI0_DDC_SDA_GPIONC_1_PAD, 0},
+ { HV_DDI0_DDC_SCL_GPIONC_2_PCONF0, HV_DDI0_DDC_SCL_GPIONC_2_PAD, 0},
+ { PANEL0_VDDEN_GPIONC_3_PCONF0, PANEL0_VDDEN_GPIONC_3_PAD, 0},
+ { PANEL0_BKLTEN_GPIONC_4_PCONF0, PANEL0_BKLTEN_GPIONC_4_PAD, 0},
+ { PANEL0_BKLTCTL_GPIONC_5_PCONF0, PANEL0_BKLTCTL_GPIONC_5_PAD, 0},
+ { HV_DDI1_HPD_GPIONC_6_PCONF0, HV_DDI1_HPD_GPIONC_6_PAD, 0},
+ { HV_DDI1_DDC_SDA_GPIONC_7_PCONF0, HV_DDI1_DDC_SDA_GPIONC_7_PAD, 0},
+ { HV_DDI1_DDC_SCL_GPIONC_8_PCONF0, HV_DDI1_DDC_SCL_GPIONC_8_PAD, 0},
+ { PANEL1_VDDEN_GPIONC_9_PCONF0, PANEL1_VDDEN_GPIONC_9_PAD, 0},
+ { PANEL1_BKLTEN_GPIONC_10_PCONF0, PANEL1_BKLTEN_GPIONC_10_PAD, 0},
+ { PANEL1_BKLTCTL_GPIONC_11_PCONF0, PANEL1_BKLTCTL_GPIONC_11_PAD, 0},
+ { GP_INTD_DSI_TE1_GPIONC_12_PCONF0, GP_INTD_DSI_TE1_GPIONC_12_PAD, 0},
+ { HV_DDI2_DDC_SDA_GPIONC_13_PCONF0, HV_DDI2_DDC_SDA_GPIONC_13_PAD, 0},
+ { HV_DDI2_DDC_SCL_GPIONC_14_PCONF0, HV_DDI2_DDC_SCL_GPIONC_14_PAD, 0},
+ { GP_CAMERASB00_GPIONC_15_PCONF0, GP_CAMERASB00_GPIONC_15_PAD, 0},
+ { GP_CAMERASB01_GPIONC_16_PCONF0, GP_CAMERASB01_GPIONC_16_PAD, 0},
+ { GP_CAMERASB02_GPIONC_17_PCONF0, GP_CAMERASB02_GPIONC_17_PAD, 0},
+ { GP_CAMERASB03_GPIONC_18_PCONF0, GP_CAMERASB03_GPIONC_18_PAD, 0},
+ { GP_CAMERASB04_GPIONC_19_PCONF0, GP_CAMERASB04_GPIONC_19_PAD, 0},
+ { GP_CAMERASB05_GPIONC_20_PCONF0, GP_CAMERASB05_GPIONC_20_PAD, 0},
+ { GP_CAMERASB06_GPIONC_21_PCONF0, GP_CAMERASB06_GPIONC_21_PAD, 0},
+ { GP_CAMERASB07_GPIONC_22_PCONF0, GP_CAMERASB07_GPIONC_22_PAD, 0},
+ { GP_CAMERASB08_GPIONC_23_PCONF0, GP_CAMERASB08_GPIONC_23_PAD, 0},
+ { GP_CAMERASB09_GPIONC_24_PCONF0, GP_CAMERASB09_GPIONC_24_PAD, 0},
+ { GP_CAMERASB10_GPIONC_25_PCONF0, GP_CAMERASB10_GPIONC_25_PAD, 0},
+ { GP_CAMERASB11_GPIONC_26_PCONF0, GP_CAMERASB11_GPIONC_26_PAD, 0},
+
+ { SATA_GP0_GPIOC_0_PCONF0, SATA_GP0_GPIOC_0_PAD, 0},
+ { SATA_GP1_GPIOC_1_PCONF0, SATA_GP1_GPIOC_1_PAD, 0},
+ { SATA_LEDN_GPIOC_2_PCONF0, SATA_LEDN_GPIOC_2_PAD, 0},
+ { PCIE_CLKREQ0B_GPIOC_3_PCONF0, PCIE_CLKREQ0B_GPIOC_3_PAD, 0},
+ { PCIE_CLKREQ1B_GPIOC_4_PCONF0, PCIE_CLKREQ1B_GPIOC_4_PAD, 0},
+ { PCIE_CLKREQ2B_GPIOC_5_PCONF0, PCIE_CLKREQ2B_GPIOC_5_PAD, 0},
+ { PCIE_CLKREQ3B_GPIOC_6_PCONF0, PCIE_CLKREQ3B_GPIOC_6_PAD, 0},
+ { PCIE_CLKREQ4B_GPIOC_7_PCONF0, PCIE_CLKREQ4B_GPIOC_7_PAD, 0},
+ { HDA_RSTB_GPIOC_8_PCONF0, HDA_RSTB_GPIOC_8_PAD, 0},
+ { HDA_SYNC_GPIOC_9_PCONF0, HDA_SYNC_GPIOC_9_PAD, 0},
+ { HDA_CLK_GPIOC_10_PCONF0, HDA_CLK_GPIOC_10_PAD, 0},
+ { HDA_SDO_GPIOC_11_PCONF0, HDA_SDO_GPIOC_11_PAD, 0},
+ { HDA_SDI0_GPIOC_12_PCONF0, HDA_SDI0_GPIOC_12_PAD, 0},
+ { HDA_SDI1_GPIOC_13_PCONF0, HDA_SDI1_GPIOC_13_PAD, 0},
+ { HDA_DOCKRSTB_GPIOC_14_PCONF0, HDA_DOCKRSTB_GPIOC_14_PAD, 0},
+ { HDA_DOCKENB_GPIOC_15_PCONF0, HDA_DOCKENB_GPIOC_15_PAD, 0},
+ { SDMMC1_CLK_GPIOC_16_PCONF0, SDMMC1_CLK_GPIOC_16_PAD, 0},
+ { SDMMC1_D0_GPIOC_17_PCONF0, SDMMC1_D0_GPIOC_17_PAD, 0},
+ { SDMMC1_D1_GPIOC_18_PCONF0, SDMMC1_D1_GPIOC_18_PAD, 0},
+ { SDMMC1_D2_GPIOC_19_PCONF0, SDMMC1_D2_GPIOC_19_PAD, 0},
+ { SDMMC1_D3_CD_B_GPIOC_20_PCONF0, SDMMC1_D3_CD_B_GPIOC_20_PAD, 0},
+ { MMC1_D4_SD_WE_GPIOC_21_PCONF0, MMC1_D4_SD_WE_GPIOC_21_PAD, 0},
+ { MMC1_D5_GPIOC_22_PCONF0, MMC1_D5_GPIOC_22_PAD, 0},
+ { MMC1_D6_GPIOC_23_PCONF0, MMC1_D6_GPIOC_23_PAD, 0},
+ { MMC1_D7_GPIOC_24_PCONF0, MMC1_D7_GPIOC_24_PAD, 0},
+ { SDMMC1_CMD_GPIOC_25_PCONF0, SDMMC1_CMD_GPIOC_25_PAD, 0},
+ { MMC1_RESET_B_GPIOC_26_PCONF0, MMC1_RESET_B_GPIOC_26_PAD, 0},
+ { SDMMC2_CLK_GPIOC_27_PCONF0, SDMMC2_CLK_GPIOC_27_PAD, 0},
+ { SDMMC2_D0_GPIOC_28_PCONF0, SDMMC2_D0_GPIOC_28_PAD, 0},
+ { SDMMC2_D1_GPIOC_29_PCONF0, SDMMC2_D1_GPIOC_29_PAD, 0},
+ { SDMMC2_D2_GPIOC_30_PCONF0, SDMMC2_D2_GPIOC_30_PAD, 0},
+ { SDMMC2_D3_CD_B_GPIOC_31_PCONF0, SDMMC2_D3_CD_B_GPIOC_31_PAD, 0},
+ { SDMMC2_CMD_GPIOC_32_PCONF0, SDMMC2_CMD_GPIOC_32_PAD, 0},
+ { SDMMC3_CLK_GPIOC_33_PCONF0, SDMMC3_CLK_GPIOC_33_PAD, 0},
+ { SDMMC3_D0_GPIOC_34_PCONF0, SDMMC3_D0_GPIOC_34_PAD, 0},
+ { SDMMC3_D1_GPIOC_35_PCONF0, SDMMC3_D1_GPIOC_35_PAD, 0},
+ { SDMMC3_D2_GPIOC_36_PCONF0, SDMMC3_D2_GPIOC_36_PAD, 0},
+ { SDMMC3_D3_GPIOC_37_PCONF0, SDMMC3_D3_GPIOC_37_PAD, 0},
+ { SDMMC3_CD_B_GPIOC_38_PCONF0, SDMMC3_CD_B_GPIOC_38_PAD, 0},
+ { SDMMC3_CMD_GPIOC_39_PCONF0, SDMMC3_CMD_GPIOC_39_PAD, 0},
+ { SDMMC3_1P8_EN_GPIOC_40_PCONF0, SDMMC3_1P8_EN_GPIOC_40_PAD, 0},
+ { SDMMC3_PWR_EN_B_GPIOC_41_PCONF0, SDMMC3_PWR_EN_B_GPIOC_41_PAD, 0},
+ { LPC_AD0_GPIOC_42_PCONF0, LPC_AD0_GPIOC_42_PAD, 0},
+ { LPC_AD1_GPIOC_43_PCONF0, LPC_AD1_GPIOC_43_PAD, 0},
+ { LPC_AD2_GPIOC_44_PCONF0, LPC_AD2_GPIOC_44_PAD, 0},
+ { LPC_AD3_GPIOC_45_PCONF0, LPC_AD3_GPIOC_45_PAD, 0},
+ { LPC_FRAMEB_GPIOC_46_PCONF0, LPC_FRAMEB_GPIOC_46_PAD, 0},
+ { LPC_CLKOUT0_GPIOC_47_PCONF0, LPC_CLKOUT0_GPIOC_47_PAD, 0},
+ { LPC_CLKOUT1_GPIOC_48_PCONF0, LPC_CLKOUT1_GPIOC_48_PAD, 0},
+ { LPC_CLKRUNB_GPIOC_49_PCONF0, LPC_CLKRUNB_GPIOC_49_PAD, 0},
+ { ILB_SERIRQ_GPIOC_50_PCONF0, ILB_SERIRQ_GPIOC_50_PAD, 0},
+ { SMB_DATA_GPIOC_51_PCONF0, SMB_DATA_GPIOC_51_PAD, 0},
+ { SMB_CLK_GPIOC_52_PCONF0, SMB_CLK_GPIOC_52_PAD, 0},
+ { SMB_ALERTB_GPIOC_53_PCONF0, SMB_ALERTB_GPIOC_53_PAD, 0},
+ { SPKR_GPIOC_54_PCONF0, SPKR_GPIOC_54_PAD, 0},
+ { MHSI_ACDATA_GPIOC_55_PCONF0, MHSI_ACDATA_GPIOC_55_PAD, 0},
+ { MHSI_ACFLAG_GPIOC_56_PCONF0, MHSI_ACFLAG_GPIOC_56_PAD, 0},
+ { MHSI_ACREADY_GPIOC_57_PCONF0, MHSI_ACREADY_GPIOC_57_PAD, 0},
+ { MHSI_ACWAKE_GPIOC_58_PCONF0, MHSI_ACWAKE_GPIOC_58_PAD, 0},
+ { MHSI_CADATA_GPIOC_59_PCONF0, MHSI_CADATA_GPIOC_59_PAD, 0},
+ { MHSI_CAFLAG_GPIOC_60_PCONF0, MHSI_CAFLAG_GPIOC_60_PAD, 0},
+ { MHSI_CAREADY_GPIOC_61_PCONF0, MHSI_CAREADY_GPIOC_61_PAD, 0},
+ { GP_SSP_2_CLK_GPIOC_62_PCONF0, GP_SSP_2_CLK_GPIOC_62_PAD, 0},
+ { GP_SSP_2_FS_GPIOC_63_PCONF0, GP_SSP_2_FS_GPIOC_63_PAD, 0},
+ { GP_SSP_2_RXD_GPIOC_64_PCONF0, GP_SSP_2_RXD_GPIOC_64_PAD, 0},
+ { GP_SSP_2_TXD_GPIOC_65_PCONF0, GP_SSP_2_TXD_GPIOC_65_PAD, 0},
+ { SPI1_CS0_B_GPIOC_66_PCONF0, SPI1_CS0_B_GPIOC_66_PAD, 0},
+ { SPI1_MISO_GPIOC_67_PCONF0, SPI1_MISO_GPIOC_67_PAD, 0},
+ { SPI1_MOSI_GPIOC_68_PCONF0, SPI1_MOSI_GPIOC_68_PAD, 0},
+ { SPI1_CLK_GPIOC_69_PCONF0, SPI1_CLK_GPIOC_69_PAD, 0},
+ { UART1_RXD_GPIOC_70_PCONF0, UART1_RXD_GPIOC_70_PAD, 0},
+ { UART1_TXD_GPIOC_71_PCONF0, UART1_TXD_GPIOC_71_PAD, 0},
+ { UART1_RTS_B_GPIOC_72_PCONF0, UART1_RTS_B_GPIOC_72_PAD, 0},
+ { UART1_CTS_B_GPIOC_73_PCONF0, UART1_CTS_B_GPIOC_73_PAD, 0},
+ { UART2_RXD_GPIOC_74_PCONF0, UART2_RXD_GPIOC_74_PAD, 0},
+ { UART2_TXD_GPIOC_75_PCONF0, UART2_TXD_GPIOC_75_PAD, 0},
+ { UART2_RTS_B_GPIOC_76_PCONF0, UART2_RTS_B_GPIOC_76_PAD, 0},
+ { UART2_CTS_B_GPIOC_77_PCONF0, UART2_CTS_B_GPIOC_77_PAD, 0},
+ { I2C0_SDA_GPIOC_78_PCONF0, I2C0_SDA_GPIOC_78_PAD, 0},
+ { I2C0_SCL_GPIOC_79_PCONF0, I2C0_SCL_GPIOC_79_PAD, 0},
+ { I2C1_SDA_GPIOC_80_PCONF0, I2C1_SDA_GPIOC_80_PAD, 0},
+ { I2C1_SCL_GPIOC_81_PCONF0, I2C1_SCL_GPIOC_81_PAD, 0},
+ { I2C2_SDA_GPIOC_82_PCONF0, I2C2_SDA_GPIOC_82_PAD, 0},
+ { I2C2_SCL_GPIOC_83_PCONF0, I2C2_SCL_GPIOC_83_PAD, 0},
+ { I2C3_SDA_GPIOC_84_PCONF0, I2C3_SDA_GPIOC_84_PAD, 0},
+ { I2C3_SCL_GPIOC_85_PCONF0, I2C3_SCL_GPIOC_85_PAD, 0},
+ { I2C4_SDA_GPIOC_86_PCONF0, I2C4_SDA_GPIOC_86_PAD, 0},
+ { I2C4_SCL_GPIOC_87_PCONF0, I2C4_SCL_GPIOC_87_PAD, 0},
+ { I2C5_SDA_GPIOC_88_PCONF0, I2C5_SDA_GPIOC_88_PAD, 0},
+ { I2C5_SCL_GPIOC_89_PCONF0, I2C5_SCL_GPIOC_89_PAD, 0},
+ { I2C6_SDA_GPIOC_90_PCONF0, I2C6_SDA_GPIOC_90_PAD, 0},
+ { I2C6_SCL_GPIOC_91_PCONF0, I2C6_SCL_GPIOC_91_PAD, 0},
+ { I2C_NFC_SDA_GPIOC_92_PCONF0, I2C_NFC_SDA_GPIOC_92_PAD, 0},
+ { I2C_NFC_SCL_GPIOC_93_PCONF0, I2C_NFC_SCL_GPIOC_93_PAD, 0},
+ { PWM0_GPIOC_94_PCONF0, PWM0_GPIOC_94_PAD, 0},
+ { PWM1_GPIOC_95_PCONF0, PWM1_GPIOC_95_PAD, 0},
+ { PLT_CLK0_GPIOC_96_PCONF0, PLT_CLK0_GPIOC_96_PAD, 0},
+ { PLT_CLK1_GPIOC_97_PCONF0, PLT_CLK1_GPIOC_97_PAD, 0},
+ { PLT_CLK2_GPIOC_98_PCONF0, PLT_CLK2_GPIOC_98_PAD, 0},
+ { PLT_CLK3_GPIOC_99_PCONF0, PLT_CLK3_GPIOC_99_PAD, 0},
+ { PLT_CLK4_GPIOC_100_PCONF0, PLT_CLK4_GPIOC_100_PAD, 0},
+ { PLT_CLK5_GPIOC_101_PCONF0, PLT_CLK5_GPIOC_101_PAD, 0},
+
+ { GPIO_SUS0_GPIO_SUS0_PCONF0, GPIO_SUS0_GPIO_SUS0_PAD, 0},
+ { GPIO_SUS1_GPIO_SUS1_PCONF0, GPIO_SUS1_GPIO_SUS1_PAD, 0},
+ { GPIO_SUS2_GPIO_SUS2_PCONF0, GPIO_SUS2_GPIO_SUS2_PAD, 0},
+ { GPIO_SUS3_GPIO_SUS3_PCONF0, GPIO_SUS3_GPIO_SUS3_PAD, 0},
+ { GPIO_SUS4_GPIO_SUS4_PCONF0, GPIO_SUS4_GPIO_SUS4_PAD, 0},
+ { GPIO_SUS5_GPIO_SUS5_PCONF0, GPIO_SUS5_GPIO_SUS5_PAD, 0},
+ { GPIO_SUS6_GPIO_SUS6_PCONF0, GPIO_SUS6_GPIO_SUS6_PAD, 0},
+ { GPIO_SUS7_GPIO_SUS7_PCONF0, GPIO_SUS7_GPIO_SUS7_PAD, 0},
+ { SEC_GPIO_SUS8_GPIO_SUS8_PCONF0, SEC_GPIO_SUS8_GPIO_SUS8_PAD, 0},
+ { SEC_GPIO_SUS9_GPIO_SUS9_PCONF0, SEC_GPIO_SUS9_GPIO_SUS9_PAD, 0},
+ { SEC_GPIO_SUS10_GPIO_SUS10_PCONF0, SEC_GPIO_SUS10_GPIO_SUS10_PAD, 0},
+ { SUSPWRDNACK_GPIOS_11_PCONF0, SUSPWRDNACK_GPIOS_11_PAD, 0},
+ { PMU_SUSCLK_GPIOS_12_PCONF0, PMU_SUSCLK_GPIOS_12_PAD, 0},
+ { PMU_SLP_S0IX_B_GPIOS_13_PCONF0, PMU_SLP_S0IX_B_GPIOS_13_PAD, 0},
+ { PMU_SLP_LAN_B_GPIOS_14_PCONF0, PMU_SLP_LAN_B_GPIOS_14_PAD, 0},
+ { PMU_WAKE_B_GPIOS_15_PCONF0, PMU_WAKE_B_GPIOS_15_PAD, 0},
+ { PMU_PWRBTN_B_GPIOS_16_PCONF0, PMU_PWRBTN_B_GPIOS_16_PAD, 0},
+ { PMU_WAKE_LAN_B_GPIOS_17_PCONF0, PMU_WAKE_LAN_B_GPIOS_17_PAD, 0},
+ { SUS_STAT_B_GPIOS_18_PCONF0, SUS_STAT_B_GPIOS_18_PAD, 0},
+ { USB_OC0_B_GPIOS_19_PCONF0, USB_OC0_B_GPIOS_19_PAD, 0},
+ { USB_OC1_B_GPIOS_20_PCONF0, USB_OC1_B_GPIOS_20_PAD, 0},
+ { SPI_CS1_B_GPIOS_21_PCONF0, SPI_CS1_B_GPIOS_21_PAD, 0},
+ { GPIO_DFX0_GPIOS_22_PCONF0, GPIO_DFX0_GPIOS_22_PAD, 0},
+ { GPIO_DFX1_GPIOS_23_PCONF0, GPIO_DFX1_GPIOS_23_PAD, 0},
+ { GPIO_DFX2_GPIOS_24_PCONF0, GPIO_DFX2_GPIOS_24_PAD, 0},
+ { GPIO_DFX3_GPIOS_25_PCONF0, GPIO_DFX3_GPIOS_25_PAD, 0},
+ { GPIO_DFX4_GPIOS_26_PCONF0, GPIO_DFX4_GPIOS_26_PAD, 0},
+ { GPIO_DFX5_GPIOS_27_PCONF0, GPIO_DFX5_GPIOS_27_PAD, 0},
+ { GPIO_DFX6_GPIOS_28_PCONF0, GPIO_DFX6_GPIOS_28_PAD, 0},
+ { GPIO_DFX7_GPIOS_29_PCONF0, GPIO_DFX7_GPIOS_29_PAD, 0},
+ { GPIO_DFX8_GPIOS_30_PCONF0, GPIO_DFX8_GPIOS_30_PAD, 0},
+ { USB_ULPI_0_CLK_GPIOS_31_PCONF0, USB_ULPI_0_CLK_GPIOS_31_PAD, 0},
+ { USB_ULPI_0_DATA0_GPIOS_32_PCONF0, USB_ULPI_0_DATA0_GPIOS_32_PAD, 0},
+ { USB_ULPI_0_DATA1_GPIOS_33_PCONF0, USB_ULPI_0_DATA1_GPIOS_33_PAD, 0},
+ { USB_ULPI_0_DATA2_GPIOS_34_PCONF0, USB_ULPI_0_DATA2_GPIOS_34_PAD, 0},
+ { USB_ULPI_0_DATA3_GPIOS_35_PCONF0, USB_ULPI_0_DATA3_GPIOS_35_PAD, 0},
+ { USB_ULPI_0_DATA4_GPIOS_36_PCONF0, USB_ULPI_0_DATA4_GPIOS_36_PAD, 0},
+ { USB_ULPI_0_DATA5_GPIOS_37_PCONF0, USB_ULPI_0_DATA5_GPIOS_37_PAD, 0},
+ { USB_ULPI_0_DATA6_GPIOS_38_PCONF0, USB_ULPI_0_DATA6_GPIOS_38_PAD, 0},
+ { USB_ULPI_0_DATA7_GPIOS_39_PCONF0, USB_ULPI_0_DATA7_GPIOS_39_PAD, 0},
+ { USB_ULPI_0_DIR_GPIOS_40_PCONF0, USB_ULPI_0_DIR_GPIOS_40_PAD, 0},
+ { USB_ULPI_0_NXT_GPIOS_41_PCONF0, USB_ULPI_0_NXT_GPIOS_41_PAD, 0},
+ { USB_ULPI_0_STP_GPIOS_42_PCONF0, USB_ULPI_0_STP_GPIOS_42_PAD, 0},
+ { USB_ULPI_0_REFCLK_GPIOS_43_PCONF0, USB_ULPI_0_REFCLK_GPIOS_43_PAD, 0}
};
static inline enum port intel_dsi_seq_port_to_port(u8 port)
@@ -202,6 +695,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
u8 gpio, action;
u16 function, pad;
u32 val;
+ u8 port;
struct drm_device *dev = intel_dsi->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -224,8 +718,22 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
}
if (dev_priv->vbt.dsi.seq_version >= 3) {
- DRM_DEBUG_KMS("GPIO element v3 not supported\n");
- goto out;
+ if (gpio <= MAX_GPIO_NUM_NC) {
+ DRM_DEBUG_KMS("GPIO is in the north block\n");
+ port = IOSF_PORT_GPIO_NC;
+ } else if (gpio > MAX_GPIO_NUM_NC && gpio <= MAX_GPIO_NUM_SC) {
+ DRM_DEBUG_KMS("GPIO is in the south block\n");
+ port = IOSF_PORT_GPIO_SC;
+ } else if (gpio > MAX_GPIO_NUM_SC && gpio <= MAX_GPIO_NUM) {
+ DRM_DEBUG_KMS("GPIO is in the SUS block\n");
+ port = IOSF_PORT_GPIO_SUS;
+ } else {
+ DRM_DEBUG_KMS("GPIO %u is in unknown range\n", gpio);
+ goto out;
+ }
+ } else {
+ /* XXX: Per spec, sequence block v2 also supports SC. */
+ port = IOSF_PORT_GPIO_NC;
}
function = gtable[gpio].function_reg;
@@ -235,15 +743,14 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
if (!gtable[gpio].init) {
/* program the function */
/* FIXME: remove constant below */
- vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, function,
- 0x2000CC00);
+ vlv_iosf_sb_write(dev_priv, port, function, 0x2000CC00);
gtable[gpio].init = 1;
}
val = 0x4 | action;
/* pull up/down */
- vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, pad, val);
+ vlv_iosf_sb_write(dev_priv, port, pad, val);
mutex_unlock(&dev_priv->sb_lock);
out:
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/dsi: i2c/gpio
2016-02-04 10:50 [PATCH 0/8] drm/i915/dsi: i2c/gpio Jani Nikula
` (7 preceding siblings ...)
2016-02-04 10:50 ` [PATCH 8/8] drm/i915/dsi: Added the generic gpio sequence support and gpio table Jani Nikula
@ 2016-02-04 12:46 ` Patchwork
2016-02-05 7:31 ` ✗ Fi.CI.BAT: failure for drm/i915/dsi: i2c/gpio (rev3) Patchwork
9 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2016-02-04 12:46 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Summary ==
Series 3075v1 drm/i915/dsi: i2c/gpio
http://patchwork.freedesktop.org/api/1.0/series/3075/revisions/1/mbox/
Test gem_sync:
Subgroup basic-blt:
incomplete -> PASS (skl-i5k-2)
bdw-nuci7 total:161 pass:152 dwarn:0 dfail:0 fail:0 skip:9
bdw-ultra total:164 pass:152 dwarn:0 dfail:0 fail:0 skip:12
bsw-nuc-2 total:164 pass:136 dwarn:0 dfail:0 fail:0 skip:28
byt-nuc total:164 pass:141 dwarn:0 dfail:0 fail:0 skip:23
hsw-brixbox total:164 pass:151 dwarn:0 dfail:0 fail:0 skip:13
hsw-gt2 total:164 pass:154 dwarn:0 dfail:0 fail:0 skip:10
ilk-hp8440p total:164 pass:116 dwarn:0 dfail:0 fail:0 skip:48
ivb-t430s total:164 pass:150 dwarn:0 dfail:0 fail:0 skip:14
skl-i5k-2 total:164 pass:149 dwarn:1 dfail:0 fail:0 skip:14
skl-i7k-2 total:164 pass:149 dwarn:1 dfail:0 fail:0 skip:14
snb-dellxps total:164 pass:142 dwarn:0 dfail:0 fail:0 skip:22
snb-x220t total:164 pass:142 dwarn:0 dfail:0 fail:1 skip:21
Results at /archive/results/CI_IGT_test/Patchwork_1363/
82b0b8e5fd2d7b63877c91cbe45138efbc46114e drm-intel-nightly: 2016y-02m-04d-11h-00m-00s UTC integration manifest
153ea3657256af0ff0a69034617c65cf2e9ff584 drm/i915/dsi: Added the generic gpio sequence support and gpio table
36e84496ec9bc2b370901167d0f6f3a82a5e5ead drm/i915: Extend gpio read/write to other cores
9b18e955646369f63527273a52fc866008e309ba drm/i915/vlv: drop unused vlv_gps_core_read/write functions
d3b3ece97c24a1097b85239da9d1540c34573286 drm/i915: put the IOSF port defines in numerical order
592caf8e1850a690beed9c31b9db643f9c2ade21 drm/i915/dsi: skip gpio element execution when not supported
030d66367e8f38cf3de84b8d3c328523ce61bccf drm/i915: Adding the parsing logic for the i2c element
ea8629e96fa6d769dfcef796fd00f861ae41fd4a drm/i915/dsi: don't pass arbitrary data to sideband
33e71e3b31b6801ae3cb182d0e60afa561d98c0c drm/i915/dsi: defend gpio table against out of bounds access
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 3/8] drm/i915: Adding the parsing logic for the i2c element
2016-02-04 10:50 ` [PATCH 3/8] drm/i915: Adding the parsing logic for the i2c element Jani Nikula
@ 2016-02-04 15:28 ` Ville Syrjälä
2016-02-04 16:21 ` Jani Nikula
0 siblings, 1 reply; 36+ messages in thread
From: Ville Syrjälä @ 2016-02-04 15:28 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Feb 04, 2016 at 12:50:51PM +0200, Jani Nikula wrote:
> From: vkorjani <vikas.korjani@intel.com>
>
> New sequence element for i2c is been added in the
> mipi sequence block of the VBT. This patch parses
> and executes the i2c sequence.
>
> v2: Add i2c_put_adapter call(Jani), rebase
>
> v3: corrected the retry loop(Jani), rebase
>
> v4 by Jani:
> - don't put the adapter if get fails
> - print an error message if all retries exhausted
> - use a for loop
> - fix warnings for unused variables
>
> v5 by Jani:
> - rebase on the skip i2c element patch
>
> v6: by Jani:
> - ignore the gmbus i2c elements (Ville)
>
> Signed-off-by: vkorjani <vikas.korjani@intel.com>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 64 ++++++++++++++++++++++++++++--
> 1 file changed, 61 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index 6f013efba45b..f4d303ee538b 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -31,6 +31,7 @@
> #include <drm/drm_panel.h>
> #include <linux/slab.h>
> #include <video/mipi_display.h>
> +#include <linux/i2c.h>
> #include <asm/intel-mid.h>
> #include <video/mipi_display.h>
> #include "i915_drv.h"
> @@ -235,9 +236,66 @@ out:
> return data;
> }
>
> -static const u8 *mipi_exec_i2c_skip(struct intel_dsi *intel_dsi, const u8 *data)
> +static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
> {
> - return data + *(data + 6) + 7;
> + struct i2c_adapter *adapter;
> + int ret, i;
> + u8 reg_offset, payload_size;
> + struct i2c_msg msg;
> + u8 *transmit_buffer;
> + u8 flag, resource_id, bus_number;
> + u16 slave_add;
> +
> + flag = *data++;
> + resource_id = *data++;
> + bus_number = *data++;
> + slave_add = *(u16 *)(data);
> + data += 2;
> + reg_offset = *data++;
> + payload_size = *data++;
> +
> + if (resource_id == 0xff || bus_number == 0xff) {
> + DRM_DEBUG_KMS("ignoring gmbus (resource id %02x, bus %02x)\n",
> + resource_id, bus_number);
> + goto out;
> + }
> +
Still missing the check for __i2c_first_dynamic_bus_num which I think
would at least provide some kind of half arsed protection against
something not registering these magic i2c busses.
> + adapter = i2c_get_adapter(bus_number);
> + if (!adapter) {
> + DRM_ERROR("i2c_get_adapter(%u)\n", bus_number);
> + goto out;
> + }
> +
> + transmit_buffer = kmalloc(1 + payload_size, GFP_TEMPORARY);
> + if (!transmit_buffer)
> + goto out_put;
> +
> + transmit_buffer[0] = reg_offset;
> + memcpy(&transmit_buffer[1], data, payload_size);
> +
> + msg.addr = slave_add;
> + msg.flags = 0;
> + msg.len = payload_size + 1;
> + msg.buf = &transmit_buffer[0];
> +
> + for (i = 0; i < 6; i++) {
> + ret = i2c_transfer(adapter, &msg, 1);
> + if (ret == 1) {
> + goto out_free;
> + } else if (ret == -EAGAIN) {
> + usleep_range(1000, 2500);
> + } else {
> + break;
> + }
> + }
> +
> + DRM_ERROR("i2c transfer failed: %d\n", ret);
> +out_free:
> + kfree(transmit_buffer);
> +out_put:
> + i2c_put_adapter(adapter);
> +out:
> + return data + payload_size;
> }
>
> typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
> @@ -246,7 +304,7 @@ static const fn_mipi_elem_exec exec_elem[] = {
> [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet,
> [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay,
> [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio,
> - [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c_skip,
> + [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c,
> };
>
> /*
> --
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 4/8] drm/i915/dsi: skip gpio element execution when not supported
2016-02-04 10:50 ` [PATCH 4/8] drm/i915/dsi: skip gpio element execution when not supported Jani Nikula
@ 2016-02-04 15:36 ` Ville Syrjälä
2016-02-04 16:52 ` [PATCH v2] " Jani Nikula
1 sibling, 0 replies; 36+ messages in thread
From: Ville Syrjälä @ 2016-02-04 15:36 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Feb 04, 2016 at 12:50:52PM +0200, Jani Nikula wrote:
> Skip v3 gpio element because the support is not there, and skip gpio
> element on non-vlv/chv because the sideband code is vlv/chv specific.
>
> Cc: drm-intel-fixes@lists.freedesktop.org
> Fixes: 2a33d93486f2 ("drm/i915/bios: add support for MIPI sequence block v3")
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index f4d303ee538b..3e1e70f81506 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -205,6 +205,9 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> struct drm_device *dev = intel_dsi->base.base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> + if (dev_priv->vbt.dsi.seq_version >= 3)
> + data++;
> +
> gpio = *data++;
>
> /* pull up/down */
> @@ -215,6 +218,16 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> goto out;
> }
>
> + if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
> + DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
> + goto out;
> + }
The gpio register table is VLV specific. So CHV shall not pass.
> +
> + if (dev_priv->vbt.dsi.seq_version >= 3) {
> + DRM_DEBUG_KMS("GPIO element v3 not supported\n");
> + goto out;
> + }
> +
> function = gtable[gpio].function_reg;
> pad = gtable[gpio].pad_reg;
>
> --
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 7/8] drm/i915: Extend gpio read/write to other cores
2016-02-04 10:50 ` [PATCH 7/8] drm/i915: Extend gpio read/write to other cores Jani Nikula
@ 2016-02-04 15:39 ` Ville Syrjälä
2016-02-04 16:55 ` [PATCH v5] " Jani Nikula
1 sibling, 0 replies; 36+ messages in thread
From: Ville Syrjälä @ 2016-02-04 15:39 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Feb 04, 2016 at 12:50:55PM +0200, Jani Nikula wrote:
> From: Deepak M <m.deepak@intel.com>
>
> Make the gpio read/write functions more generic iosf sideband read/write
> functions, taking the iosf port as argument.
>
> v2: rebase
> v3: rebase
> v4 by Jani: address Ville's review
>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 4 ++--
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 5 +++--
> drivers/gpu/drm/i915/intel_sideband.c | 9 +++++----
> 4 files changed, 12 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index af601be8b490..47da528c16d0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3475,8 +3475,8 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val
> u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
> void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
> u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
> -u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
> -void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
> +u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
> +void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
> u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
> void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
> u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c761fa2f3b8b..d00e5b8e5469 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -618,6 +618,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define IOSF_PORT_CCK 0x14
> #define IOSF_PORT_DPIO_2 0x1a
> #define IOSF_PORT_FLISDSI 0x1b
> +#define IOSF_PORT_GPIO_SC 0x48
> +#define IOSF_PORT_GPIO_SUS 0xa8
> #define IOSF_PORT_CCU 0xa9
> #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
> #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index 3e1e70f81506..de1966552a33 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -235,14 +235,15 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> if (!gtable[gpio].init) {
> /* program the function */
> /* FIXME: remove constant below */
> - vlv_gpio_nc_write(dev_priv, function, 0x2000CC00);
> + vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, function,
> + 0x2000CC00);
> gtable[gpio].init = 1;
> }
>
> val = 0x4 | action;
>
> /* pull up/down */
> - vlv_gpio_nc_write(dev_priv, pad, val);
> + vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, pad, val);
> mutex_unlock(&dev_priv->sb_lock);
>
> out:
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index f5b0ab6f5942..78c3d93fd963 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -129,17 +129,18 @@ u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
> return val;
> }
>
> -u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg)
> +u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg)
> {
> u32 val = 0;
> - vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,
> + vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), port,
^
Not correct.
> SB_CRRDDA_NP, reg, &val);
> return val;
> }
>
> -void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
> +void vlv_iosf_sb_write(struct drm_i915_private *dev_priv,
> + u8 port, u32 reg, u32 val)
> {
> - vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,
> + vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), port,
ditto
> SB_CRWRDA_NP, reg, &val);
> }
>
> --
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/8] drm/i915/dsi: defend gpio table against out of bounds access
2016-02-04 10:50 ` [PATCH 1/8] drm/i915/dsi: defend gpio table against out of bounds access Jani Nikula
@ 2016-02-04 15:40 ` Ville Syrjälä
0 siblings, 0 replies; 36+ messages in thread
From: Ville Syrjälä @ 2016-02-04 15:40 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Feb 04, 2016 at 12:50:49PM +0200, Jani Nikula wrote:
> Do not blindly trust the VBT data used for indexing.
>
> Cc: stable@vger.kernel.org
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index 1d43e6f37fc1..4775aa5462e8 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -209,6 +209,11 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> /* pull up/down */
> action = *data++;
>
> + if (gpio >= ARRAY_SIZE(gtable)) {
> + DRM_DEBUG_KMS("unknown gpio %u\n", gpio);
> + goto out;
> + }
> +
> function = gtable[gpio].function_reg;
> pad = gtable[gpio].pad_reg;
>
> @@ -226,6 +231,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> vlv_gpio_nc_write(dev_priv, pad, val);
> mutex_unlock(&dev_priv->sb_lock);
>
> +out:
> return data;
> }
>
> --
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 2/8] drm/i915/dsi: don't pass arbitrary data to sideband
2016-02-04 10:50 ` [PATCH 2/8] drm/i915/dsi: don't pass arbitrary data to sideband Jani Nikula
@ 2016-02-04 15:41 ` Ville Syrjälä
2016-02-04 16:56 ` Jani Nikula
0 siblings, 1 reply; 36+ messages in thread
From: Ville Syrjälä @ 2016-02-04 15:41 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Feb 04, 2016 at 12:50:50PM +0200, Jani Nikula wrote:
> Since sequence block v2 the second byte contains flags other than just
> pull up/down. Don't pass arbitrary data to the sideband interface.
>
> The rest may or may not work for sequence block v2, but there should be
> no harm done.
>
> Cc: stable@vger.kernel.org
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
well, as far as it can be reviewed with the crappy specs.
> ---
> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index 4775aa5462e8..6f013efba45b 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -207,7 +207,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> gpio = *data++;
>
> /* pull up/down */
> - action = *data++;
> + action = *data++ & 1;
>
> if (gpio >= ARRAY_SIZE(gtable)) {
> DRM_DEBUG_KMS("unknown gpio %u\n", gpio);
> --
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 5/8] drm/i915: put the IOSF port defines in numerical order
2016-02-04 10:50 ` [PATCH 5/8] drm/i915: put the IOSF port defines in numerical order Jani Nikula
@ 2016-02-04 16:05 ` Ville Syrjälä
0 siblings, 0 replies; 36+ messages in thread
From: Ville Syrjälä @ 2016-02-04 16:05 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Feb 04, 2016 at 12:50:53PM +0200, Jani Nikula wrote:
> Make it easier to spot duplicates.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c0bd691b41f8..f3b4b19198b9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -610,16 +610,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define IOSF_BYTE_ENABLES_SHIFT 4
> #define IOSF_BAR_SHIFT 1
> #define IOSF_SB_BUSY (1<<0)
> -#define IOSF_PORT_BUNIT 0x3
> -#define IOSF_PORT_PUNIT 0x4
> +#define IOSF_PORT_BUNIT 0x03
> +#define IOSF_PORT_PUNIT 0x04
> #define IOSF_PORT_NC 0x11
> #define IOSF_PORT_DPIO 0x12
> -#define IOSF_PORT_DPIO_2 0x1a
> #define IOSF_PORT_GPIO_NC 0x13
> #define IOSF_PORT_CCK 0x14
> -#define IOSF_PORT_CCU 0xA9
> +#define IOSF_PORT_DPIO_2 0x1a
> +#define IOSF_PORT_FLISDSI 0x1b
> #define IOSF_PORT_GPS_CORE 0x48
> -#define IOSF_PORT_FLISDSI 0x1B
> +#define IOSF_PORT_CCU 0xa9
> #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
> #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
>
> --
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 6/8] drm/i915/vlv: drop unused vlv_gps_core_read/write functions
2016-02-04 10:50 ` [PATCH 6/8] drm/i915/vlv: drop unused vlv_gps_core_read/write functions Jani Nikula
@ 2016-02-04 16:12 ` Ville Syrjälä
2016-02-04 16:57 ` Jani Nikula
0 siblings, 1 reply; 36+ messages in thread
From: Ville Syrjälä @ 2016-02-04 16:12 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Feb 04, 2016 at 12:50:54PM +0200, Jani Nikula wrote:
> Not needed.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 --
> drivers/gpu/drm/i915/i915_reg.h | 1 -
> drivers/gpu/drm/i915/intel_sideband.c | 14 --------------
> 3 files changed, 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 77227a39f3d5..af601be8b490 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3483,8 +3483,6 @@ u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
> void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
> u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
> void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
> -u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
> -void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
> u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
> void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
> u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f3b4b19198b9..c761fa2f3b8b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -618,7 +618,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define IOSF_PORT_CCK 0x14
> #define IOSF_PORT_DPIO_2 0x1a
> #define IOSF_PORT_FLISDSI 0x1b
> -#define IOSF_PORT_GPS_CORE 0x48
> #define IOSF_PORT_CCU 0xa9
> #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
> #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index 8831fc579ade..f5b0ab6f5942 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -171,20 +171,6 @@ void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
> SB_CRWRDA_NP, reg, &val);
> }
>
> -u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg)
> -{
> - u32 val = 0;
> - vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPS_CORE,
> - SB_CRRDDA_NP, reg, &val);
> - return val;
> -}
> -
> -void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
> -{
> - vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPS_CORE,
> - SB_CRWRDA_NP, reg, &val);
> -}
> -
> u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
> {
> u32 val = 0;
> --
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 3/8] drm/i915: Adding the parsing logic for the i2c element
2016-02-04 15:28 ` Ville Syrjälä
@ 2016-02-04 16:21 ` Jani Nikula
2016-02-04 16:36 ` Ville Syrjälä
0 siblings, 1 reply; 36+ messages in thread
From: Jani Nikula @ 2016-02-04 16:21 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, 04 Feb 2016, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, Feb 04, 2016 at 12:50:51PM +0200, Jani Nikula wrote:
>> From: vkorjani <vikas.korjani@intel.com>
>>
>> New sequence element for i2c is been added in the
>> mipi sequence block of the VBT. This patch parses
>> and executes the i2c sequence.
>>
>> v2: Add i2c_put_adapter call(Jani), rebase
>>
>> v3: corrected the retry loop(Jani), rebase
>>
>> v4 by Jani:
>> - don't put the adapter if get fails
>> - print an error message if all retries exhausted
>> - use a for loop
>> - fix warnings for unused variables
>>
>> v5 by Jani:
>> - rebase on the skip i2c element patch
>>
>> v6: by Jani:
>> - ignore the gmbus i2c elements (Ville)
>>
>> Signed-off-by: vkorjani <vikas.korjani@intel.com>
>> Signed-off-by: Deepak M <m.deepak@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 64 ++++++++++++++++++++++++++++--
>> 1 file changed, 61 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> index 6f013efba45b..f4d303ee538b 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> @@ -31,6 +31,7 @@
>> #include <drm/drm_panel.h>
>> #include <linux/slab.h>
>> #include <video/mipi_display.h>
>> +#include <linux/i2c.h>
>> #include <asm/intel-mid.h>
>> #include <video/mipi_display.h>
>> #include "i915_drv.h"
>> @@ -235,9 +236,66 @@ out:
>> return data;
>> }
>>
>> -static const u8 *mipi_exec_i2c_skip(struct intel_dsi *intel_dsi, const u8 *data)
>> +static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
>> {
>> - return data + *(data + 6) + 7;
>> + struct i2c_adapter *adapter;
>> + int ret, i;
>> + u8 reg_offset, payload_size;
>> + struct i2c_msg msg;
>> + u8 *transmit_buffer;
>> + u8 flag, resource_id, bus_number;
>> + u16 slave_add;
>> +
>> + flag = *data++;
>> + resource_id = *data++;
>> + bus_number = *data++;
>> + slave_add = *(u16 *)(data);
>> + data += 2;
>> + reg_offset = *data++;
>> + payload_size = *data++;
>> +
>> + if (resource_id == 0xff || bus_number == 0xff) {
>> + DRM_DEBUG_KMS("ignoring gmbus (resource id %02x, bus %02x)\n",
>> + resource_id, bus_number);
>> + goto out;
>> + }
>> +
>
> Still missing the check for __i2c_first_dynamic_bus_num which I think
> would at least provide some kind of half arsed protection against
> something not registering these magic i2c busses.
I meant to reply to that part of the review but forgot.
Problem is, we'd have to include drivers/i2c/i2c-core.h directly, which
also has this warning,
/* These symbols are exported ONLY FOR the i2c core.
* No other users will be supported.
*/
and there are no users outside of drivers/i2c. I'm quite reluctant to
add that.
BR,
Jani.
>
>> + adapter = i2c_get_adapter(bus_number);
>> + if (!adapter) {
>> + DRM_ERROR("i2c_get_adapter(%u)\n", bus_number);
>> + goto out;
>> + }
>> +
>> + transmit_buffer = kmalloc(1 + payload_size, GFP_TEMPORARY);
>> + if (!transmit_buffer)
>> + goto out_put;
>> +
>> + transmit_buffer[0] = reg_offset;
>> + memcpy(&transmit_buffer[1], data, payload_size);
>> +
>> + msg.addr = slave_add;
>> + msg.flags = 0;
>> + msg.len = payload_size + 1;
>> + msg.buf = &transmit_buffer[0];
>> +
>> + for (i = 0; i < 6; i++) {
>> + ret = i2c_transfer(adapter, &msg, 1);
>> + if (ret == 1) {
>> + goto out_free;
>> + } else if (ret == -EAGAIN) {
>> + usleep_range(1000, 2500);
>> + } else {
>> + break;
>> + }
>> + }
>> +
>> + DRM_ERROR("i2c transfer failed: %d\n", ret);
>> +out_free:
>> + kfree(transmit_buffer);
>> +out_put:
>> + i2c_put_adapter(adapter);
>> +out:
>> + return data + payload_size;
>> }
>>
>> typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
>> @@ -246,7 +304,7 @@ static const fn_mipi_elem_exec exec_elem[] = {
>> [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet,
>> [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay,
>> [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio,
>> - [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c_skip,
>> + [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c,
>> };
>>
>> /*
>> --
>> 2.1.4
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 3/8] drm/i915: Adding the parsing logic for the i2c element
2016-02-04 16:21 ` Jani Nikula
@ 2016-02-04 16:36 ` Ville Syrjälä
2016-02-15 16:48 ` Daniel Vetter
0 siblings, 1 reply; 36+ messages in thread
From: Ville Syrjälä @ 2016-02-04 16:36 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Feb 04, 2016 at 06:21:23PM +0200, Jani Nikula wrote:
> On Thu, 04 Feb 2016, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Thu, Feb 04, 2016 at 12:50:51PM +0200, Jani Nikula wrote:
> >> From: vkorjani <vikas.korjani@intel.com>
> >>
> >> New sequence element for i2c is been added in the
> >> mipi sequence block of the VBT. This patch parses
> >> and executes the i2c sequence.
> >>
> >> v2: Add i2c_put_adapter call(Jani), rebase
> >>
> >> v3: corrected the retry loop(Jani), rebase
> >>
> >> v4 by Jani:
> >> - don't put the adapter if get fails
> >> - print an error message if all retries exhausted
> >> - use a for loop
> >> - fix warnings for unused variables
> >>
> >> v5 by Jani:
> >> - rebase on the skip i2c element patch
> >>
> >> v6: by Jani:
> >> - ignore the gmbus i2c elements (Ville)
> >>
> >> Signed-off-by: vkorjani <vikas.korjani@intel.com>
> >> Signed-off-by: Deepak M <m.deepak@intel.com>
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 64 ++++++++++++++++++++++++++++--
> >> 1 file changed, 61 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> >> index 6f013efba45b..f4d303ee538b 100644
> >> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> >> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> >> @@ -31,6 +31,7 @@
> >> #include <drm/drm_panel.h>
> >> #include <linux/slab.h>
> >> #include <video/mipi_display.h>
> >> +#include <linux/i2c.h>
> >> #include <asm/intel-mid.h>
> >> #include <video/mipi_display.h>
> >> #include "i915_drv.h"
> >> @@ -235,9 +236,66 @@ out:
> >> return data;
> >> }
> >>
> >> -static const u8 *mipi_exec_i2c_skip(struct intel_dsi *intel_dsi, const u8 *data)
> >> +static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
> >> {
> >> - return data + *(data + 6) + 7;
> >> + struct i2c_adapter *adapter;
> >> + int ret, i;
> >> + u8 reg_offset, payload_size;
> >> + struct i2c_msg msg;
> >> + u8 *transmit_buffer;
> >> + u8 flag, resource_id, bus_number;
> >> + u16 slave_add;
> >> +
> >> + flag = *data++;
> >> + resource_id = *data++;
> >> + bus_number = *data++;
> >> + slave_add = *(u16 *)(data);
> >> + data += 2;
> >> + reg_offset = *data++;
> >> + payload_size = *data++;
> >> +
> >> + if (resource_id == 0xff || bus_number == 0xff) {
> >> + DRM_DEBUG_KMS("ignoring gmbus (resource id %02x, bus %02x)\n",
> >> + resource_id, bus_number);
> >> + goto out;
> >> + }
> >> +
> >
> > Still missing the check for __i2c_first_dynamic_bus_num which I think
> > would at least provide some kind of half arsed protection against
> > something not registering these magic i2c busses.
>
> I meant to reply to that part of the review but forgot.
>
> Problem is, we'd have to include drivers/i2c/i2c-core.h directly, which
> also has this warning,
>
> /* These symbols are exported ONLY FOR the i2c core.
> * No other users will be supported.
> */
>
> and there are no users outside of drivers/i2c. I'm quite reluctant to
> add that.
The we need some other way to look up the adapter. Passing in
essentially random adapter numbers could give us more or less
any i2c bus on the system, and if we go poke there we could do
real damage.
The whole scheme is very poorly thoght out I think. There really
should be some kind of ACPI ID or something that lets us look up
exactly the right thing.
>
>
> BR,
> Jani.
>
>
> >
> >> + adapter = i2c_get_adapter(bus_number);
> >> + if (!adapter) {
> >> + DRM_ERROR("i2c_get_adapter(%u)\n", bus_number);
> >> + goto out;
> >> + }
> >> +
> >> + transmit_buffer = kmalloc(1 + payload_size, GFP_TEMPORARY);
> >> + if (!transmit_buffer)
> >> + goto out_put;
> >> +
> >> + transmit_buffer[0] = reg_offset;
> >> + memcpy(&transmit_buffer[1], data, payload_size);
> >> +
> >> + msg.addr = slave_add;
> >> + msg.flags = 0;
> >> + msg.len = payload_size + 1;
> >> + msg.buf = &transmit_buffer[0];
> >> +
> >> + for (i = 0; i < 6; i++) {
> >> + ret = i2c_transfer(adapter, &msg, 1);
> >> + if (ret == 1) {
> >> + goto out_free;
> >> + } else if (ret == -EAGAIN) {
> >> + usleep_range(1000, 2500);
> >> + } else {
> >> + break;
> >> + }
> >> + }
> >> +
> >> + DRM_ERROR("i2c transfer failed: %d\n", ret);
> >> +out_free:
> >> + kfree(transmit_buffer);
> >> +out_put:
> >> + i2c_put_adapter(adapter);
> >> +out:
> >> + return data + payload_size;
> >> }
> >>
> >> typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
> >> @@ -246,7 +304,7 @@ static const fn_mipi_elem_exec exec_elem[] = {
> >> [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet,
> >> [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay,
> >> [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio,
> >> - [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c_skip,
> >> + [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c,
> >> };
> >>
> >> /*
> >> --
> >> 2.1.4
> >>
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Jani Nikula, Intel Open Source Technology Center
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v2] drm/i915/dsi: skip gpio element execution when not supported
2016-02-04 10:50 ` [PATCH 4/8] drm/i915/dsi: skip gpio element execution when not supported Jani Nikula
2016-02-04 15:36 ` Ville Syrjälä
@ 2016-02-04 16:52 ` Jani Nikula
2016-02-04 17:05 ` Ville Syrjälä
2016-02-04 17:49 ` Ville Syrjälä
1 sibling, 2 replies; 36+ messages in thread
From: Jani Nikula @ 2016-02-04 16:52 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
Skip v3 gpio element because the support is not there, and skip gpio
element on non-vlv because the sideband code is vlv specific.
v2: the gpio stuff is currently only supported on vlv (Ville)
Cc: drm-intel-fixes@lists.freedesktop.org
Fixes: 2a33d93486f2 ("drm/i915/bios: add support for MIPI sequence block v3")
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index f4d303ee538b..bcc083db7632 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -205,6 +205,9 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
struct drm_device *dev = intel_dsi->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ if (dev_priv->vbt.dsi.seq_version >= 3)
+ data++;
+
gpio = *data++;
/* pull up/down */
@@ -215,6 +218,16 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
goto out;
}
+ if (!IS_VALLEYVIEW(dev_priv)) {
+ DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
+ goto out;
+ }
+
+ if (dev_priv->vbt.dsi.seq_version >= 3) {
+ DRM_DEBUG_KMS("GPIO element v3 not supported\n");
+ goto out;
+ }
+
function = gtable[gpio].function_reg;
pad = gtable[gpio].pad_reg;
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v5] drm/i915: Extend gpio read/write to other cores
2016-02-04 10:50 ` [PATCH 7/8] drm/i915: Extend gpio read/write to other cores Jani Nikula
2016-02-04 15:39 ` Ville Syrjälä
@ 2016-02-04 16:55 ` Jani Nikula
2016-02-04 17:03 ` Ville Syrjälä
1 sibling, 1 reply; 36+ messages in thread
From: Jani Nikula @ 2016-02-04 16:55 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
From: Deepak M <m.deepak@intel.com>
Make the gpio read/write functions more generic iosf sideband read/write
functions, taking the iosf port as argument.
v2: rebase
v3: rebase
v4 by Jani: address Ville's review
v5 by Jani: drop the PCI_DEVFN change (Ville)
Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 5 +++--
drivers/gpu/drm/i915/intel_sideband.c | 9 +++++----
4 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bd126ff3a6e2..8216665405eb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3471,8 +3471,8 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
-u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
-void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
+u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
+void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6867295dbdc1..6732fc139196 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -618,6 +618,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define IOSF_PORT_CCK 0x14
#define IOSF_PORT_DPIO_2 0x1a
#define IOSF_PORT_FLISDSI 0x1b
+#define IOSF_PORT_GPIO_SC 0x48
+#define IOSF_PORT_GPIO_SUS 0xa8
#define IOSF_PORT_CCU 0xa9
#define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
#define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index bcc083db7632..b96ac87902b4 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -235,14 +235,15 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
if (!gtable[gpio].init) {
/* program the function */
/* FIXME: remove constant below */
- vlv_gpio_nc_write(dev_priv, function, 0x2000CC00);
+ vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, function,
+ 0x2000CC00);
gtable[gpio].init = 1;
}
val = 0x4 | action;
/* pull up/down */
- vlv_gpio_nc_write(dev_priv, pad, val);
+ vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, pad, val);
mutex_unlock(&dev_priv->sb_lock);
out:
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index f5b0ab6f5942..c3998188cf35 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -129,17 +129,18 @@ u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
return val;
}
-u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg)
+u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg)
{
u32 val = 0;
- vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,
+ vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), port,
SB_CRRDDA_NP, reg, &val);
return val;
}
-void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
+void vlv_iosf_sb_write(struct drm_i915_private *dev_priv,
+ u8 port, u32 reg, u32 val)
{
- vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,
+ vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), port,
SB_CRWRDA_NP, reg, &val);
}
--
2.1.4
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [PATCH 2/8] drm/i915/dsi: don't pass arbitrary data to sideband
2016-02-04 15:41 ` Ville Syrjälä
@ 2016-02-04 16:56 ` Jani Nikula
0 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2016-02-04 16:56 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, 04 Feb 2016, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, Feb 04, 2016 at 12:50:50PM +0200, Jani Nikula wrote:
>> Since sequence block v2 the second byte contains flags other than just
>> pull up/down. Don't pass arbitrary data to the sideband interface.
>>
>> The rest may or may not work for sequence block v2, but there should be
>> no harm done.
>>
>> Cc: stable@vger.kernel.org
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> well, as far as it can be reviewed with the crappy specs.
Pushed patches 1-2 to dinq, thanks for the review.
BR,
Jani.
>
>> ---
>> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> index 4775aa5462e8..6f013efba45b 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> @@ -207,7 +207,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>> gpio = *data++;
>>
>> /* pull up/down */
>> - action = *data++;
>> + action = *data++ & 1;
>>
>> if (gpio >= ARRAY_SIZE(gtable)) {
>> DRM_DEBUG_KMS("unknown gpio %u\n", gpio);
>> --
>> 2.1.4
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 6/8] drm/i915/vlv: drop unused vlv_gps_core_read/write functions
2016-02-04 16:12 ` Ville Syrjälä
@ 2016-02-04 16:57 ` Jani Nikula
0 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2016-02-04 16:57 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, 04 Feb 2016, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, Feb 04, 2016 at 12:50:54PM +0200, Jani Nikula wrote:
>> Not needed.
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Pushed patches 5-6 to dinq, thanks for the review.
BR,
Jani.
>
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 2 --
>> drivers/gpu/drm/i915/i915_reg.h | 1 -
>> drivers/gpu/drm/i915/intel_sideband.c | 14 --------------
>> 3 files changed, 17 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 77227a39f3d5..af601be8b490 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -3483,8 +3483,6 @@ u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
>> void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
>> u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
>> void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
>> -u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
>> -void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
>> u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
>> void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
>> u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index f3b4b19198b9..c761fa2f3b8b 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -618,7 +618,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>> #define IOSF_PORT_CCK 0x14
>> #define IOSF_PORT_DPIO_2 0x1a
>> #define IOSF_PORT_FLISDSI 0x1b
>> -#define IOSF_PORT_GPS_CORE 0x48
>> #define IOSF_PORT_CCU 0xa9
>> #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
>> #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
>> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
>> index 8831fc579ade..f5b0ab6f5942 100644
>> --- a/drivers/gpu/drm/i915/intel_sideband.c
>> +++ b/drivers/gpu/drm/i915/intel_sideband.c
>> @@ -171,20 +171,6 @@ void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
>> SB_CRWRDA_NP, reg, &val);
>> }
>>
>> -u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg)
>> -{
>> - u32 val = 0;
>> - vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPS_CORE,
>> - SB_CRRDDA_NP, reg, &val);
>> - return val;
>> -}
>> -
>> -void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
>> -{
>> - vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPS_CORE,
>> - SB_CRWRDA_NP, reg, &val);
>> -}
>> -
>> u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
>> {
>> u32 val = 0;
>> --
>> 2.1.4
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v5] drm/i915: Extend gpio read/write to other cores
2016-02-04 16:55 ` [PATCH v5] " Jani Nikula
@ 2016-02-04 17:03 ` Ville Syrjälä
2016-02-04 17:14 ` Jani Nikula
0 siblings, 1 reply; 36+ messages in thread
From: Ville Syrjälä @ 2016-02-04 17:03 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Feb 04, 2016 at 06:55:15PM +0200, Jani Nikula wrote:
> From: Deepak M <m.deepak@intel.com>
>
> Make the gpio read/write functions more generic iosf sideband read/write
> functions, taking the iosf port as argument.
>
> v2: rebase
> v3: rebase
> v4 by Jani: address Ville's review
> v5 by Jani: drop the PCI_DEVFN change (Ville)
>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 4 ++--
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 5 +++--
> drivers/gpu/drm/i915/intel_sideband.c | 9 +++++----
> 4 files changed, 12 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index bd126ff3a6e2..8216665405eb 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3471,8 +3471,8 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val
> u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
> void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
> u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
> -u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
> -void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
> +u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
> +void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
> u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
> void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
> u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6867295dbdc1..6732fc139196 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -618,6 +618,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define IOSF_PORT_CCK 0x14
> #define IOSF_PORT_DPIO_2 0x1a
> #define IOSF_PORT_FLISDSI 0x1b
> +#define IOSF_PORT_GPIO_SC 0x48
> +#define IOSF_PORT_GPIO_SUS 0xa8
> #define IOSF_PORT_CCU 0xa9
> #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
> #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index bcc083db7632..b96ac87902b4 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -235,14 +235,15 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> if (!gtable[gpio].init) {
> /* program the function */
> /* FIXME: remove constant below */
> - vlv_gpio_nc_write(dev_priv, function, 0x2000CC00);
> + vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, function,
> + 0x2000CC00);
> gtable[gpio].init = 1;
> }
>
> val = 0x4 | action;
>
> /* pull up/down */
> - vlv_gpio_nc_write(dev_priv, pad, val);
> + vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, pad, val);
> mutex_unlock(&dev_priv->sb_lock);
>
> out:
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index f5b0ab6f5942..c3998188cf35 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -129,17 +129,18 @@ u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
> return val;
> }
>
> -u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg)
> +u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg)
> {
> u32 val = 0;
> - vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,
> + vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), port,
> SB_CRRDDA_NP, reg, &val);
> return val;
> }
>
> -void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
> +void vlv_iosf_sb_write(struct drm_i915_private *dev_priv,
> + u8 port, u32 reg, u32 val)
> {
> - vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,
> + vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), port,
> SB_CRWRDA_NP, reg, &val);
> }
>
> --
> 2.1.4
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v2] drm/i915/dsi: skip gpio element execution when not supported
2016-02-04 16:52 ` [PATCH v2] " Jani Nikula
@ 2016-02-04 17:05 ` Ville Syrjälä
2016-02-04 17:10 ` Jani Nikula
2016-02-04 17:49 ` Ville Syrjälä
1 sibling, 1 reply; 36+ messages in thread
From: Ville Syrjälä @ 2016-02-04 17:05 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Feb 04, 2016 at 06:52:47PM +0200, Jani Nikula wrote:
> Skip v3 gpio element because the support is not there, and skip gpio
> element on non-vlv because the sideband code is vlv specific.
>
> v2: the gpio stuff is currently only supported on vlv (Ville)
>
> Cc: drm-intel-fixes@lists.freedesktop.org
> Fixes: 2a33d93486f2 ("drm/i915/bios: add support for MIPI sequence block v3")
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index f4d303ee538b..bcc083db7632 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -205,6 +205,9 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> struct drm_device *dev = intel_dsi->base.base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> + if (dev_priv->vbt.dsi.seq_version >= 3)
> + data++;
> +
So here we handle v3
> gpio = *data++;
>
> /* pull up/down */
> @@ -215,6 +218,16 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> goto out;
> }
>
> + if (!IS_VALLEYVIEW(dev_priv)) {
> + DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
> + goto out;
> + }
> +
> + if (dev_priv->vbt.dsi.seq_version >= 3) {
> + DRM_DEBUG_KMS("GPIO element v3 not supported\n");
> + goto out;
> + }
but here we say it's not supported. Is there more missing?
> +
> function = gtable[gpio].function_reg;
> pad = gtable[gpio].pad_reg;
>
> --
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v2] drm/i915/dsi: skip gpio element execution when not supported
2016-02-04 17:05 ` Ville Syrjälä
@ 2016-02-04 17:10 ` Jani Nikula
2016-02-04 17:12 ` Jani Nikula
2016-02-04 17:18 ` Ville Syrjälä
0 siblings, 2 replies; 36+ messages in thread
From: Jani Nikula @ 2016-02-04 17:10 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, 04 Feb 2016, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, Feb 04, 2016 at 06:52:47PM +0200, Jani Nikula wrote:
>> Skip v3 gpio element because the support is not there, and skip gpio
>> element on non-vlv because the sideband code is vlv specific.
>>
>> v2: the gpio stuff is currently only supported on vlv (Ville)
>>
>> Cc: drm-intel-fixes@lists.freedesktop.org
>> Fixes: 2a33d93486f2 ("drm/i915/bios: add support for MIPI sequence block v3")
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 13 +++++++++++++
>> 1 file changed, 13 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> index f4d303ee538b..bcc083db7632 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> @@ -205,6 +205,9 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>> struct drm_device *dev = intel_dsi->base.base.dev;
>> struct drm_i915_private *dev_priv = dev->dev_private;
>>
>> + if (dev_priv->vbt.dsi.seq_version >= 3)
>> + data++;
>> +
>
> So here we handle v3
>
>> gpio = *data++;
>>
>> /* pull up/down */
>> @@ -215,6 +218,16 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>> goto out;
>> }
>>
>> + if (!IS_VALLEYVIEW(dev_priv)) {
>> + DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
>> + goto out;
>> + }
>> +
>> + if (dev_priv->vbt.dsi.seq_version >= 3) {
>> + DRM_DEBUG_KMS("GPIO element v3 not supported\n");
>> + goto out;
>> + }
>
> but here we say it's not supported. Is there more missing?
The whole point of doing it this way is to support *skipping* v3 in a
graceful manner. If I bailed out at the top, I'd have to duplicate the
knowledge about the length of the element.
BR,
Jani.
>
>> +
>> function = gtable[gpio].function_reg;
>> pad = gtable[gpio].pad_reg;
>>
>> --
>> 2.1.4
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v2] drm/i915/dsi: skip gpio element execution when not supported
2016-02-04 17:10 ` Jani Nikula
@ 2016-02-04 17:12 ` Jani Nikula
2016-02-04 17:18 ` Ville Syrjälä
1 sibling, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2016-02-04 17:12 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, 04 Feb 2016, Jani Nikula <jani.nikula@intel.com> wrote:
> On Thu, 04 Feb 2016, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
>> On Thu, Feb 04, 2016 at 06:52:47PM +0200, Jani Nikula wrote:
>>> Skip v3 gpio element because the support is not there, and skip gpio
>>> element on non-vlv because the sideband code is vlv specific.
>>>
>>> v2: the gpio stuff is currently only supported on vlv (Ville)
>>>
>>> Cc: drm-intel-fixes@lists.freedesktop.org
>>> Fixes: 2a33d93486f2 ("drm/i915/bios: add support for MIPI sequence block v3")
>>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 13 +++++++++++++
>>> 1 file changed, 13 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>> index f4d303ee538b..bcc083db7632 100644
>>> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>> @@ -205,6 +205,9 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>>> struct drm_device *dev = intel_dsi->base.base.dev;
>>> struct drm_i915_private *dev_priv = dev->dev_private;
>>>
>>> + if (dev_priv->vbt.dsi.seq_version >= 3)
>>> + data++;
>>> +
>>
>> So here we handle v3
>>
>>> gpio = *data++;
>>>
>>> /* pull up/down */
>>> @@ -215,6 +218,16 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>>> goto out;
>>> }
>>>
>>> + if (!IS_VALLEYVIEW(dev_priv)) {
>>> + DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
>>> + goto out;
>>> + }
>>> +
>>> + if (dev_priv->vbt.dsi.seq_version >= 3) {
>>> + DRM_DEBUG_KMS("GPIO element v3 not supported\n");
>>> + goto out;
>>> + }
>>
>> but here we say it's not supported. Is there more missing?
>
> The whole point of doing it this way is to support *skipping* v3 in a
> graceful manner. If I bailed out at the top, I'd have to duplicate the
> knowledge about the length of the element.
Oh, and I want to split the v3 support like this to allow backporting
*this* patch for fixes, while the actual support goes through dinq.
>
> BR,
> Jani.
>
>
>>
>>> +
>>> function = gtable[gpio].function_reg;
>>> pad = gtable[gpio].pad_reg;
>>>
>>> --
>>> 2.1.4
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v5] drm/i915: Extend gpio read/write to other cores
2016-02-04 17:03 ` Ville Syrjälä
@ 2016-02-04 17:14 ` Jani Nikula
0 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2016-02-04 17:14 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, 04 Feb 2016, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, Feb 04, 2016 at 06:55:15PM +0200, Jani Nikula wrote:
>> From: Deepak M <m.deepak@intel.com>
>>
>> Make the gpio read/write functions more generic iosf sideband read/write
>> functions, taking the iosf port as argument.
>>
>> v2: rebase
>> v3: rebase
>> v4 by Jani: address Ville's review
>> v5 by Jani: drop the PCI_DEVFN change (Ville)
>>
>> Signed-off-by: Deepak M <m.deepak@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Pushed this patch to dinq, thanks for the review.
BR,
Jani.
>
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 4 ++--
>> drivers/gpu/drm/i915/i915_reg.h | 2 ++
>> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 5 +++--
>> drivers/gpu/drm/i915/intel_sideband.c | 9 +++++----
>> 4 files changed, 12 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index bd126ff3a6e2..8216665405eb 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -3471,8 +3471,8 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val
>> u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
>> void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
>> u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
>> -u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
>> -void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
>> +u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
>> +void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
>> u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
>> void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
>> u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 6867295dbdc1..6732fc139196 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -618,6 +618,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>> #define IOSF_PORT_CCK 0x14
>> #define IOSF_PORT_DPIO_2 0x1a
>> #define IOSF_PORT_FLISDSI 0x1b
>> +#define IOSF_PORT_GPIO_SC 0x48
>> +#define IOSF_PORT_GPIO_SUS 0xa8
>> #define IOSF_PORT_CCU 0xa9
>> #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
>> #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> index bcc083db7632..b96ac87902b4 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> @@ -235,14 +235,15 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>> if (!gtable[gpio].init) {
>> /* program the function */
>> /* FIXME: remove constant below */
>> - vlv_gpio_nc_write(dev_priv, function, 0x2000CC00);
>> + vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, function,
>> + 0x2000CC00);
>> gtable[gpio].init = 1;
>> }
>>
>> val = 0x4 | action;
>>
>> /* pull up/down */
>> - vlv_gpio_nc_write(dev_priv, pad, val);
>> + vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, pad, val);
>> mutex_unlock(&dev_priv->sb_lock);
>>
>> out:
>> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
>> index f5b0ab6f5942..c3998188cf35 100644
>> --- a/drivers/gpu/drm/i915/intel_sideband.c
>> +++ b/drivers/gpu/drm/i915/intel_sideband.c
>> @@ -129,17 +129,18 @@ u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
>> return val;
>> }
>>
>> -u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg)
>> +u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg)
>> {
>> u32 val = 0;
>> - vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,
>> + vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), port,
>> SB_CRRDDA_NP, reg, &val);
>> return val;
>> }
>>
>> -void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
>> +void vlv_iosf_sb_write(struct drm_i915_private *dev_priv,
>> + u8 port, u32 reg, u32 val)
>> {
>> - vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,
>> + vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), port,
>> SB_CRWRDA_NP, reg, &val);
>> }
>>
>> --
>> 2.1.4
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v2] drm/i915/dsi: skip gpio element execution when not supported
2016-02-04 17:10 ` Jani Nikula
2016-02-04 17:12 ` Jani Nikula
@ 2016-02-04 17:18 ` Ville Syrjälä
2016-02-04 17:22 ` Jani Nikula
1 sibling, 1 reply; 36+ messages in thread
From: Ville Syrjälä @ 2016-02-04 17:18 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Feb 04, 2016 at 07:10:42PM +0200, Jani Nikula wrote:
> On Thu, 04 Feb 2016, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Thu, Feb 04, 2016 at 06:52:47PM +0200, Jani Nikula wrote:
> >> Skip v3 gpio element because the support is not there, and skip gpio
> >> element on non-vlv because the sideband code is vlv specific.
> >>
> >> v2: the gpio stuff is currently only supported on vlv (Ville)
> >>
> >> Cc: drm-intel-fixes@lists.freedesktop.org
> >> Fixes: 2a33d93486f2 ("drm/i915/bios: add support for MIPI sequence block v3")
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 13 +++++++++++++
> >> 1 file changed, 13 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> >> index f4d303ee538b..bcc083db7632 100644
> >> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> >> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> >> @@ -205,6 +205,9 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> >> struct drm_device *dev = intel_dsi->base.base.dev;
> >> struct drm_i915_private *dev_priv = dev->dev_private;
> >>
> >> + if (dev_priv->vbt.dsi.seq_version >= 3)
> >> + data++;
> >> +
> >
> > So here we handle v3
> >
> >> gpio = *data++;
> >>
> >> /* pull up/down */
> >> @@ -215,6 +218,16 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> >> goto out;
> >> }
> >>
> >> + if (!IS_VALLEYVIEW(dev_priv)) {
> >> + DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
> >> + goto out;
> >> + }
> >> +
> >> + if (dev_priv->vbt.dsi.seq_version >= 3) {
> >> + DRM_DEBUG_KMS("GPIO element v3 not supported\n");
> >> + goto out;
> >> + }
> >
> > but here we say it's not supported. Is there more missing?
>
> The whole point of doing it this way is to support *skipping* v3 in a
> graceful manner. If I bailed out at the top, I'd have to duplicate the
> knowledge about the length of the element.
Hmm, right. But the question still stands; what more is missing for
actual v3 support?
From what I saw in the spec, the new byte is there just for Windows.
Which in itself is an utter fail on part of the spec. There's no good
reason why Windows and Linux should do things differently because that
will probably mean putting Linux on some random machine that came with
Windows won't work :(
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v2] drm/i915/dsi: skip gpio element execution when not supported
2016-02-04 17:18 ` Ville Syrjälä
@ 2016-02-04 17:22 ` Jani Nikula
2016-02-04 17:48 ` Ville Syrjälä
0 siblings, 1 reply; 36+ messages in thread
From: Jani Nikula @ 2016-02-04 17:22 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, 04 Feb 2016, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, Feb 04, 2016 at 07:10:42PM +0200, Jani Nikula wrote:
>> On Thu, 04 Feb 2016, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
>> > On Thu, Feb 04, 2016 at 06:52:47PM +0200, Jani Nikula wrote:
>> >> Skip v3 gpio element because the support is not there, and skip gpio
>> >> element on non-vlv because the sideband code is vlv specific.
>> >>
>> >> v2: the gpio stuff is currently only supported on vlv (Ville)
>> >>
>> >> Cc: drm-intel-fixes@lists.freedesktop.org
>> >> Fixes: 2a33d93486f2 ("drm/i915/bios: add support for MIPI sequence block v3")
>> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> >> ---
>> >> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 13 +++++++++++++
>> >> 1 file changed, 13 insertions(+)
>> >>
>> >> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> >> index f4d303ee538b..bcc083db7632 100644
>> >> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> >> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> >> @@ -205,6 +205,9 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>> >> struct drm_device *dev = intel_dsi->base.base.dev;
>> >> struct drm_i915_private *dev_priv = dev->dev_private;
>> >>
>> >> + if (dev_priv->vbt.dsi.seq_version >= 3)
>> >> + data++;
>> >> +
>> >
>> > So here we handle v3
>> >
>> >> gpio = *data++;
>> >>
>> >> /* pull up/down */
>> >> @@ -215,6 +218,16 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>> >> goto out;
>> >> }
>> >>
>> >> + if (!IS_VALLEYVIEW(dev_priv)) {
>> >> + DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
>> >> + goto out;
>> >> + }
>> >> +
>> >> + if (dev_priv->vbt.dsi.seq_version >= 3) {
>> >> + DRM_DEBUG_KMS("GPIO element v3 not supported\n");
>> >> + goto out;
>> >> + }
>> >
>> > but here we say it's not supported. Is there more missing?
>>
>> The whole point of doing it this way is to support *skipping* v3 in a
>> graceful manner. If I bailed out at the top, I'd have to duplicate the
>> knowledge about the length of the element.
>
> Hmm, right. But the question still stands; what more is missing for
> actual v3 support?
That's the ugly patch #8...?
> From what I saw in the spec, the new byte is there just for Windows.
> Which in itself is an utter fail on part of the spec. There's no good
> reason why Windows and Linux should do things differently because that
> will probably mean putting Linux on some random machine that came with
> Windows won't work :(
There's no disagreement here. Ugly specs lead to ugly implementations.
BR,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v2] drm/i915/dsi: skip gpio element execution when not supported
2016-02-04 17:22 ` Jani Nikula
@ 2016-02-04 17:48 ` Ville Syrjälä
0 siblings, 0 replies; 36+ messages in thread
From: Ville Syrjälä @ 2016-02-04 17:48 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Feb 04, 2016 at 07:22:30PM +0200, Jani Nikula wrote:
> On Thu, 04 Feb 2016, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Thu, Feb 04, 2016 at 07:10:42PM +0200, Jani Nikula wrote:
> >> On Thu, 04 Feb 2016, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> >> > On Thu, Feb 04, 2016 at 06:52:47PM +0200, Jani Nikula wrote:
> >> >> Skip v3 gpio element because the support is not there, and skip gpio
> >> >> element on non-vlv because the sideband code is vlv specific.
> >> >>
> >> >> v2: the gpio stuff is currently only supported on vlv (Ville)
> >> >>
> >> >> Cc: drm-intel-fixes@lists.freedesktop.org
> >> >> Fixes: 2a33d93486f2 ("drm/i915/bios: add support for MIPI sequence block v3")
> >> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> >> ---
> >> >> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 13 +++++++++++++
> >> >> 1 file changed, 13 insertions(+)
> >> >>
> >> >> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> >> >> index f4d303ee538b..bcc083db7632 100644
> >> >> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> >> >> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> >> >> @@ -205,6 +205,9 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> >> >> struct drm_device *dev = intel_dsi->base.base.dev;
> >> >> struct drm_i915_private *dev_priv = dev->dev_private;
> >> >>
> >> >> + if (dev_priv->vbt.dsi.seq_version >= 3)
> >> >> + data++;
> >> >> +
> >> >
> >> > So here we handle v3
> >> >
> >> >> gpio = *data++;
> >> >>
> >> >> /* pull up/down */
> >> >> @@ -215,6 +218,16 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> >> >> goto out;
> >> >> }
> >> >>
> >> >> + if (!IS_VALLEYVIEW(dev_priv)) {
> >> >> + DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
> >> >> + goto out;
> >> >> + }
> >> >> +
> >> >> + if (dev_priv->vbt.dsi.seq_version >= 3) {
> >> >> + DRM_DEBUG_KMS("GPIO element v3 not supported\n");
> >> >> + goto out;
> >> >> + }
> >> >
> >> > but here we say it's not supported. Is there more missing?
> >>
> >> The whole point of doing it this way is to support *skipping* v3 in a
> >> graceful manner. If I bailed out at the top, I'd have to duplicate the
> >> knowledge about the length of the element.
> >
> > Hmm, right. But the question still stands; what more is missing for
> > actual v3 support?
>
> That's the ugly patch #8...?
Ah, right it's the randomly (?) chosen gpio pin blocks split thing.
>
> > From what I saw in the spec, the new byte is there just for Windows.
> > Which in itself is an utter fail on part of the spec. There's no good
> > reason why Windows and Linux should do things differently because that
> > will probably mean putting Linux on some random machine that came with
> > Windows won't work :(
>
> There's no disagreement here. Ugly specs lead to ugly implementations.
>
> BR,
> Jani.
>
>
>
> --
> Jani Nikula, Intel Open Source Technology Center
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v2] drm/i915/dsi: skip gpio element execution when not supported
2016-02-04 16:52 ` [PATCH v2] " Jani Nikula
2016-02-04 17:05 ` Ville Syrjälä
@ 2016-02-04 17:49 ` Ville Syrjälä
2016-02-04 18:39 ` Jani Nikula
1 sibling, 1 reply; 36+ messages in thread
From: Ville Syrjälä @ 2016-02-04 17:49 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Feb 04, 2016 at 06:52:47PM +0200, Jani Nikula wrote:
> Skip v3 gpio element because the support is not there, and skip gpio
> element on non-vlv because the sideband code is vlv specific.
>
> v2: the gpio stuff is currently only supported on vlv (Ville)
>
> Cc: drm-intel-fixes@lists.freedesktop.org
> Fixes: 2a33d93486f2 ("drm/i915/bios: add support for MIPI sequence block v3")
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index f4d303ee538b..bcc083db7632 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -205,6 +205,9 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> struct drm_device *dev = intel_dsi->base.base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> + if (dev_priv->vbt.dsi.seq_version >= 3)
> + data++;
> +
> gpio = *data++;
>
> /* pull up/down */
> @@ -215,6 +218,16 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> goto out;
> }
>
> + if (!IS_VALLEYVIEW(dev_priv)) {
> + DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
> + goto out;
> + }
> +
> + if (dev_priv->vbt.dsi.seq_version >= 3) {
> + DRM_DEBUG_KMS("GPIO element v3 not supported\n");
> + goto out;
> + }
> +
> function = gtable[gpio].function_reg;
> pad = gtable[gpio].pad_reg;
>
> --
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 8/8] drm/i915/dsi: Added the generic gpio sequence support and gpio table
2016-02-04 10:50 ` [PATCH 8/8] drm/i915/dsi: Added the generic gpio sequence support and gpio table Jani Nikula
@ 2016-02-04 17:51 ` Ville Syrjälä
0 siblings, 0 replies; 36+ messages in thread
From: Ville Syrjälä @ 2016-02-04 17:51 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Feb 04, 2016 at 12:50:56PM +0200, Jani Nikula wrote:
> From: Deepak M <m.deepak@intel.com>
>
> The generic gpio is sequence is parsed from the VBT and the
> GPIO table is updated with the North core, South core and
> SUS core elements.
>
> v2: Move changes in sideband.c file to new patch(Jani), rebase
> v3: Moved the Macro`s to intel_dsi_panel_vbt.c (Jani)
>
> v3 by Jani
> - rebase on previous patches
> - don't return null on errors
>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> ---
>
> Mmmh, the gpio table actually has some pretty scary stuff. We shouldn't
> trust the vbt not to clobber some of the GPIOs listed in the table!
>
> Also, is this really vlv specific as noted by Ville? What about chv, not
> to mention bxt?!
Indeed, and IIRC during my last review I noticed that the number of pins
in each of these blocks doesn't actually match how many pins the
hardware has in theose blocks. So either this is just wrong even for VLV
or it's based on some other spec that no one has ever seen (since IIRC I
didn't see anything in the VBT spec about this stuff).
> ---
> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 589 +++++++++++++++++++++++++++--
> 1 file changed, 548 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index de1966552a33..b85d935617ef 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -59,30 +59,360 @@ static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel)
>
> #define NS_KHZ_RATIO 1000000
>
> -#define GPI0_NC_0_HV_DDI0_HPD 0x4130
> -#define GPIO_NC_0_HV_DDI0_PAD 0x4138
> -#define GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
> -#define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD 0x4128
> -#define GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
> -#define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD 0x4118
> -#define GPIO_NC_3_PANEL0_VDDEN 0x4140
> -#define GPIO_NC_3_PANEL0_VDDEN_PAD 0x4148
> -#define GPIO_NC_4_PANEL0_BLKEN 0x4150
> -#define GPIO_NC_4_PANEL0_BLKEN_PAD 0x4158
> -#define GPIO_NC_5_PANEL0_BLKCTL 0x4160
> -#define GPIO_NC_5_PANEL0_BLKCTL_PAD 0x4168
> -#define GPIO_NC_6_PCONF0 0x4180
> -#define GPIO_NC_6_PAD 0x4188
> -#define GPIO_NC_7_PCONF0 0x4190
> -#define GPIO_NC_7_PAD 0x4198
> -#define GPIO_NC_8_PCONF0 0x4170
> -#define GPIO_NC_8_PAD 0x4178
> -#define GPIO_NC_9_PCONF0 0x4100
> -#define GPIO_NC_9_PAD 0x4108
> -#define GPIO_NC_10_PCONF0 0x40E0
> -#define GPIO_NC_10_PAD 0x40E8
> -#define GPIO_NC_11_PCONF0 0x40F0
> -#define GPIO_NC_11_PAD 0x40F8
> +#define MAX_GPIO_NUM_NC 26
> +#define MAX_GPIO_NUM_SC 128
> +#define MAX_GPIO_NUM 172
> +
> +#define HV_DDI0_HPD_GPIONC_0_PCONF0 0x4130
> +#define HV_DDI0_HPD_GPIONC_0_PAD 0x4138
> +#define HV_DDI0_DDC_SDA_GPIONC_1_PCONF0 0x4120
> +#define HV_DDI0_DDC_SDA_GPIONC_1_PAD 0x4128
> +#define HV_DDI0_DDC_SCL_GPIONC_2_PCONF0 0x4110
> +#define HV_DDI0_DDC_SCL_GPIONC_2_PAD 0x4118
> +#define PANEL0_VDDEN_GPIONC_3_PCONF0 0x4140
> +#define PANEL0_VDDEN_GPIONC_3_PAD 0x4148
> +#define PANEL0_BKLTEN_GPIONC_4_PCONF0 0x4150
> +#define PANEL0_BKLTEN_GPIONC_4_PAD 0x4158
> +#define PANEL0_BKLTCTL_GPIONC_5_PCONF0 0x4160
> +#define PANEL0_BKLTCTL_GPIONC_5_PAD 0x4168
> +#define HV_DDI1_HPD_GPIONC_6_PCONF0 0x4180
> +#define HV_DDI1_HPD_GPIONC_6_PAD 0x4188
> +#define HV_DDI1_DDC_SDA_GPIONC_7_PCONF0 0x4190
> +#define HV_DDI1_DDC_SDA_GPIONC_7_PAD 0x4198
> +#define HV_DDI1_DDC_SCL_GPIONC_8_PCONF0 0x4170
> +#define HV_DDI1_DDC_SCL_GPIONC_8_PAD 0x4178
> +#define PANEL1_VDDEN_GPIONC_9_PCONF0 0x4100
> +#define PANEL1_VDDEN_GPIONC_9_PAD 0x4108
> +#define PANEL1_BKLTEN_GPIONC_10_PCONF0 0x40E0
> +#define PANEL1_BKLTEN_GPIONC_10_PAD 0x40E8
> +#define PANEL1_BKLTCTL_GPIONC_11_PCONF0 0x40F0
> +#define PANEL1_BKLTCTL_GPIONC_11_PAD 0x40F8
> +#define GP_INTD_DSI_TE1_GPIONC_12_PCONF0 0x40C0
> +#define GP_INTD_DSI_TE1_GPIONC_12_PAD 0x40C8
> +#define HV_DDI2_DDC_SDA_GPIONC_13_PCONF0 0x41A0
> +#define HV_DDI2_DDC_SDA_GPIONC_13_PAD 0x41A8
> +#define HV_DDI2_DDC_SCL_GPIONC_14_PCONF0 0x41B0
> +#define HV_DDI2_DDC_SCL_GPIONC_14_PAD 0x41B8
> +#define GP_CAMERASB00_GPIONC_15_PCONF0 0x4010
> +#define GP_CAMERASB00_GPIONC_15_PAD 0x4018
> +#define GP_CAMERASB01_GPIONC_16_PCONF0 0x4040
> +#define GP_CAMERASB01_GPIONC_16_PAD 0x4048
> +#define GP_CAMERASB02_GPIONC_17_PCONF0 0x4080
> +#define GP_CAMERASB02_GPIONC_17_PAD 0x4088
> +#define GP_CAMERASB03_GPIONC_18_PCONF0 0x40B0
> +#define GP_CAMERASB03_GPIONC_18_PAD 0x40B8
> +#define GP_CAMERASB04_GPIONC_19_PCONF0 0x4000
> +#define GP_CAMERASB04_GPIONC_19_PAD 0x4008
> +#define GP_CAMERASB05_GPIONC_20_PCONF0 0x4030
> +#define GP_CAMERASB05_GPIONC_20_PAD 0x4038
> +#define GP_CAMERASB06_GPIONC_21_PCONF0 0x4060
> +#define GP_CAMERASB06_GPIONC_21_PAD 0x4068
> +#define GP_CAMERASB07_GPIONC_22_PCONF0 0x40A0
> +#define GP_CAMERASB07_GPIONC_22_PAD 0x40A8
> +#define GP_CAMERASB08_GPIONC_23_PCONF0 0x40D0
> +#define GP_CAMERASB08_GPIONC_23_PAD 0x40D8
> +#define GP_CAMERASB09_GPIONC_24_PCONF0 0x4020
> +#define GP_CAMERASB09_GPIONC_24_PAD 0x4028
> +#define GP_CAMERASB10_GPIONC_25_PCONF0 0x4050
> +#define GP_CAMERASB10_GPIONC_25_PAD 0x4058
> +#define GP_CAMERASB11_GPIONC_26_PCONF0 0x4090
> +#define GP_CAMERASB11_GPIONC_26_PAD 0x4098
> +
> +#define SATA_GP0_GPIOC_0_PCONF0 0x4550
> +#define SATA_GP0_GPIOC_0_PAD 0x4558
> +#define SATA_GP1_GPIOC_1_PCONF0 0x4590
> +#define SATA_GP1_GPIOC_1_PAD 0x4598
> +#define SATA_LEDN_GPIOC_2_PCONF0 0x45D0
> +#define SATA_LEDN_GPIOC_2_PAD 0x45D8
> +#define PCIE_CLKREQ0B_GPIOC_3_PCONF0 0x4600
> +#define PCIE_CLKREQ0B_GPIOC_3_PAD 0x4608
> +#define PCIE_CLKREQ1B_GPIOC_4_PCONF0 0x4630
> +#define PCIE_CLKREQ1B_GPIOC_4_PAD 0x4638
> +#define PCIE_CLKREQ2B_GPIOC_5_PCONF0 0x4660
> +#define PCIE_CLKREQ2B_GPIOC_5_PAD 0x4668
> +#define PCIE_CLKREQ3B_GPIOC_6_PCONF0 0x4620
> +#define PCIE_CLKREQ3B_GPIOC_6_PAD 0x4628
> +#define PCIE_CLKREQ4B_GPIOC_7_PCONF0 0x4650
> +#define PCIE_CLKREQ4B_GPIOC_7_PAD 0x4658
> +#define HDA_RSTB_GPIOC_8_PCONF0 0x4220
> +#define HDA_RSTB_GPIOC_8_PAD 0x4228
> +#define HDA_SYNC_GPIOC_9_PCONF0 0x4250
> +#define HDA_SYNC_GPIOC_9_PAD 0x4258
> +#define HDA_CLK_GPIOC_10_PCONF0 0x4240
> +#define HDA_CLK_GPIOC_10_PAD 0x4248
> +#define HDA_SDO_GPIOC_11_PCONF0 0x4260
> +#define HDA_SDO_GPIOC_11_PAD 0x4268
> +#define HDA_SDI0_GPIOC_12_PCONF0 0x4270
> +#define HDA_SDI0_GPIOC_12_PAD 0x4278
> +#define HDA_SDI1_GPIOC_13_PCONF0 0x4230
> +#define HDA_SDI1_GPIOC_13_PAD 0x4238
> +#define HDA_DOCKRSTB_GPIOC_14_PCONF0 0x4280
> +#define HDA_DOCKRSTB_GPIOC_14_PAD 0x4288
> +#define HDA_DOCKENB_GPIOC_15_PCONF0 0x4540
> +#define HDA_DOCKENB_GPIOC_15_PAD 0x4548
> +#define SDMMC1_CLK_GPIOC_16_PCONF0 0x43E0
> +#define SDMMC1_CLK_GPIOC_16_PAD 0x43E8
> +#define SDMMC1_D0_GPIOC_17_PCONF0 0x43D0
> +#define SDMMC1_D0_GPIOC_17_PAD 0x43D8
> +#define SDMMC1_D1_GPIOC_18_PCONF0 0x4400
> +#define SDMMC1_D1_GPIOC_18_PAD 0x4408
> +#define SDMMC1_D2_GPIOC_19_PCONF0 0x43B0
> +#define SDMMC1_D2_GPIOC_19_PAD 0x43B8
> +#define SDMMC1_D3_CD_B_GPIOC_20_PCONF0 0x4360
> +#define SDMMC1_D3_CD_B_GPIOC_20_PAD 0x4368
> +#define MMC1_D4_SD_WE_GPIOC_21_PCONF0 0x4380
> +#define MMC1_D4_SD_WE_GPIOC_21_PAD 0x4388
> +#define MMC1_D5_GPIOC_22_PCONF0 0x43C0
> +#define MMC1_D5_GPIOC_22_PAD 0x43C8
> +#define MMC1_D6_GPIOC_23_PCONF0 0x4370
> +#define MMC1_D6_GPIOC_23_PAD 0x4378
> +#define MMC1_D7_GPIOC_24_PCONF0 0x43F0
> +#define MMC1_D7_GPIOC_24_PAD 0x43F8
> +#define SDMMC1_CMD_GPIOC_25_PCONF0 0x4390
> +#define SDMMC1_CMD_GPIOC_25_PAD 0x4398
> +#define MMC1_RESET_B_GPIOC_26_PCONF0 0x4330
> +#define MMC1_RESET_B_GPIOC_26_PAD 0x4338
> +#define SDMMC2_CLK_GPIOC_27_PCONF0 0x4320
> +#define SDMMC2_CLK_GPIOC_27_PAD 0x4328
> +#define SDMMC2_D0_GPIOC_28_PCONF0 0x4350
> +#define SDMMC2_D0_GPIOC_28_PAD 0x4358
> +#define SDMMC2_D1_GPIOC_29_PCONF0 0x42F0
> +#define SDMMC2_D1_GPIOC_29_PAD 0x42F8
> +#define SDMMC2_D2_GPIOC_30_PCONF0 0x4340
> +#define SDMMC2_D2_GPIOC_30_PAD 0x4348
> +#define SDMMC2_D3_CD_B_GPIOC_31_PCONF0 0x4310
> +#define SDMMC2_D3_CD_B_GPIOC_31_PAD 0x4318
> +#define SDMMC2_CMD_GPIOC_32_PCONF0 0x4300
> +#define SDMMC2_CMD_GPIOC_32_PAD 0x4308
> +#define SDMMC3_CLK_GPIOC_33_PCONF0 0x42B0
> +#define SDMMC3_CLK_GPIOC_33_PAD 0x42B8
> +#define SDMMC3_D0_GPIOC_34_PCONF0 0x42E0
> +#define SDMMC3_D0_GPIOC_34_PAD 0x42E8
> +#define SDMMC3_D1_GPIOC_35_PCONF0 0x4290
> +#define SDMMC3_D1_GPIOC_35_PAD 0x4298
> +#define SDMMC3_D2_GPIOC_36_PCONF0 0x42D0
> +#define SDMMC3_D2_GPIOC_36_PAD 0x42D8
> +#define SDMMC3_D3_GPIOC_37_PCONF0 0x42A0
> +#define SDMMC3_D3_GPIOC_37_PAD 0x42A8
> +#define SDMMC3_CD_B_GPIOC_38_PCONF0 0x43A0
> +#define SDMMC3_CD_B_GPIOC_38_PAD 0x43A8
> +#define SDMMC3_CMD_GPIOC_39_PCONF0 0x42C0
> +#define SDMMC3_CMD_GPIOC_39_PAD 0x42C8
> +#define SDMMC3_1P8_EN_GPIOC_40_PCONF0 0x45F0
> +#define SDMMC3_1P8_EN_GPIOC_40_PAD 0x45F8
> +#define SDMMC3_PWR_EN_B_GPIOC_41_PCONF0 0x4690
> +#define SDMMC3_PWR_EN_B_GPIOC_41_PAD 0x4698
> +#define LPC_AD0_GPIOC_42_PCONF0 0x4460
> +#define LPC_AD0_GPIOC_42_PAD 0x4468
> +#define LPC_AD1_GPIOC_43_PCONF0 0x4440
> +#define LPC_AD1_GPIOC_43_PAD 0x4448
> +#define LPC_AD2_GPIOC_44_PCONF0 0x4430
> +#define LPC_AD2_GPIOC_44_PAD 0x4438
> +#define LPC_AD3_GPIOC_45_PCONF0 0x4420
> +#define LPC_AD3_GPIOC_45_PAD 0x4428
> +#define LPC_FRAMEB_GPIOC_46_PCONF0 0x4450
> +#define LPC_FRAMEB_GPIOC_46_PAD 0x4458
> +#define LPC_CLKOUT0_GPIOC_47_PCONF0 0x4470
> +#define LPC_CLKOUT0_GPIOC_47_PAD 0x4478
> +#define LPC_CLKOUT1_GPIOC_48_PCONF0 0x4410
> +#define LPC_CLKOUT1_GPIOC_48_PAD 0x4418
> +#define LPC_CLKRUNB_GPIOC_49_PCONF0 0x4480
> +#define LPC_CLKRUNB_GPIOC_49_PAD 0x4488
> +#define ILB_SERIRQ_GPIOC_50_PCONF0 0x4560
> +#define ILB_SERIRQ_GPIOC_50_PAD 0x4568
> +#define SMB_DATA_GPIOC_51_PCONF0 0x45A0
> +#define SMB_DATA_GPIOC_51_PAD 0x45A8
> +#define SMB_CLK_GPIOC_52_PCONF0 0x4580
> +#define SMB_CLK_GPIOC_52_PAD 0x4588
> +#define SMB_ALERTB_GPIOC_53_PCONF0 0x45C0
> +#define SMB_ALERTB_GPIOC_53_PAD 0x45C8
> +#define SPKR_GPIOC_54_PCONF0 0x4670
> +#define SPKR_GPIOC_54_PAD 0x4678
> +#define MHSI_ACDATA_GPIOC_55_PCONF0 0x44D0
> +#define MHSI_ACDATA_GPIOC_55_PAD 0x44D8
> +#define MHSI_ACFLAG_GPIOC_56_PCONF0 0x44F0
> +#define MHSI_ACFLAG_GPIOC_56_PAD 0x44F8
> +#define MHSI_ACREADY_GPIOC_57_PCONF0 0x4530
> +#define MHSI_ACREADY_GPIOC_57_PAD 0x4538
> +#define MHSI_ACWAKE_GPIOC_58_PCONF0 0x44E0
> +#define MHSI_ACWAKE_GPIOC_58_PAD 0x44E8
> +#define MHSI_CADATA_GPIOC_59_PCONF0 0x4510
> +#define MHSI_CADATA_GPIOC_59_PAD 0x4518
> +#define MHSI_CAFLAG_GPIOC_60_PCONF0 0x4500
> +#define MHSI_CAFLAG_GPIOC_60_PAD 0x4508
> +#define MHSI_CAREADY_GPIOC_61_PCONF0 0x4520
> +#define MHSI_CAREADY_GPIOC_61_PAD 0x4528
> +#define GP_SSP_2_CLK_GPIOC_62_PCONF0 0x40D0
> +#define GP_SSP_2_CLK_GPIOC_62_PAD 0x40D8
> +#define GP_SSP_2_FS_GPIOC_63_PCONF0 0x40C0
> +#define GP_SSP_2_FS_GPIOC_63_PAD 0x40C8
> +#define GP_SSP_2_RXD_GPIOC_64_PCONF0 0x40F0
> +#define GP_SSP_2_RXD_GPIOC_64_PAD 0x40F8
> +#define GP_SSP_2_TXD_GPIOC_65_PCONF0 0x40E0
> +#define GP_SSP_2_TXD_GPIOC_65_PAD 0x40E8
> +#define SPI1_CS0_B_GPIOC_66_PCONF0 0x4110
> +#define SPI1_CS0_B_GPIOC_66_PAD 0x4118
> +#define SPI1_MISO_GPIOC_67_PCONF0 0x4120
> +#define SPI1_MISO_GPIOC_67_PAD 0x4128
> +#define SPI1_MOSI_GPIOC_68_PCONF0 0x4130
> +#define SPI1_MOSI_GPIOC_68_PAD 0x4138
> +#define SPI1_CLK_GPIOC_69_PCONF0 0x4100
> +#define SPI1_CLK_GPIOC_69_PAD 0x4108
> +#define UART1_RXD_GPIOC_70_PCONF0 0x4020
> +#define UART1_RXD_GPIOC_70_PAD 0x4028
> +#define UART1_TXD_GPIOC_71_PCONF0 0x4010
> +#define UART1_TXD_GPIOC_71_PAD 0x4018
> +#define UART1_RTS_B_GPIOC_72_PCONF0 0x4000
> +#define UART1_RTS_B_GPIOC_72_PAD 0x4008
> +#define UART1_CTS_B_GPIOC_73_PCONF0 0x4040
> +#define UART1_CTS_B_GPIOC_73_PAD 0x4048
> +#define UART2_RXD_GPIOC_74_PCONF0 0x4060
> +#define UART2_RXD_GPIOC_74_PAD 0x4068
> +#define UART2_TXD_GPIOC_75_PCONF0 0x4070
> +#define UART2_TXD_GPIOC_75_PAD 0x4078
> +#define UART2_RTS_B_GPIOC_76_PCONF0 0x4090
> +#define UART2_RTS_B_GPIOC_76_PAD 0x4098
> +#define UART2_CTS_B_GPIOC_77_PCONF0 0x4080
> +#define UART2_CTS_B_GPIOC_77_PAD 0x4088
> +#define I2C0_SDA_GPIOC_78_PCONF0 0x4210
> +#define I2C0_SDA_GPIOC_78_PAD 0x4218
> +#define I2C0_SCL_GPIOC_79_PCONF0 0x4200
> +#define I2C0_SCL_GPIOC_79_PAD 0x4208
> +#define I2C1_SDA_GPIOC_80_PCONF0 0x41F0
> +#define I2C1_SDA_GPIOC_80_PAD 0x41F8
> +#define I2C1_SCL_GPIOC_81_PCONF0 0x41E0
> +#define I2C1_SCL_GPIOC_81_PAD 0x41E8
> +#define I2C2_SDA_GPIOC_82_PCONF0 0x41D0
> +#define I2C2_SDA_GPIOC_82_PAD 0x41D8
> +#define I2C2_SCL_GPIOC_83_PCONF0 0x41B0
> +#define I2C2_SCL_GPIOC_83_PAD 0x41B8
> +#define I2C3_SDA_GPIOC_84_PCONF0 0x4190
> +#define I2C2_SCL_GPIOC_83_PAD 0x41B8
> +#define I2C3_SDA_GPIOC_84_PCONF0 0x4190
> +#define I2C3_SDA_GPIOC_84_PAD 0x4198
> +#define I2C3_SCL_GPIOC_85_PCONF0 0x41C0
> +#define I2C3_SCL_GPIOC_85_PAD 0x41C8
> +#define I2C4_SDA_GPIOC_86_PCONF0 0x41A0
> +#define I2C4_SDA_GPIOC_86_PAD 0x41A8
> +#define I2C4_SCL_GPIOC_87_PCONF0 0x4170
> +#define I2C4_SCL_GPIOC_87_PAD 0x4178
> +#define I2C5_SDA_GPIOC_88_PCONF0 0x4150
> +#define I2C5_SDA_GPIOC_88_PAD 0x4158
> +#define I2C5_SCL_GPIOC_89_PCONF0 0x4140
> +#define I2C5_SCL_GPIOC_89_PAD 0x4148
> +#define I2C6_SDA_GPIOC_90_PCONF0 0x4180
> +#define I2C6_SDA_GPIOC_90_PAD 0x4188
> +#define I2C6_SCL_GPIOC_91_PCONF0 0x4160
> +#define I2C6_SCL_GPIOC_91_PAD 0x4168
> +#define I2C_NFC_SDA_GPIOC_92_PCONF0 0x4050
> +#define I2C_NFC_SDA_GPIOC_92_PAD 0x4058
> +#define I2C_NFC_SCL_GPIOC_93_PCONF0 0x4030
> +#define I2C_NFC_SCL_GPIOC_93_PAD 0x4038
> +#define PWM0_GPIOC_94_PCONF0 0x40A0
> +#define PWM0_GPIOC_94_PAD 0x40A8
> +#define PWM1_GPIOC_95_PCONF0 0x40B0
> +#define PWM1_GPIOC_95_PAD 0x40B8
> +#define PLT_CLK0_GPIOC_96_PCONF0 0x46A0
> +#define PLT_CLK0_GPIOC_96_PAD 0x46A8
> +#define PLT_CLK1_GPIOC_97_PCONF0 0x4570
> +#define PLT_CLK1_GPIOC_97_PAD 0x4578
> +#define PLT_CLK2_GPIOC_98_PCONF0 0x45B0
> +#define PLT_CLK2_GPIOC_98_PAD 0x45B8
> +#define PLT_CLK3_GPIOC_99_PCONF0 0x4680
> +#define PLT_CLK3_GPIOC_99_PAD 0x4688
> +#define PLT_CLK4_GPIOC_100_PCONF0 0x4610
> +#define PLT_CLK4_GPIOC_100_PAD 0x4618
> +#define PLT_CLK5_GPIOC_101_PCONF0 0x4640
> +#define PLT_CLK5_GPIOC_101_PAD 0x4648
> +
> +#define GPIO_SUS0_GPIO_SUS0_PCONF0 0x41D0
> +#define GPIO_SUS0_GPIO_SUS0_PAD 0x41D8
> +#define GPIO_SUS1_GPIO_SUS1_PCONF0 0x4210
> +#define GPIO_SUS1_GPIO_SUS1_PAD 0x4218
> +#define GPIO_SUS2_GPIO_SUS2_PCONF0 0x41E0
> +#define GPIO_SUS2_GPIO_SUS2_PAD 0x41E8
> +#define GPIO_SUS3_GPIO_SUS3_PCONF0 0x41F0
> +#define GPIO_SUS3_GPIO_SUS3_PAD 0x41F8
> +#define GPIO_SUS4_GPIO_SUS4_PCONF0 0x4200
> +#define GPIO_SUS4_GPIO_SUS4_PAD 0x4208
> +#define GPIO_SUS5_GPIO_SUS5_PCONF0 0x4220
> +#define GPIO_SUS5_GPIO_SUS5_PAD 0x4228
> +#define GPIO_SUS6_GPIO_SUS6_PCONF0 0x4240
> +#define GPIO_SUS6_GPIO_SUS6_PAD 0x4248
> +#define GPIO_SUS7_GPIO_SUS7_PCONF0 0x4230
> +#define GPIO_SUS7_GPIO_SUS7_PAD 0x4238
> +#define SEC_GPIO_SUS8_GPIO_SUS8_PCONF0 0x4260
> +#define SEC_GPIO_SUS8_GPIO_SUS8_PAD 0x4268
> +#define SEC_GPIO_SUS9_GPIO_SUS9_PCONF0 0x4250
> +#define SEC_GPIO_SUS9_GPIO_SUS9_PAD 0x4258
> +#define SEC_GPIO_SUS10_GPIO_SUS10_PCONF0 0x4120
> +#define SEC_GPIO_SUS10_GPIO_SUS10_PAD 0x4128
> +#define SUSPWRDNACK_GPIOS_11_PCONF0 0x4070
> +#define SUSPWRDNACK_GPIOS_11_PAD 0x4078
> +#define PMU_SUSCLK_GPIOS_12_PCONF0 0x40B0
> +#define PMU_SUSCLK_GPIOS_12_PAD 0x40B8
> +#define PMU_SLP_S0IX_B_GPIOS_13_PCONF0 0x4140
> +#define PMU_SLP_S0IX_B_GPIOS_13_PAD 0x4148
> +#define PMU_SLP_LAN_B_GPIOS_14_PCONF0 0x4110
> +#define PMU_SLP_LAN_B_GPIOS_14_PAD 0x4118
> +#define PMU_WAKE_B_GPIOS_15_PCONF0 0x4010
> +#define PMU_WAKE_B_GPIOS_15_PAD 0x4018
> +#define PMU_PWRBTN_B_GPIOS_16_PCONF0 0x4080
> +#define PMU_PWRBTN_B_GPIOS_16_PAD 0x4088
> +#define PMU_WAKE_LAN_B_GPIOS_17_PCONF0 0x40A0
> +#define PMU_WAKE_LAN_B_GPIOS_17_PAD 0x40A8
> +#define SUS_STAT_B_GPIOS_18_PCONF0 0x4130
> +#define SUS_STAT_B_GPIOS_18_PAD 0x4138
> +#define USB_OC0_B_GPIOS_19_PCONF0 0x40C0
> +#define USB_OC0_B_GPIOS_19_PAD 0x40C8
> +#define USB_OC1_B_GPIOS_20_PCONF0 0x4000
> +#define USB_OC1_B_GPIOS_20_PAD 0x4008
> +#define SPI_CS1_B_GPIOS_21_PCONF0 0x4020
> +#define SPI_CS1_B_GPIOS_21_PAD 0x4028
> +#define GPIO_DFX0_GPIOS_22_PCONF0 0x4170
> +#define GPIO_DFX0_GPIOS_22_PAD 0x4178
> +#define GPIO_DFX1_GPIOS_23_PCONF0 0x4270
> +#define GPIO_DFX1_GPIOS_23_PAD 0x4278
> +#define GPIO_DFX2_GPIOS_24_PCONF0 0x41C0
> +#define GPIO_DFX2_GPIOS_24_PAD 0x41C8
> +#define GPIO_DFX3_GPIOS_25_PCONF0 0x41B0
> +#define GPIO_DFX3_GPIOS_25_PAD 0x41B8
> +#define GPIO_DFX4_GPIOS_26_PCONF0 0x4160
> +#define GPIO_DFX4_GPIOS_26_PAD 0x4168
> +#define GPIO_DFX5_GPIOS_27_PCONF0 0x4150
> +#define GPIO_DFX5_GPIOS_27_PAD 0x4158
> +#define GPIO_DFX6_GPIOS_28_PCONF0 0x4180
> +#define GPIO_DFX6_GPIOS_28_PAD 0x4188
> +#define GPIO_DFX7_GPIOS_29_PCONF0 0x4190
> +#define GPIO_DFX7_GPIOS_29_PAD 0x4198
> +#define GPIO_DFX8_GPIOS_30_PCONF0 0x41A0
> +#define GPIO_DFX8_GPIOS_30_PAD 0x41A8
> +#define USB_ULPI_0_CLK_GPIOS_31_PCONF0 0x4330
> +#define USB_ULPI_0_CLK_GPIOS_31_PAD 0x4338
> +#define USB_ULPI_0_DATA0_GPIOS_32_PCONF0 0x4380
> +#define USB_ULPI_0_DATA0_GPIOS_32_PAD 0x4388
> +#define USB_ULPI_0_DATA1_GPIOS_33_PCONF0 0x4360
> +#define USB_ULPI_0_DATA1_GPIOS_33_PAD 0x4368
> +#define USB_ULPI_0_DATA2_GPIOS_34_PCONF0 0x4310
> +#define USB_ULPI_0_DATA2_GPIOS_34_PAD 0x4318
> +#define USB_ULPI_0_DATA3_GPIOS_35_PCONF0 0x4370
> +#define USB_ULPI_0_DATA3_GPIOS_35_PAD 0x4378
> +#define USB_ULPI_0_DATA4_GPIOS_36_PCONF0 0x4300
> +#define USB_ULPI_0_DATA4_GPIOS_36_PAD 0x4308
> +#define USB_ULPI_0_DATA5_GPIOS_37_PCONF0 0x4390
> +#define USB_ULPI_0_DATA5_GPIOS_37_PAD 0x4398
> +#define USB_ULPI_0_DATA6_GPIOS_38_PCONF0 0x4320
> +#define USB_ULPI_0_DATA6_GPIOS_38_PAD 0x4328
> +#define USB_ULPI_0_DATA7_GPIOS_39_PCONF0 0x43A0
> +#define USB_ULPI_0_DATA7_GPIOS_39_PAD 0x43A8
> +#define USB_ULPI_0_DIR_GPIOS_40_PCONF0 0x4340
> +#define USB_ULPI_0_DIR_GPIOS_40_PAD 0x4348
> +#define USB_ULPI_0_NXT_GPIOS_41_PCONF0 0x4350
> +#define USB_ULPI_0_NXT_GPIOS_41_PAD 0x4358
> +#define USB_ULPI_0_STP_GPIOS_42_PCONF0 0x43B0
> +#define USB_ULPI_0_STP_GPIOS_42_PAD 0x43B8
> +#define USB_ULPI_0_REFCLK_GPIOS_43_PCONF0 0x4280
> +#define USB_ULPI_0_REFCLK_GPIOS_43_PAD 0x4288
>
> struct gpio_table {
> u16 function_reg;
> @@ -91,18 +421,181 @@ struct gpio_table {
> };
>
> static struct gpio_table gtable[] = {
> - { GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 },
> - { GPIO_NC_1_HV_DDI0_DDC_SDA, GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 },
> - { GPIO_NC_2_HV_DDI0_DDC_SCL, GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 },
> - { GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD, 0 },
> - { GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0 },
> - { GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0 },
> - { GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 },
> - { GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 },
> - { GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 },
> - { GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 },
> - { GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0},
> - { GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
> + { HV_DDI0_HPD_GPIONC_0_PCONF0, HV_DDI0_HPD_GPIONC_0_PAD, 0},
> + { HV_DDI0_DDC_SDA_GPIONC_1_PCONF0, HV_DDI0_DDC_SDA_GPIONC_1_PAD, 0},
> + { HV_DDI0_DDC_SCL_GPIONC_2_PCONF0, HV_DDI0_DDC_SCL_GPIONC_2_PAD, 0},
> + { PANEL0_VDDEN_GPIONC_3_PCONF0, PANEL0_VDDEN_GPIONC_3_PAD, 0},
> + { PANEL0_BKLTEN_GPIONC_4_PCONF0, PANEL0_BKLTEN_GPIONC_4_PAD, 0},
> + { PANEL0_BKLTCTL_GPIONC_5_PCONF0, PANEL0_BKLTCTL_GPIONC_5_PAD, 0},
> + { HV_DDI1_HPD_GPIONC_6_PCONF0, HV_DDI1_HPD_GPIONC_6_PAD, 0},
> + { HV_DDI1_DDC_SDA_GPIONC_7_PCONF0, HV_DDI1_DDC_SDA_GPIONC_7_PAD, 0},
> + { HV_DDI1_DDC_SCL_GPIONC_8_PCONF0, HV_DDI1_DDC_SCL_GPIONC_8_PAD, 0},
> + { PANEL1_VDDEN_GPIONC_9_PCONF0, PANEL1_VDDEN_GPIONC_9_PAD, 0},
> + { PANEL1_BKLTEN_GPIONC_10_PCONF0, PANEL1_BKLTEN_GPIONC_10_PAD, 0},
> + { PANEL1_BKLTCTL_GPIONC_11_PCONF0, PANEL1_BKLTCTL_GPIONC_11_PAD, 0},
> + { GP_INTD_DSI_TE1_GPIONC_12_PCONF0, GP_INTD_DSI_TE1_GPIONC_12_PAD, 0},
> + { HV_DDI2_DDC_SDA_GPIONC_13_PCONF0, HV_DDI2_DDC_SDA_GPIONC_13_PAD, 0},
> + { HV_DDI2_DDC_SCL_GPIONC_14_PCONF0, HV_DDI2_DDC_SCL_GPIONC_14_PAD, 0},
> + { GP_CAMERASB00_GPIONC_15_PCONF0, GP_CAMERASB00_GPIONC_15_PAD, 0},
> + { GP_CAMERASB01_GPIONC_16_PCONF0, GP_CAMERASB01_GPIONC_16_PAD, 0},
> + { GP_CAMERASB02_GPIONC_17_PCONF0, GP_CAMERASB02_GPIONC_17_PAD, 0},
> + { GP_CAMERASB03_GPIONC_18_PCONF0, GP_CAMERASB03_GPIONC_18_PAD, 0},
> + { GP_CAMERASB04_GPIONC_19_PCONF0, GP_CAMERASB04_GPIONC_19_PAD, 0},
> + { GP_CAMERASB05_GPIONC_20_PCONF0, GP_CAMERASB05_GPIONC_20_PAD, 0},
> + { GP_CAMERASB06_GPIONC_21_PCONF0, GP_CAMERASB06_GPIONC_21_PAD, 0},
> + { GP_CAMERASB07_GPIONC_22_PCONF0, GP_CAMERASB07_GPIONC_22_PAD, 0},
> + { GP_CAMERASB08_GPIONC_23_PCONF0, GP_CAMERASB08_GPIONC_23_PAD, 0},
> + { GP_CAMERASB09_GPIONC_24_PCONF0, GP_CAMERASB09_GPIONC_24_PAD, 0},
> + { GP_CAMERASB10_GPIONC_25_PCONF0, GP_CAMERASB10_GPIONC_25_PAD, 0},
> + { GP_CAMERASB11_GPIONC_26_PCONF0, GP_CAMERASB11_GPIONC_26_PAD, 0},
> +
> + { SATA_GP0_GPIOC_0_PCONF0, SATA_GP0_GPIOC_0_PAD, 0},
> + { SATA_GP1_GPIOC_1_PCONF0, SATA_GP1_GPIOC_1_PAD, 0},
> + { SATA_LEDN_GPIOC_2_PCONF0, SATA_LEDN_GPIOC_2_PAD, 0},
> + { PCIE_CLKREQ0B_GPIOC_3_PCONF0, PCIE_CLKREQ0B_GPIOC_3_PAD, 0},
> + { PCIE_CLKREQ1B_GPIOC_4_PCONF0, PCIE_CLKREQ1B_GPIOC_4_PAD, 0},
> + { PCIE_CLKREQ2B_GPIOC_5_PCONF0, PCIE_CLKREQ2B_GPIOC_5_PAD, 0},
> + { PCIE_CLKREQ3B_GPIOC_6_PCONF0, PCIE_CLKREQ3B_GPIOC_6_PAD, 0},
> + { PCIE_CLKREQ4B_GPIOC_7_PCONF0, PCIE_CLKREQ4B_GPIOC_7_PAD, 0},
> + { HDA_RSTB_GPIOC_8_PCONF0, HDA_RSTB_GPIOC_8_PAD, 0},
> + { HDA_SYNC_GPIOC_9_PCONF0, HDA_SYNC_GPIOC_9_PAD, 0},
> + { HDA_CLK_GPIOC_10_PCONF0, HDA_CLK_GPIOC_10_PAD, 0},
> + { HDA_SDO_GPIOC_11_PCONF0, HDA_SDO_GPIOC_11_PAD, 0},
> + { HDA_SDI0_GPIOC_12_PCONF0, HDA_SDI0_GPIOC_12_PAD, 0},
> + { HDA_SDI1_GPIOC_13_PCONF0, HDA_SDI1_GPIOC_13_PAD, 0},
> + { HDA_DOCKRSTB_GPIOC_14_PCONF0, HDA_DOCKRSTB_GPIOC_14_PAD, 0},
> + { HDA_DOCKENB_GPIOC_15_PCONF0, HDA_DOCKENB_GPIOC_15_PAD, 0},
> + { SDMMC1_CLK_GPIOC_16_PCONF0, SDMMC1_CLK_GPIOC_16_PAD, 0},
> + { SDMMC1_D0_GPIOC_17_PCONF0, SDMMC1_D0_GPIOC_17_PAD, 0},
> + { SDMMC1_D1_GPIOC_18_PCONF0, SDMMC1_D1_GPIOC_18_PAD, 0},
> + { SDMMC1_D2_GPIOC_19_PCONF0, SDMMC1_D2_GPIOC_19_PAD, 0},
> + { SDMMC1_D3_CD_B_GPIOC_20_PCONF0, SDMMC1_D3_CD_B_GPIOC_20_PAD, 0},
> + { MMC1_D4_SD_WE_GPIOC_21_PCONF0, MMC1_D4_SD_WE_GPIOC_21_PAD, 0},
> + { MMC1_D5_GPIOC_22_PCONF0, MMC1_D5_GPIOC_22_PAD, 0},
> + { MMC1_D6_GPIOC_23_PCONF0, MMC1_D6_GPIOC_23_PAD, 0},
> + { MMC1_D7_GPIOC_24_PCONF0, MMC1_D7_GPIOC_24_PAD, 0},
> + { SDMMC1_CMD_GPIOC_25_PCONF0, SDMMC1_CMD_GPIOC_25_PAD, 0},
> + { MMC1_RESET_B_GPIOC_26_PCONF0, MMC1_RESET_B_GPIOC_26_PAD, 0},
> + { SDMMC2_CLK_GPIOC_27_PCONF0, SDMMC2_CLK_GPIOC_27_PAD, 0},
> + { SDMMC2_D0_GPIOC_28_PCONF0, SDMMC2_D0_GPIOC_28_PAD, 0},
> + { SDMMC2_D1_GPIOC_29_PCONF0, SDMMC2_D1_GPIOC_29_PAD, 0},
> + { SDMMC2_D2_GPIOC_30_PCONF0, SDMMC2_D2_GPIOC_30_PAD, 0},
> + { SDMMC2_D3_CD_B_GPIOC_31_PCONF0, SDMMC2_D3_CD_B_GPIOC_31_PAD, 0},
> + { SDMMC2_CMD_GPIOC_32_PCONF0, SDMMC2_CMD_GPIOC_32_PAD, 0},
> + { SDMMC3_CLK_GPIOC_33_PCONF0, SDMMC3_CLK_GPIOC_33_PAD, 0},
> + { SDMMC3_D0_GPIOC_34_PCONF0, SDMMC3_D0_GPIOC_34_PAD, 0},
> + { SDMMC3_D1_GPIOC_35_PCONF0, SDMMC3_D1_GPIOC_35_PAD, 0},
> + { SDMMC3_D2_GPIOC_36_PCONF0, SDMMC3_D2_GPIOC_36_PAD, 0},
> + { SDMMC3_D3_GPIOC_37_PCONF0, SDMMC3_D3_GPIOC_37_PAD, 0},
> + { SDMMC3_CD_B_GPIOC_38_PCONF0, SDMMC3_CD_B_GPIOC_38_PAD, 0},
> + { SDMMC3_CMD_GPIOC_39_PCONF0, SDMMC3_CMD_GPIOC_39_PAD, 0},
> + { SDMMC3_1P8_EN_GPIOC_40_PCONF0, SDMMC3_1P8_EN_GPIOC_40_PAD, 0},
> + { SDMMC3_PWR_EN_B_GPIOC_41_PCONF0, SDMMC3_PWR_EN_B_GPIOC_41_PAD, 0},
> + { LPC_AD0_GPIOC_42_PCONF0, LPC_AD0_GPIOC_42_PAD, 0},
> + { LPC_AD1_GPIOC_43_PCONF0, LPC_AD1_GPIOC_43_PAD, 0},
> + { LPC_AD2_GPIOC_44_PCONF0, LPC_AD2_GPIOC_44_PAD, 0},
> + { LPC_AD3_GPIOC_45_PCONF0, LPC_AD3_GPIOC_45_PAD, 0},
> + { LPC_FRAMEB_GPIOC_46_PCONF0, LPC_FRAMEB_GPIOC_46_PAD, 0},
> + { LPC_CLKOUT0_GPIOC_47_PCONF0, LPC_CLKOUT0_GPIOC_47_PAD, 0},
> + { LPC_CLKOUT1_GPIOC_48_PCONF0, LPC_CLKOUT1_GPIOC_48_PAD, 0},
> + { LPC_CLKRUNB_GPIOC_49_PCONF0, LPC_CLKRUNB_GPIOC_49_PAD, 0},
> + { ILB_SERIRQ_GPIOC_50_PCONF0, ILB_SERIRQ_GPIOC_50_PAD, 0},
> + { SMB_DATA_GPIOC_51_PCONF0, SMB_DATA_GPIOC_51_PAD, 0},
> + { SMB_CLK_GPIOC_52_PCONF0, SMB_CLK_GPIOC_52_PAD, 0},
> + { SMB_ALERTB_GPIOC_53_PCONF0, SMB_ALERTB_GPIOC_53_PAD, 0},
> + { SPKR_GPIOC_54_PCONF0, SPKR_GPIOC_54_PAD, 0},
> + { MHSI_ACDATA_GPIOC_55_PCONF0, MHSI_ACDATA_GPIOC_55_PAD, 0},
> + { MHSI_ACFLAG_GPIOC_56_PCONF0, MHSI_ACFLAG_GPIOC_56_PAD, 0},
> + { MHSI_ACREADY_GPIOC_57_PCONF0, MHSI_ACREADY_GPIOC_57_PAD, 0},
> + { MHSI_ACWAKE_GPIOC_58_PCONF0, MHSI_ACWAKE_GPIOC_58_PAD, 0},
> + { MHSI_CADATA_GPIOC_59_PCONF0, MHSI_CADATA_GPIOC_59_PAD, 0},
> + { MHSI_CAFLAG_GPIOC_60_PCONF0, MHSI_CAFLAG_GPIOC_60_PAD, 0},
> + { MHSI_CAREADY_GPIOC_61_PCONF0, MHSI_CAREADY_GPIOC_61_PAD, 0},
> + { GP_SSP_2_CLK_GPIOC_62_PCONF0, GP_SSP_2_CLK_GPIOC_62_PAD, 0},
> + { GP_SSP_2_FS_GPIOC_63_PCONF0, GP_SSP_2_FS_GPIOC_63_PAD, 0},
> + { GP_SSP_2_RXD_GPIOC_64_PCONF0, GP_SSP_2_RXD_GPIOC_64_PAD, 0},
> + { GP_SSP_2_TXD_GPIOC_65_PCONF0, GP_SSP_2_TXD_GPIOC_65_PAD, 0},
> + { SPI1_CS0_B_GPIOC_66_PCONF0, SPI1_CS0_B_GPIOC_66_PAD, 0},
> + { SPI1_MISO_GPIOC_67_PCONF0, SPI1_MISO_GPIOC_67_PAD, 0},
> + { SPI1_MOSI_GPIOC_68_PCONF0, SPI1_MOSI_GPIOC_68_PAD, 0},
> + { SPI1_CLK_GPIOC_69_PCONF0, SPI1_CLK_GPIOC_69_PAD, 0},
> + { UART1_RXD_GPIOC_70_PCONF0, UART1_RXD_GPIOC_70_PAD, 0},
> + { UART1_TXD_GPIOC_71_PCONF0, UART1_TXD_GPIOC_71_PAD, 0},
> + { UART1_RTS_B_GPIOC_72_PCONF0, UART1_RTS_B_GPIOC_72_PAD, 0},
> + { UART1_CTS_B_GPIOC_73_PCONF0, UART1_CTS_B_GPIOC_73_PAD, 0},
> + { UART2_RXD_GPIOC_74_PCONF0, UART2_RXD_GPIOC_74_PAD, 0},
> + { UART2_TXD_GPIOC_75_PCONF0, UART2_TXD_GPIOC_75_PAD, 0},
> + { UART2_RTS_B_GPIOC_76_PCONF0, UART2_RTS_B_GPIOC_76_PAD, 0},
> + { UART2_CTS_B_GPIOC_77_PCONF0, UART2_CTS_B_GPIOC_77_PAD, 0},
> + { I2C0_SDA_GPIOC_78_PCONF0, I2C0_SDA_GPIOC_78_PAD, 0},
> + { I2C0_SCL_GPIOC_79_PCONF0, I2C0_SCL_GPIOC_79_PAD, 0},
> + { I2C1_SDA_GPIOC_80_PCONF0, I2C1_SDA_GPIOC_80_PAD, 0},
> + { I2C1_SCL_GPIOC_81_PCONF0, I2C1_SCL_GPIOC_81_PAD, 0},
> + { I2C2_SDA_GPIOC_82_PCONF0, I2C2_SDA_GPIOC_82_PAD, 0},
> + { I2C2_SCL_GPIOC_83_PCONF0, I2C2_SCL_GPIOC_83_PAD, 0},
> + { I2C3_SDA_GPIOC_84_PCONF0, I2C3_SDA_GPIOC_84_PAD, 0},
> + { I2C3_SCL_GPIOC_85_PCONF0, I2C3_SCL_GPIOC_85_PAD, 0},
> + { I2C4_SDA_GPIOC_86_PCONF0, I2C4_SDA_GPIOC_86_PAD, 0},
> + { I2C4_SCL_GPIOC_87_PCONF0, I2C4_SCL_GPIOC_87_PAD, 0},
> + { I2C5_SDA_GPIOC_88_PCONF0, I2C5_SDA_GPIOC_88_PAD, 0},
> + { I2C5_SCL_GPIOC_89_PCONF0, I2C5_SCL_GPIOC_89_PAD, 0},
> + { I2C6_SDA_GPIOC_90_PCONF0, I2C6_SDA_GPIOC_90_PAD, 0},
> + { I2C6_SCL_GPIOC_91_PCONF0, I2C6_SCL_GPIOC_91_PAD, 0},
> + { I2C_NFC_SDA_GPIOC_92_PCONF0, I2C_NFC_SDA_GPIOC_92_PAD, 0},
> + { I2C_NFC_SCL_GPIOC_93_PCONF0, I2C_NFC_SCL_GPIOC_93_PAD, 0},
> + { PWM0_GPIOC_94_PCONF0, PWM0_GPIOC_94_PAD, 0},
> + { PWM1_GPIOC_95_PCONF0, PWM1_GPIOC_95_PAD, 0},
> + { PLT_CLK0_GPIOC_96_PCONF0, PLT_CLK0_GPIOC_96_PAD, 0},
> + { PLT_CLK1_GPIOC_97_PCONF0, PLT_CLK1_GPIOC_97_PAD, 0},
> + { PLT_CLK2_GPIOC_98_PCONF0, PLT_CLK2_GPIOC_98_PAD, 0},
> + { PLT_CLK3_GPIOC_99_PCONF0, PLT_CLK3_GPIOC_99_PAD, 0},
> + { PLT_CLK4_GPIOC_100_PCONF0, PLT_CLK4_GPIOC_100_PAD, 0},
> + { PLT_CLK5_GPIOC_101_PCONF0, PLT_CLK5_GPIOC_101_PAD, 0},
> +
> + { GPIO_SUS0_GPIO_SUS0_PCONF0, GPIO_SUS0_GPIO_SUS0_PAD, 0},
> + { GPIO_SUS1_GPIO_SUS1_PCONF0, GPIO_SUS1_GPIO_SUS1_PAD, 0},
> + { GPIO_SUS2_GPIO_SUS2_PCONF0, GPIO_SUS2_GPIO_SUS2_PAD, 0},
> + { GPIO_SUS3_GPIO_SUS3_PCONF0, GPIO_SUS3_GPIO_SUS3_PAD, 0},
> + { GPIO_SUS4_GPIO_SUS4_PCONF0, GPIO_SUS4_GPIO_SUS4_PAD, 0},
> + { GPIO_SUS5_GPIO_SUS5_PCONF0, GPIO_SUS5_GPIO_SUS5_PAD, 0},
> + { GPIO_SUS6_GPIO_SUS6_PCONF0, GPIO_SUS6_GPIO_SUS6_PAD, 0},
> + { GPIO_SUS7_GPIO_SUS7_PCONF0, GPIO_SUS7_GPIO_SUS7_PAD, 0},
> + { SEC_GPIO_SUS8_GPIO_SUS8_PCONF0, SEC_GPIO_SUS8_GPIO_SUS8_PAD, 0},
> + { SEC_GPIO_SUS9_GPIO_SUS9_PCONF0, SEC_GPIO_SUS9_GPIO_SUS9_PAD, 0},
> + { SEC_GPIO_SUS10_GPIO_SUS10_PCONF0, SEC_GPIO_SUS10_GPIO_SUS10_PAD, 0},
> + { SUSPWRDNACK_GPIOS_11_PCONF0, SUSPWRDNACK_GPIOS_11_PAD, 0},
> + { PMU_SUSCLK_GPIOS_12_PCONF0, PMU_SUSCLK_GPIOS_12_PAD, 0},
> + { PMU_SLP_S0IX_B_GPIOS_13_PCONF0, PMU_SLP_S0IX_B_GPIOS_13_PAD, 0},
> + { PMU_SLP_LAN_B_GPIOS_14_PCONF0, PMU_SLP_LAN_B_GPIOS_14_PAD, 0},
> + { PMU_WAKE_B_GPIOS_15_PCONF0, PMU_WAKE_B_GPIOS_15_PAD, 0},
> + { PMU_PWRBTN_B_GPIOS_16_PCONF0, PMU_PWRBTN_B_GPIOS_16_PAD, 0},
> + { PMU_WAKE_LAN_B_GPIOS_17_PCONF0, PMU_WAKE_LAN_B_GPIOS_17_PAD, 0},
> + { SUS_STAT_B_GPIOS_18_PCONF0, SUS_STAT_B_GPIOS_18_PAD, 0},
> + { USB_OC0_B_GPIOS_19_PCONF0, USB_OC0_B_GPIOS_19_PAD, 0},
> + { USB_OC1_B_GPIOS_20_PCONF0, USB_OC1_B_GPIOS_20_PAD, 0},
> + { SPI_CS1_B_GPIOS_21_PCONF0, SPI_CS1_B_GPIOS_21_PAD, 0},
> + { GPIO_DFX0_GPIOS_22_PCONF0, GPIO_DFX0_GPIOS_22_PAD, 0},
> + { GPIO_DFX1_GPIOS_23_PCONF0, GPIO_DFX1_GPIOS_23_PAD, 0},
> + { GPIO_DFX2_GPIOS_24_PCONF0, GPIO_DFX2_GPIOS_24_PAD, 0},
> + { GPIO_DFX3_GPIOS_25_PCONF0, GPIO_DFX3_GPIOS_25_PAD, 0},
> + { GPIO_DFX4_GPIOS_26_PCONF0, GPIO_DFX4_GPIOS_26_PAD, 0},
> + { GPIO_DFX5_GPIOS_27_PCONF0, GPIO_DFX5_GPIOS_27_PAD, 0},
> + { GPIO_DFX6_GPIOS_28_PCONF0, GPIO_DFX6_GPIOS_28_PAD, 0},
> + { GPIO_DFX7_GPIOS_29_PCONF0, GPIO_DFX7_GPIOS_29_PAD, 0},
> + { GPIO_DFX8_GPIOS_30_PCONF0, GPIO_DFX8_GPIOS_30_PAD, 0},
> + { USB_ULPI_0_CLK_GPIOS_31_PCONF0, USB_ULPI_0_CLK_GPIOS_31_PAD, 0},
> + { USB_ULPI_0_DATA0_GPIOS_32_PCONF0, USB_ULPI_0_DATA0_GPIOS_32_PAD, 0},
> + { USB_ULPI_0_DATA1_GPIOS_33_PCONF0, USB_ULPI_0_DATA1_GPIOS_33_PAD, 0},
> + { USB_ULPI_0_DATA2_GPIOS_34_PCONF0, USB_ULPI_0_DATA2_GPIOS_34_PAD, 0},
> + { USB_ULPI_0_DATA3_GPIOS_35_PCONF0, USB_ULPI_0_DATA3_GPIOS_35_PAD, 0},
> + { USB_ULPI_0_DATA4_GPIOS_36_PCONF0, USB_ULPI_0_DATA4_GPIOS_36_PAD, 0},
> + { USB_ULPI_0_DATA5_GPIOS_37_PCONF0, USB_ULPI_0_DATA5_GPIOS_37_PAD, 0},
> + { USB_ULPI_0_DATA6_GPIOS_38_PCONF0, USB_ULPI_0_DATA6_GPIOS_38_PAD, 0},
> + { USB_ULPI_0_DATA7_GPIOS_39_PCONF0, USB_ULPI_0_DATA7_GPIOS_39_PAD, 0},
> + { USB_ULPI_0_DIR_GPIOS_40_PCONF0, USB_ULPI_0_DIR_GPIOS_40_PAD, 0},
> + { USB_ULPI_0_NXT_GPIOS_41_PCONF0, USB_ULPI_0_NXT_GPIOS_41_PAD, 0},
> + { USB_ULPI_0_STP_GPIOS_42_PCONF0, USB_ULPI_0_STP_GPIOS_42_PAD, 0},
> + { USB_ULPI_0_REFCLK_GPIOS_43_PCONF0, USB_ULPI_0_REFCLK_GPIOS_43_PAD, 0}
> };
>
> static inline enum port intel_dsi_seq_port_to_port(u8 port)
> @@ -202,6 +695,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> u8 gpio, action;
> u16 function, pad;
> u32 val;
> + u8 port;
> struct drm_device *dev = intel_dsi->base.base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> @@ -224,8 +718,22 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> }
>
> if (dev_priv->vbt.dsi.seq_version >= 3) {
> - DRM_DEBUG_KMS("GPIO element v3 not supported\n");
> - goto out;
> + if (gpio <= MAX_GPIO_NUM_NC) {
> + DRM_DEBUG_KMS("GPIO is in the north block\n");
> + port = IOSF_PORT_GPIO_NC;
> + } else if (gpio > MAX_GPIO_NUM_NC && gpio <= MAX_GPIO_NUM_SC) {
> + DRM_DEBUG_KMS("GPIO is in the south block\n");
> + port = IOSF_PORT_GPIO_SC;
> + } else if (gpio > MAX_GPIO_NUM_SC && gpio <= MAX_GPIO_NUM) {
> + DRM_DEBUG_KMS("GPIO is in the SUS block\n");
> + port = IOSF_PORT_GPIO_SUS;
> + } else {
> + DRM_DEBUG_KMS("GPIO %u is in unknown range\n", gpio);
> + goto out;
> + }
> + } else {
> + /* XXX: Per spec, sequence block v2 also supports SC. */
> + port = IOSF_PORT_GPIO_NC;
> }
>
> function = gtable[gpio].function_reg;
> @@ -235,15 +743,14 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> if (!gtable[gpio].init) {
> /* program the function */
> /* FIXME: remove constant below */
> - vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, function,
> - 0x2000CC00);
> + vlv_iosf_sb_write(dev_priv, port, function, 0x2000CC00);
> gtable[gpio].init = 1;
> }
>
> val = 0x4 | action;
>
> /* pull up/down */
> - vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, pad, val);
> + vlv_iosf_sb_write(dev_priv, port, pad, val);
> mutex_unlock(&dev_priv->sb_lock);
>
> out:
> --
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v2] drm/i915/dsi: skip gpio element execution when not supported
2016-02-04 17:49 ` Ville Syrjälä
@ 2016-02-04 18:39 ` Jani Nikula
0 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2016-02-04 18:39 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, 04 Feb 2016, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, Feb 04, 2016 at 06:52:47PM +0200, Jani Nikula wrote:
>> Skip v3 gpio element because the support is not there, and skip gpio
>> element on non-vlv because the sideband code is vlv specific.
>>
>> v2: the gpio stuff is currently only supported on vlv (Ville)
>>
>> Cc: drm-intel-fixes@lists.freedesktop.org
>> Fixes: 2a33d93486f2 ("drm/i915/bios: add support for MIPI sequence block v3")
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
And pushed to dinq, thanks for the review.
BR,
Jani.
>
>> ---
>> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 13 +++++++++++++
>> 1 file changed, 13 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> index f4d303ee538b..bcc083db7632 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> @@ -205,6 +205,9 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>> struct drm_device *dev = intel_dsi->base.base.dev;
>> struct drm_i915_private *dev_priv = dev->dev_private;
>>
>> + if (dev_priv->vbt.dsi.seq_version >= 3)
>> + data++;
>> +
>> gpio = *data++;
>>
>> /* pull up/down */
>> @@ -215,6 +218,16 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>> goto out;
>> }
>>
>> + if (!IS_VALLEYVIEW(dev_priv)) {
>> + DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
>> + goto out;
>> + }
>> +
>> + if (dev_priv->vbt.dsi.seq_version >= 3) {
>> + DRM_DEBUG_KMS("GPIO element v3 not supported\n");
>> + goto out;
>> + }
>> +
>> function = gtable[gpio].function_reg;
>> pad = gtable[gpio].pad_reg;
>>
>> --
>> 2.1.4
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/dsi: i2c/gpio (rev3)
2016-02-04 10:50 [PATCH 0/8] drm/i915/dsi: i2c/gpio Jani Nikula
` (8 preceding siblings ...)
2016-02-04 12:46 ` ✓ Fi.CI.BAT: success for drm/i915/dsi: i2c/gpio Patchwork
@ 2016-02-05 7:31 ` Patchwork
9 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2016-02-05 7:31 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Summary ==
Series 3075v3 drm/i915/dsi: i2c/gpio
2016-02-04T16:55:25.384210 http://patchwork.freedesktop.org/api/1.0/series/3075/revisions/3/mbox/
Applying: drm/i915/dsi: defend gpio table against out of bounds access
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
Applying: drm/i915/dsi: don't pass arbitrary data to sideband
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
Patch failed at 0002 drm/i915/dsi: don't pass arbitrary data to sideband
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^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 3/8] drm/i915: Adding the parsing logic for the i2c element
2016-02-04 16:36 ` Ville Syrjälä
@ 2016-02-15 16:48 ` Daniel Vetter
0 siblings, 0 replies; 36+ messages in thread
From: Daniel Vetter @ 2016-02-15 16:48 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Jani Nikula, intel-gfx
On Thu, Feb 04, 2016 at 06:36:22PM +0200, Ville Syrjälä wrote:
> On Thu, Feb 04, 2016 at 06:21:23PM +0200, Jani Nikula wrote:
> > On Thu, 04 Feb 2016, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > > On Thu, Feb 04, 2016 at 12:50:51PM +0200, Jani Nikula wrote:
> > >> From: vkorjani <vikas.korjani@intel.com>
> > >>
> > >> New sequence element for i2c is been added in the
> > >> mipi sequence block of the VBT. This patch parses
> > >> and executes the i2c sequence.
> > >>
> > >> v2: Add i2c_put_adapter call(Jani), rebase
> > >>
> > >> v3: corrected the retry loop(Jani), rebase
> > >>
> > >> v4 by Jani:
> > >> - don't put the adapter if get fails
> > >> - print an error message if all retries exhausted
> > >> - use a for loop
> > >> - fix warnings for unused variables
> > >>
> > >> v5 by Jani:
> > >> - rebase on the skip i2c element patch
> > >>
> > >> v6: by Jani:
> > >> - ignore the gmbus i2c elements (Ville)
> > >>
> > >> Signed-off-by: vkorjani <vikas.korjani@intel.com>
> > >> Signed-off-by: Deepak M <m.deepak@intel.com>
> > >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> > >> ---
> > >> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 64 ++++++++++++++++++++++++++++--
> > >> 1 file changed, 61 insertions(+), 3 deletions(-)
> > >>
> > >> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > >> index 6f013efba45b..f4d303ee538b 100644
> > >> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > >> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > >> @@ -31,6 +31,7 @@
> > >> #include <drm/drm_panel.h>
> > >> #include <linux/slab.h>
> > >> #include <video/mipi_display.h>
> > >> +#include <linux/i2c.h>
> > >> #include <asm/intel-mid.h>
> > >> #include <video/mipi_display.h>
> > >> #include "i915_drv.h"
> > >> @@ -235,9 +236,66 @@ out:
> > >> return data;
> > >> }
> > >>
> > >> -static const u8 *mipi_exec_i2c_skip(struct intel_dsi *intel_dsi, const u8 *data)
> > >> +static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
> > >> {
> > >> - return data + *(data + 6) + 7;
> > >> + struct i2c_adapter *adapter;
> > >> + int ret, i;
> > >> + u8 reg_offset, payload_size;
> > >> + struct i2c_msg msg;
> > >> + u8 *transmit_buffer;
> > >> + u8 flag, resource_id, bus_number;
> > >> + u16 slave_add;
> > >> +
> > >> + flag = *data++;
> > >> + resource_id = *data++;
> > >> + bus_number = *data++;
> > >> + slave_add = *(u16 *)(data);
> > >> + data += 2;
> > >> + reg_offset = *data++;
> > >> + payload_size = *data++;
> > >> +
> > >> + if (resource_id == 0xff || bus_number == 0xff) {
> > >> + DRM_DEBUG_KMS("ignoring gmbus (resource id %02x, bus %02x)\n",
> > >> + resource_id, bus_number);
> > >> + goto out;
> > >> + }
> > >> +
> > >
> > > Still missing the check for __i2c_first_dynamic_bus_num which I think
> > > would at least provide some kind of half arsed protection against
> > > something not registering these magic i2c busses.
> >
> > I meant to reply to that part of the review but forgot.
> >
> > Problem is, we'd have to include drivers/i2c/i2c-core.h directly, which
> > also has this warning,
> >
> > /* These symbols are exported ONLY FOR the i2c core.
> > * No other users will be supported.
> > */
> >
> > and there are no users outside of drivers/i2c. I'm quite reluctant to
> > add that.
>
> The we need some other way to look up the adapter. Passing in
> essentially random adapter numbers could give us more or less
> any i2c bus on the system, and if we go poke there we could do
> real damage.
>
> The whole scheme is very poorly thoght out I think. There really
> should be some kind of ACPI ID or something that lets us look up
> exactly the right thing.
Agreed this is super fragile, but we should at least try to make sure we
don't end up getting some random dynamic i2c adapter. Maybe add an
i2c_get_board_adapter or similar, which does this check in the i2c core?
Definitely need to pull in the i2c maintainers here (and help them with
avoid hair-pulling exercises on their end ...).
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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^ permalink raw reply [flat|nested] 36+ messages in thread
end of thread, other threads:[~2016-02-15 16:48 UTC | newest]
Thread overview: 36+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-02-04 10:50 [PATCH 0/8] drm/i915/dsi: i2c/gpio Jani Nikula
2016-02-04 10:50 ` [PATCH 1/8] drm/i915/dsi: defend gpio table against out of bounds access Jani Nikula
2016-02-04 15:40 ` Ville Syrjälä
2016-02-04 10:50 ` [PATCH 2/8] drm/i915/dsi: don't pass arbitrary data to sideband Jani Nikula
2016-02-04 15:41 ` Ville Syrjälä
2016-02-04 16:56 ` Jani Nikula
2016-02-04 10:50 ` [PATCH 3/8] drm/i915: Adding the parsing logic for the i2c element Jani Nikula
2016-02-04 15:28 ` Ville Syrjälä
2016-02-04 16:21 ` Jani Nikula
2016-02-04 16:36 ` Ville Syrjälä
2016-02-15 16:48 ` Daniel Vetter
2016-02-04 10:50 ` [PATCH 4/8] drm/i915/dsi: skip gpio element execution when not supported Jani Nikula
2016-02-04 15:36 ` Ville Syrjälä
2016-02-04 16:52 ` [PATCH v2] " Jani Nikula
2016-02-04 17:05 ` Ville Syrjälä
2016-02-04 17:10 ` Jani Nikula
2016-02-04 17:12 ` Jani Nikula
2016-02-04 17:18 ` Ville Syrjälä
2016-02-04 17:22 ` Jani Nikula
2016-02-04 17:48 ` Ville Syrjälä
2016-02-04 17:49 ` Ville Syrjälä
2016-02-04 18:39 ` Jani Nikula
2016-02-04 10:50 ` [PATCH 5/8] drm/i915: put the IOSF port defines in numerical order Jani Nikula
2016-02-04 16:05 ` Ville Syrjälä
2016-02-04 10:50 ` [PATCH 6/8] drm/i915/vlv: drop unused vlv_gps_core_read/write functions Jani Nikula
2016-02-04 16:12 ` Ville Syrjälä
2016-02-04 16:57 ` Jani Nikula
2016-02-04 10:50 ` [PATCH 7/8] drm/i915: Extend gpio read/write to other cores Jani Nikula
2016-02-04 15:39 ` Ville Syrjälä
2016-02-04 16:55 ` [PATCH v5] " Jani Nikula
2016-02-04 17:03 ` Ville Syrjälä
2016-02-04 17:14 ` Jani Nikula
2016-02-04 10:50 ` [PATCH 8/8] drm/i915/dsi: Added the generic gpio sequence support and gpio table Jani Nikula
2016-02-04 17:51 ` Ville Syrjälä
2016-02-04 12:46 ` ✓ Fi.CI.BAT: success for drm/i915/dsi: i2c/gpio Patchwork
2016-02-05 7:31 ` ✗ Fi.CI.BAT: failure for drm/i915/dsi: i2c/gpio (rev3) Patchwork
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