From: Marek Vasut <marex@denx.de>
To: Patrick DELAUNAY <patrick.delaunay@foss.st.com>, u-boot@lists.denx.de
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Subject: Re: [PATCH] ram: stm32mp1: Conditionally enable ASR
Date: Thu, 14 Apr 2022 19:34:30 +0200 [thread overview]
Message-ID: <641bd43c-c2f4-d1a8-7a67-1a2f0039dcfb@denx.de> (raw)
In-Reply-To: <f699e3ec-6c22-7ddf-f6c7-147452709ce5@denx.de>
On 4/14/22 18:48, Marek Vasut wrote:
> On 4/14/22 18:37, Patrick DELAUNAY wrote:
>> Hi Marek,
>
> Hi,
>
>> on ST platform the ASR/SSR/HSR request are already provided by the DDR
>> settings with pwrctl register value
>>
>> it is managed in TF-A by
>>
>> arm-trusted-firmware/drivers/st/ddr/stm32mp1_ddr_helpers.c
>
> Sure, I don't use ATF and I have no intention of ever using ATF on this
> platform.
>
>> enumstm32mp1_ddr_sr_mode ddr_read_sr_mode(void)
>> {
>> uint32_tpwrctl = mmio_read_32(stm32mp_ddrctrl_base() + DDRCTRL_PWRCTL);
>> switch(pwrctl & (DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE |
>> DDRCTRL_PWRCTL_SELFREF_EN)) {
>> case0U:
>> returnDDR_SSR_MODE;
>> caseDDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE:
>> returnDDR_HSR_MODE;
>> caseDDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE | DDRCTRL_PWRCTL_SELFREF_EN:
>> returnDDR_ASR_MODE;
>> default:
>> returnDDR_SR_MODE_INVALID;
>> }
>> }
>>
>> no need to add an other property
>
> This is for U-Boot, plain, stock, without any other software partaking
> in it.
Note that this patch just reinstates the old behavior before v2022.04
release, except it adds a DT property to enable the new behavior with
ASR and makes it non-default.
next prev parent reply other threads:[~2022-04-14 17:34 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-13 2:49 [PATCH] ram: stm32mp1: Conditionally enable ASR Marek Vasut
2022-04-14 16:37 ` Patrick DELAUNAY
2022-04-14 16:48 ` Marek Vasut
2022-04-14 17:34 ` Marek Vasut [this message]
2022-04-26 10:49 ` Patrick DELAUNAY
2022-04-26 11:27 ` Patrick DELAUNAY
2022-04-22 7:57 ` Patrice CHOTARD
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