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[204.210.126.223]) by smtp.gmail.com with ESMTPSA id k189sm36567300pgk.14.2021.07.22.23.29.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 22 Jul 2021 23:29:09 -0700 (PDT) Subject: Re: [PATCH v2 16/22] target/loongarch: Add floating point move instruction translation To: Song Gao , qemu-devel@nongnu.org References: <1626861198-6133-1-git-send-email-gaosong@loongson.cn> <1626861198-6133-17-git-send-email-gaosong@loongson.cn> From: Richard Henderson Message-ID: <643a7954-cf1c-78dd-2d08-f0969ea6127e@linaro.org> Date: Thu, 22 Jul 2021 20:29:05 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <1626861198-6133-17-git-send-email-gaosong@loongson.cn> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.203, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, thuth@redhat.com, chenhuacai@gmail.com, philmd@redhat.com, yangxiaojuan@loongson.cn, laurent@vivier.eu, maobibo@loongson.cn, alistair.francis@wdc.com, pbonzini@redhat.com, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 7/20/21 11:53 PM, Song Gao wrote: > This patch implement floationg point move instruction translation. > > This includes: > - FMOV.{S/D} > - FSEL > - MOVGR2FR.{W/D}, MOVGR2FRH.W > - MOVFR2GR.{S/D}, MOVFRH2GR.S > - MOVGR2FCSR, MOVFCSR2GR > - MOVFR2CF, MOVCF2FR > - MOVGR2CF, MOVCF2GR > > Signed-off-by: Song Gao > --- > target/loongarch/fpu_helper.c | 80 +++++++++++++ > target/loongarch/helper.h | 6 + > target/loongarch/insns.decode | 41 +++++++ > target/loongarch/trans.inc.c | 270 ++++++++++++++++++++++++++++++++++++++++++ > 4 files changed, 397 insertions(+) > > diff --git a/target/loongarch/fpu_helper.c b/target/loongarch/fpu_helper.c > index 162085a..7662715 100644 > --- a/target/loongarch/fpu_helper.c > +++ b/target/loongarch/fpu_helper.c > @@ -379,6 +379,11 @@ uint64_t helper_fp_logb_d(CPULoongArchState *env, uint64_t fp) > return fp1; > } > > +void helper_movreg2cf(CPULoongArchState *env, uint32_t cd, target_ulong src) > +{ > + env->active_fpu.cf[cd & 0x7] = src & 0x1; > +} tcg_gen_andi_tl + tcg_gen_st8_tl. > +target_ulong helper_fsel(CPULoongArchState *env, target_ulong fj, > + target_ulong fk, uint32_t ca) > +{ > + if (env->active_fpu.cf[ca & 0x7]) { > + return fk; > + } else { > + return fj; > + } > +} tcg_gen_movcond_i64. > +void helper_movgr2fcsr(CPULoongArchState *env, target_ulong arg1, > + uint32_t fcsr) > +{ > + switch (fcsr) { > + case 0: > + env->active_fpu.fcsr0 = arg1; > + break; > + case 1: > + env->active_fpu.fcsr0 = (arg1 & FCSR0_M1) | > + (env->active_fpu.fcsr0 & ~FCSR0_M1); > + break; > + case 2: > + env->active_fpu.fcsr0 = (arg1 & FCSR0_M2) | > + (env->active_fpu.fcsr0 & ~FCSR0_M2); > + break; > + case 3: > + env->active_fpu.fcsr0 = (arg1 & FCSR0_M3) | > + (env->active_fpu.fcsr0 & ~FCSR0_M3); > + break; This is easily implemented inline, followed by a single helper call to re-load the rounding mode (if required by the mask). > + case 16: > + env->active_fpu.vcsr16 = arg1; > + break; The documentation I have does not describe the vector stuff? > + default: > + printf("%s: warning, fcsr '%d' not supported\n", __func__, fcsr); > + assert(0); > + break; No printfs, no assert. This should have been caught by > +target_ulong helper_movcf2reg(CPULoongArchState *env, uint32_t cj) > +{ > + return (target_ulong)env->active_fpu.cf[cj & 0x7]; > +} tcg_gen_ld8u_tl. r~