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Thu, 2 Sep 2021 10:57:25 +0000 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 2 Sep 2021 10:57:24 +0000 Received: from [10.26.49.12] (172.20.187.6) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 2 Sep 2021 10:57:21 +0000 Subject: Re: [PATCH v3 2/4] dmaengine: tegra: Add tegra gpcdma driver From: Jon Hunter To: Akhil R , CC: , , , , , , , , , Pavan Kunapuli References: <1630044294-21169-1-git-send-email-akhilrajeev@nvidia.com> <1630044294-21169-3-git-send-email-akhilrajeev@nvidia.com> <4f0293e1-01de-8735-40e7-0622d185188a@nvidia.com> Message-ID: <64505970-1d68-b4cb-490b-7bfa1c842a1f@nvidia.com> Date: Thu, 2 Sep 2021 11:57:19 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <4f0293e1-01de-8735-40e7-0622d185188a@nvidia.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To DRHQMAIL107.nvidia.com (10.27.9.16) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: eba119a5-5e3f-4cdd-dc4c-08d96e0072b0 X-MS-TrafficTypeDiagnostic: DM4PR12MB5376: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Sep 2021 10:57:25.1715 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eba119a5-5e3f-4cdd-dc4c-08d96e0072b0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.35];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT061.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5376 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org On 01/09/2021 21:56, Jon Hunter wrote: > > On 27/08/2021 07:04, Akhil R wrote: >> Adding GPC DMA controller driver for Tegra186 and Tegra194. The driver >> supports dma transfers between memory to memory, IO peripheral to memory >> and memory to IO peripheral. >> >> Signed-off-by: Pavan Kunapuli >> Signed-off-by: Rajesh Gumasta >> Signed-off-by: Akhil R >> --- >>   drivers/dma/Kconfig         |   12 + >>   drivers/dma/Makefile        |    1 + >>   drivers/dma/tegra-gpc-dma.c | 1343 >> +++++++++++++++++++++++++++++++++++++++++++ >>   3 files changed, 1356 insertions(+) >>   create mode 100644 drivers/dma/tegra-gpc-dma.c ... >> +static int tegra_dma_terminate_all(struct dma_chan *dc) >> +{ >> +    struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); >> +    unsigned long wcount = 0; >> +    unsigned long status; >> +    unsigned long flags; >> +    bool was_busy; >> +    int err; >> + >> +    raw_spin_lock_irqsave(&tdc->lock, flags); >> + >> +    if (!tdc->dma_desc) { >> +        raw_spin_unlock_irqrestore(&tdc->lock, flags); >> +        return 0; >> +    } >> + >> +    if (!tdc->busy) >> +        goto skip_dma_stop; >> + >> +    if (tdc->tdma->chip_data->hw_support_pause) { >> +        err = tegra_dma_pause(tdc); >> +        if (err) { >> +            raw_spin_unlock_irqrestore(&tdc->lock, flags); >> +            return err; >> +        } >> +    } else { >> +        /* Before Reading DMA status to figure out number >> +         * of bytes transferred by DMA channel: >> +         * Change the client associated with the DMA channel >> +         * to stop DMA engine from starting any more bursts for >> +         * the given client and wait for in flight bursts to complete >> +         */ >> +        tegra_dma_reset_client(tdc); >> + >> +        /* Wait for in flight data transfer to finish */ >> +        udelay(TEGRA_GPCDMA_BURST_COMPLETE_TIME); >> + >> +        /* If TX/RX path is still active wait till it becomes >> +         * inactive >> +         */ >> + >> +        if (readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + >> +                tdc->chan_base_offset + >> +                TEGRA_GPCDMA_CHAN_STATUS, >> +                status, >> +                !(status & (TEGRA_GPCDMA_STATUS_CHANNEL_TX | >> +                TEGRA_GPCDMA_STATUS_CHANNEL_RX)), >> +                5, >> +                TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT)) { >> +            dev_dbg(tdc2dev(tdc), "Timeout waiting for DMA burst >> completion!\n"); >> +            tegra_dma_dump_chan_regs(tdc); >> +        } > > I would be tempted to make the code in the 'else' clause > tegra_dma_sw_pause(). Then you could have tegra_dma_hw_pause() and > tegra_dma_sw_pause(). Thinking some more tegra_dma_hw_pause() and tegra_dma_sw_pause() it not very clear/accurate. I would be tempted to call these tegra_dma_pause() and tegra_dma_stop_client() or tegra_dma_stop_transactions(), because without having a proper hardware pause, you are simply ignoring the client sync events. Jon -- nvpublic