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From: Michal Simek <michal.simek@xilinx.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 24/40] arm64: zynqmp: Update device tree for pinmux
Date: Mon,  6 Nov 2017 13:12:56 +0100	[thread overview]
Message-ID: <646966b0268f93fe6c8d9e2860efce1ec1ac941f.1509970359.git.michal.simek@xilinx.com> (raw)
In-Reply-To: <cover.1509970359.git.michal.simek@xilinx.com>

Added pin control support in device tree for zynqmp.

Signed-off-by: Chirag Parekh <chirag.parekh@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 arch/arm/dts/zynqmp-zcu102-revA.dts          | 289 +++++++++++++++++++++++++++
 arch/arm/dts/zynqmp.dtsi                     |   6 +
 include/dt-bindings/pinctrl/pinctrl-zynqmp.h |  30 +++
 3 files changed, 325 insertions(+)
 create mode 100644 include/dt-bindings/pinctrl/pinctrl-zynqmp.h

diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 66dc110a964c..eb361b00362a 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -13,6 +13,7 @@
 #include "zynqmp.dtsi"
 #include "zynqmp-clk.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
 
 / {
 	model = "ZynqMP ZCU102 RevA";
@@ -68,6 +69,8 @@
 
 &can1 {
 	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_can1_default>;
 };
 
 &dcc {
@@ -120,6 +123,8 @@
 	status = "okay";
 	phy-handle = <&phy0>;
 	phy-mode = "rgmii-id";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gem3_default>;
 	phy0: phy at 21 {
 		reg = <21>;
 		ti,rx-internal-delay = <0x8>;
@@ -130,6 +135,8 @@
 
 &gpio {
 	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpio_default>;
 };
 
 &gpu {
@@ -139,6 +146,11 @@
 &i2c0 {
 	status = "okay";
 	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c0_default>;
+	pinctrl-1 = <&pinctrl_i2c0_gpio>;
+	scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 
 	tca6416_u97: gpio at 20 {
 		/*
@@ -400,6 +412,12 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 &i2c1 {
 	status = "okay";
 	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1_default>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
+
 	/* FIXME PL i2c via PCA9306 - u45 */
 	/* FIXME MSP430 - u41 - not detected */
 	i2cswitch at 74 { /* u34 */
@@ -549,6 +567,269 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 	};
 };
 
+&pinctrl0 {
+	status = "okay";
+	pinctrl_i2c0_default: i2c0-default {
+		mux {
+			groups = "i2c0_3_grp";
+			function = "i2c0";
+		};
+
+		conf {
+			groups = "i2c0_3_grp";
+			bias-pull-up;
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+		};
+	};
+
+	pinctrl_i2c0_gpio: i2c0-gpio {
+		mux {
+			groups = "gpio0_14_grp", "gpio0_15_grp";
+			function = "gpio0";
+		};
+
+		conf {
+			groups = "gpio0_14_grp", "gpio0_15_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+		};
+	};
+
+	pinctrl_i2c1_default: i2c1-default {
+		mux {
+			groups = "i2c1_4_grp";
+			function = "i2c1";
+		};
+
+		conf {
+			groups = "i2c1_4_grp";
+			bias-pull-up;
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+		};
+	};
+
+	pinctrl_i2c1_gpio: i2c1-gpio {
+		mux {
+			groups = "gpio0_16_grp", "gpio0_17_grp";
+			function = "gpio0";
+		};
+
+		conf {
+			groups = "gpio0_16_grp", "gpio0_17_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+		};
+	};
+
+	pinctrl_uart0_default: uart0-default {
+		mux {
+			groups = "uart0_4_grp";
+			function = "uart0";
+		};
+
+		conf {
+			groups = "uart0_4_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+		};
+
+		conf-rx {
+			pins = "MIO18";
+			bias-high-impedance;
+		};
+
+		conf-tx {
+			pins = "MIO19";
+			bias-disable;
+		};
+	};
+
+	pinctrl_uart1_default: uart1-default {
+		mux {
+			groups = "uart1_5_grp";
+			function = "uart1";
+		};
+
+		conf {
+			groups = "uart1_5_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+		};
+
+		conf-rx {
+			pins = "MIO21";
+			bias-high-impedance;
+		};
+
+		conf-tx {
+			pins = "MIO20";
+			bias-disable;
+		};
+	};
+
+	pinctrl_usb0_default: usb0-default {
+		mux {
+			groups = "usb0_0_grp";
+			function = "usb0";
+		};
+
+		conf {
+			groups = "usb0_0_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+		};
+
+		conf-rx {
+			pins = "MIO52", "MIO53", "MIO55";
+			bias-high-impedance;
+		};
+
+		conf-tx {
+			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+			       "MIO60", "MIO61", "MIO62", "MIO63";
+			bias-disable;
+		};
+	};
+
+	pinctrl_gem3_default: gem3-default {
+		mux {
+			function = "ethernet3";
+			groups = "ethernet3_0_grp";
+		};
+
+		conf {
+			groups = "ethernet3_0_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+		};
+
+		conf-rx {
+			pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
+									"MIO75";
+			bias-high-impedance;
+			low-power-disable;
+		};
+
+		conf-tx {
+			pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
+									"MIO69";
+			bias-disable;
+			low-power-enable;
+		};
+
+		mux-mdio {
+			function = "mdio3";
+			groups = "mdio3_0_grp";
+		};
+
+		conf-mdio {
+			groups = "mdio3_0_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+			bias-disable;
+		};
+	};
+
+	pinctrl_can1_default: can1-default {
+		mux {
+			function = "can1";
+			groups = "can1_6_grp";
+		};
+
+		conf {
+			groups = "can1_6_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+		};
+
+		conf-rx {
+			pins = "MIO25";
+			bias-high-impedance;
+		};
+
+		conf-tx {
+			pins = "MIO24";
+			bias-disable;
+		};
+	};
+
+	pinctrl_sdhci1_default: sdhci1-default {
+		mux {
+			groups = "sdio1_0_grp";
+			function = "sdio1";
+		};
+
+		conf {
+			groups = "sdio1_0_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+			bias-disable;
+		};
+
+		mux-cd {
+			groups = "sdio1_0_cd_grp";
+			function = "sdio1_cd";
+		};
+
+		conf-cd {
+			groups = "sdio1_0_cd_grp";
+			bias-high-impedance;
+			bias-pull-up;
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+		};
+
+		mux-wp {
+			groups = "sdio1_0_wp_grp";
+			function = "sdio1_wp";
+		};
+
+		conf-wp {
+			groups = "sdio1_0_wp_grp";
+			bias-high-impedance;
+			bias-pull-up;
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+		};
+	};
+
+	pinctrl_gpio_default: gpio-default {
+		mux-sw {
+			function = "gpio0";
+			groups = "gpio0_22_grp", "gpio0_23_grp";
+		};
+
+		conf-sw {
+			groups = "gpio0_22_grp", "gpio0_23_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+		};
+
+		mux-msp {
+			function = "gpio0";
+			groups = "gpio0_13_grp", "gpio0_38_grp";
+		};
+
+		conf-msp {
+			groups = "gpio0_13_grp", "gpio0_38_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+		};
+
+		conf-pull-up {
+			pins = "MIO22", "MIO23";
+			bias-pull-up;
+		};
+
+		conf-pull-none {
+			pins = "MIO13", "MIO38";
+			bias-disable;
+		};
+	};
+};
+
 &pcie {
 	status = "okay";
 };
@@ -603,21 +884,29 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 /* SD1 with level shifter */
 &sdhci1 {
 	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sdhci1_default>;
 	no-1-8-v;	/* for 1.0 silicon */
 	xlnx,mio_bank = <1>;
 };
 
 &uart0 {
 	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart0_default>;
 };
 
 &uart1 {
 	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1_default>;
 };
 
 /* ULPI SMSC USB3320 */
 &usb0 {
 	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb0_default>;
 };
 
 &dwc3_0 {
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 07b99233b3d2..54e0edbbb9a3 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -830,6 +830,12 @@
 			power-domains = <&pd_sd1>;
 		};
 
+		pinctrl0: pinctrl at ff180000 {
+			compatible = "xlnx,pinctrl-zynqmp";
+			status = "disabled";
+			reg = <0x0 0xff180000 0x0 0x1000>;
+		};
+
 		smmu: smmu at fd800000 {
 			compatible = "arm,mmu-500";
 			reg = <0x0 0xfd800000 0x0 0x20000>;
diff --git a/include/dt-bindings/pinctrl/pinctrl-zynqmp.h b/include/dt-bindings/pinctrl/pinctrl-zynqmp.h
new file mode 100644
index 000000000000..e1b81fe5ef2f
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-zynqmp.h
@@ -0,0 +1,30 @@
+/*
+ * MIO pin configuration defines for Xilinx ZynqMP
+ *
+ * Copyright (C) 2017 Xilinx, Inc.
+ * Author: Chirag Parekh <chirag.parekh@xilinx.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H
+#define _DT_BINDINGS_PINCTRL_ZYNQMP_H
+
+/* Bit value for IO standards */
+#define IO_STANDARD_LVCMOS33      0
+#define IO_STANDARD_LVCMOS18      1
+
+/* Bit values for Slew Rates */
+#define SLEW_RATE_FAST            0
+#define SLEW_RATE_SLOW            1
+
+/* Bit values for Pin inputs */
+#define PIN_INPUT_TYPE_CMOS       0
+#define PIN_INPUT_TYPE_SCHMITT    1
+
+#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */
-- 
1.9.1

  parent reply	other threads:[~2017-11-06 12:12 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-11-06 12:12 [U-Boot] [PATCH 00/40] zynqmp: arm64: DT changes Michal Simek
2017-11-06 12:12 ` [U-Boot] [PATCH 01/40] arm64: zynqmp: Add references to cpu nodes Michal Simek
2017-11-06 12:12 ` [U-Boot] [PATCH 02/40] arm64: zynqmp: Update the OPPs for cpu freq Michal Simek
2017-11-06 12:12 ` [U-Boot] [PATCH 03/40] arm64: zynqmp: DT: Fix typo in idle-states node definition Michal Simek
2017-11-06 12:12 ` [U-Boot] [PATCH 04/40] arm64: zynqmp: Reduced min-residency time for idle state node Michal Simek
2017-11-06 12:12 ` [U-Boot] [PATCH 05/40] arm64: zynqmp: PM: Add IRQ Michal Simek
2017-11-06 12:12 ` [U-Boot] [PATCH 06/40] arm64: zynqmp: Fix broken architected timer interrupt trigger Michal Simek
2017-11-06 12:12 ` [U-Boot] [PATCH 07/40] arm64: zynqmp: Label whole PL part as fpga_full region Michal Simek
2017-11-06 12:12 ` [U-Boot] [PATCH 08/40] arm64: zynqmp: Add clock name for GPU Michal Simek
2017-11-06 12:12 ` [U-Boot] [PATCH 09/40] arm64: zynqmp: Update the GPU address size Michal Simek
2017-11-06 12:12 ` [U-Boot] [PATCH 10/40] arm64: zynqmp: Add missing gpio property to dtsi Michal Simek
2017-11-06 12:12 ` [U-Boot] [PATCH 11/40] arm64: dts: xilinx: fix PCI bus dtc warnings Michal Simek
2017-11-06 12:12 ` [U-Boot] [PATCH 12/40] arm64: zynqmp: Add SMMU support for SATA IP Michal Simek
2017-11-06 12:12 ` [U-Boot] [PATCH 13/40] arm64: zynqmp: rtc: Add calibration Michal Simek
2017-11-06 12:12 ` [U-Boot] [PATCH 14/40] arm64: zynqmp: disable smmu Michal Simek
2017-11-06 12:12 ` [U-Boot] [PATCH 15/40] arm64: zynqmp: PM: Specify power domains for DP related nodes Michal Simek
2017-11-06 12:12 ` [U-Boot] [PATCH 16/40] arm64: zynqmp: Use revision in dts file description Michal Simek
2017-11-06 12:12 ` [U-Boot] [PATCH 17/40] arm64: zynqmp: Add revB string to compatible string Michal Simek
2017-11-06 12:12 ` [U-Boot] [PATCH 18/40] arm64: zynqmp: Update device tree for gpio Michal Simek
2017-11-06 12:12 ` [U-Boot] [PATCH 19/40] arm64: zynqmp: zcu102: Modifying GTR lane-0 to PCIe Michal Simek
2017-11-06 12:12 ` [U-Boot] [PATCH 20/40] arm64: zynqmp: Add missing alias for gem0 for ep108 Michal Simek
2017-11-06 12:12 ` [U-Boot] [PATCH 21/40] arm64: zynqmp: Remove leading 0s from mtd table for spi flashes Michal Simek
2017-11-06 12:12 ` [U-Boot] [PATCH 22/40] arm64: zynqmp: Use SPDX license with dc4 Michal Simek
2017-11-06 12:12 ` [U-Boot] [PATCH 23/40] arm64: zynqmp: Remove local-mac-address from dtsi file Michal Simek
2017-11-06 12:12 ` Michal Simek [this message]
2017-11-06 12:12 ` [U-Boot] [PATCH 25/40] arm64: zynqmp: Add support for zcu102 1.0 rev Michal Simek
2017-11-06 12:12 ` [U-Boot] [PATCH 26/40] arm64: zynqmp: Add support for zynqmp nvmem firmware driver Michal Simek
2017-11-06 12:12 ` [U-Boot] [PATCH 27/40] arm64: zynqmp: Remove tx_termination_fix detection on silicon v1 Michal Simek
2017-11-06 12:13 ` [U-Boot] [PATCH 28/40] arm64: zynqmp: Add reset-controller support in serdes driver Michal Simek
2017-11-06 12:13 ` [U-Boot] [PATCH 29/40] arm64: zynqmp: Use reset controller framework for asserting/de-asserting reset Michal Simek
2017-11-06 12:13 ` [U-Boot] [PATCH 30/40] arm64: zynqmp: sdhci: set host quirk2 for no 1.8V support for 1.0 silicon Michal Simek
2017-11-06 12:13 ` [U-Boot] [PATCH 31/40] arm64: zynqmp: dt: Add AMS node Michal Simek
2017-11-06 12:13 ` [U-Boot] [PATCH 32/40] arm64: zynqmp: Move nodes which have no reg property out of bus Michal Simek
2017-11-06 12:13 ` [U-Boot] [PATCH 33/40] arm64: zynqmp: Add support reading SoC revision using nvmem driver in dwc3 Michal Simek
2017-11-06 12:13 ` [U-Boot] [PATCH 34/40] arm64: zynqmp: Enabled CCI support for USB Michal Simek
2017-11-06 12:13 ` [U-Boot] [PATCH 35/40] arm64: zynqmmp: Add USB OTG interrupts support in dt Michal Simek
2017-11-06 12:13 ` [U-Boot] [PATCH 36/40] arm64: zynqmp: Uncomment snps, quirk-frame-length-adjustment flag in dwc3 Michal Simek
2017-11-06 12:13 ` [U-Boot] [PATCH 37/40] arm64: zynqmp: Remove clock setting from dtsi Michal Simek
2017-11-06 12:13 ` [U-Boot] [PATCH 38/40] arm64: zynqmp: usb: Correct IOMMU node for making SMMU work with USB Michal Simek
2017-11-06 12:13 ` [U-Boot] [PATCH 39/40] arm64: zynqmp: Add note about si5328 interrupt Michal Simek
2017-11-06 12:13 ` [U-Boot] [PATCH 40/40] arm64: zynqmp: Enable watchdog by default Michal Simek

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