Re: [PATCH v2 2/3] target/ppc: Fix FPSCR.FI changing in float_overflow_excp()

[Richard Henderson <richard.henderson@linaro.org>]

On 5/10/22 13:46, Víctor Colombo wrote:
> This patch fixes another not-so-clear situation in Power ISA
> regarding the inexact bits in FPSCR. The ISA states that:
> 
> """
> When Overflow Exception is disabled (OE=0) and an
> Overflow Exception occurs, the following actions are
> taken:
> ...
> 2. Inexact Exception is set
> XX <- 1
> ...
> FI is set to 1
> ...
> """
> 
> However, when tested on a Power 9 hardware, some instructions that
> trigger an OX don't set the FI bit:
> 
> xvcvdpsp(0x4050533fcdb7b95ff8d561c40bf90996) = FI: CLEARED -> CLEARED
> xvnmsubmsp(0xf3c0c1fc8f3230, 0xbeaab9c5) = FI: CLEARED -> CLEARED
> (just a few examples. Other instructions are also affected)
> 
> The root cause for this seems to be that only instructions that list
> the bit FI in the "Special Registers Altered" should modify it.
> 
> QEMU is, today, not working like the hardware:
> 
> xvcvdpsp(0x4050533fcdb7b95ff8d561c40bf90996) = FI: CLEARED -> SET
> xvnmsubmsp(0xf3c0c1fc8f3230, 0xbeaab9c5) = FI: CLEARED -> SET
> 
> (all tests assume FI is cleared beforehand)
> 
> Fix this by making float_overflow_excp() return float_flag_inexact
> if it should update the inexact flags.
> 
> Signed-off-by: Víctor Colombo<victor.colombo@eldorado.org.br>
> 
> ---
> 
> v2:
> - remove the setting of FI from float_overflow_excp, making
>    do_float_check_status() the only responsible for it.
> - make float_overflow_excp() return float_flag_inexact if it should
>    update the inexact flags.
> ---
>   target/ppc/fpu_helper.c | 13 +++++++------
>   1 file changed, 7 insertions(+), 6 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~