From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65630C433F5 for ; Sat, 9 Apr 2022 03:50:14 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 286A883DA2; Sat, 9 Apr 2022 05:50:12 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=rock-chips.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id F2B1283A97; Sat, 9 Apr 2022 05:50:09 +0200 (CEST) Received: from mail-m17664.qiye.163.com (mail-m17664.qiye.163.com [59.111.176.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 9EBFD83DAA for ; Sat, 9 Apr 2022 05:50:04 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=kever.yang@rock-chips.com Received: from [192.168.0.115] (unknown [112.49.233.126]) by mail-m17664.qiye.163.com (Hmail) with ESMTPA id ED1F01401E5; Sat, 9 Apr 2022 11:49:51 +0800 (CST) Message-ID: <64a54656-9b34-076f-ef80-ff41610563e7@rock-chips.com> Date: Sat, 9 Apr 2022 11:49:51 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH v9 04/16] rockchip: rk3066: add rk3066 pinctrl driver Content-Language: en-US To: Johan Jonker Cc: sjg@chromium.org, philipp.tomsich@vrull.eu, lukma@denx.de, seanga2@gmail.com, u-boot@lists.denx.de References: <20220404141926.6085-1-jbx6244@gmail.com> <20220404141926.6085-5-jbx6244@gmail.com> From: Kever Yang In-Reply-To: <20220404141926.6085-5-jbx6244@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-HM-Spam-Status: e1kfGhgUHx5ZQUtXWQgPGg8OCBgUHx5ZQUlOS1dZCBgUCR5ZQVlLVUtZV1 kWDxoPAgseWUFZKDYvK1lXWShZQUhPN1dZLVlBSVdZDwkaFQgSH1lBWRkdTk9WS0sZQkJIQhkeSU xCVRMBExYaEhckFA4PWVdZFhoPEhUdFFlBWU9LSFVKSktISkxVS1kG X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6NCI6EBw4Tz5DAUwKSz4tIUwj EyMaCzRVSlVKTU9CT0xNSkJJSElLVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlKSklVT0JVSUhIVUpJTVlXWQgBWUFNSkxINwY+ X-HM-Tid: 0a800c71474ada2fkuwsed1f01401e5 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On 2022/4/4 22:19, Johan Jonker wrote: > From: PaweÅ‚ Jarosz > > Add driver supporting pin multiplexing on rk3066 platform. > > Signed-off-by: PaweÅ‚ Jarosz > Signed-off-by: Johan Jonker Reviewed-by: Kever Yang Thanks, - Kever > --- > > Changed V9: > change regmap source > > Changed V7: > restyle > changed function prefix. > restyle U_BOOT_DRIVER structure > use OF_REAL > use EOPNOTSUPP > --- > drivers/pinctrl/rockchip/Makefile | 1 + > drivers/pinctrl/rockchip/pinctrl-rk3066.c | 112 ++++++++++++++++++++++ > 2 files changed, 113 insertions(+) > create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3066.c > > diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile > index fcf19f877a..7d03f8101d 100644 > --- a/drivers/pinctrl/rockchip/Makefile > +++ b/drivers/pinctrl/rockchip/Makefile > @@ -5,6 +5,7 @@ > obj-y += pinctrl-rockchip-core.o > obj-$(CONFIG_ROCKCHIP_PX30) += pinctrl-px30.o > obj-$(CONFIG_ROCKCHIP_RK3036) += pinctrl-rk3036.o > +obj-$(CONFIG_ROCKCHIP_RK3066) += pinctrl-rk3066.o > obj-$(CONFIG_ROCKCHIP_RK3128) += pinctrl-rk3128.o > obj-$(CONFIG_ROCKCHIP_RK3188) += pinctrl-rk3188.o > obj-$(CONFIG_ROCKCHIP_RK322X) += pinctrl-rk322x.o > diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3066.c b/drivers/pinctrl/rockchip/pinctrl-rk3066.c > new file mode 100644 > index 0000000000..598b63223e > --- /dev/null > +++ b/drivers/pinctrl/rockchip/pinctrl-rk3066.c > @@ -0,0 +1,112 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * (C) Copyright 2021 Rockchip Electronics Co., Ltd > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "pinctrl-rockchip.h" > + > +static int rk3066_pinctrl_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) > +{ > + struct rockchip_pinctrl_priv *priv = bank->priv; > + int iomux_num = (pin / 8); > + struct regmap *regmap; > + int reg, ret, mask, mux_type; > + u8 bit; > + u32 data; > + > + regmap = priv->regmap_base; > + > + /* get basic quadrupel of mux registers and the correct reg inside */ > + mux_type = bank->iomux[iomux_num].type; > + reg = bank->iomux[iomux_num].offset; > + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); > + > + data = (mask << (bit + 16)); > + data |= (mux & mask) << bit; > + ret = regmap_write(regmap, reg, data); > + > + return ret; > +} > + > +#define RK3066_PULL_OFFSET 0x118 > +#define RK3066_PULL_PINS_PER_REG 16 > +#define RK3066_PULL_BANK_STRIDE 8 > + > +static void rk3066_pinctrl_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, > + int pin_num, struct regmap **regmap, > + int *reg, u8 *bit) > +{ > + struct rockchip_pinctrl_priv *priv = bank->priv; > + > + *regmap = priv->regmap_base; > + *reg = RK3066_PULL_OFFSET; > + *reg += bank->bank_num * RK3066_PULL_BANK_STRIDE; > + *reg += (pin_num / RK3066_PULL_PINS_PER_REG) * 4; > + > + *bit = pin_num % RK3066_PULL_PINS_PER_REG; > +}; > + > +static int rk3066_pinctrl_set_pull(struct rockchip_pin_bank *bank, > + int pin_num, int pull) > +{ > + struct regmap *regmap; > + int reg, ret; > + u8 bit; > + u32 data; > + > + if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT && > + pull != PIN_CONFIG_BIAS_DISABLE) > + return -EOPNOTSUPP; > + > + rk3066_pinctrl_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); > + data = BIT(bit + 16); > + if (pull == PIN_CONFIG_BIAS_DISABLE) > + data |= BIT(bit); > + ret = regmap_write(regmap, reg, data); > + > + return ret; > +} > + > +static struct rockchip_pin_bank rk3066_pin_banks[] = { > + PIN_BANK(0, 32, "gpio0"), > + PIN_BANK(1, 32, "gpio1"), > + PIN_BANK(2, 32, "gpio2"), > + PIN_BANK(3, 32, "gpio3"), > + PIN_BANK(4, 32, "gpio4"), > + PIN_BANK(6, 16, "gpio6"), > +}; > + > +static struct rockchip_pin_ctrl rk3066_pin_ctrl = { > + .pin_banks = rk3066_pin_banks, > + .nr_banks = ARRAY_SIZE(rk3066_pin_banks), > + .grf_mux_offset = 0xa8, > + .set_mux = rk3066_pinctrl_set_mux, > + .set_pull = rk3066_pinctrl_set_pull, > +}; > + > +static const struct udevice_id rk3066_pinctrl_ids[] = { > + { > + .compatible = "rockchip,rk3066a-pinctrl", > + .data = (ulong)&rk3066_pin_ctrl > + }, > + {} > +}; > + > +U_BOOT_DRIVER(rockchip_rk3066a_pinctrl) = { > + .name = "rockchip_rk3066a_pinctrl", > + .id = UCLASS_PINCTRL, > + .ops = &rockchip_pinctrl_ops, > + .probe = rockchip_pinctrl_probe, > +#if CONFIG_IS_ENABLED(OF_REAL) > + .bind = dm_scan_fdt_dev, > +#endif > + .of_match = rk3066_pinctrl_ids, > + .priv_auto = sizeof(struct rockchip_pinctrl_priv), > +};