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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: Bin Meng <bmeng.cn@gmail.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: Bin Meng <bin.meng@windriver.com>
Subject: Re: [PATCH v3 3/9] hw/ssi: Add SiFive SPI controller support
Date: Tue, 26 Jan 2021 08:34:05 +0100	[thread overview]
Message-ID: <64f493fb-25cb-d3c9-11fe-ca61fca75f50@amsat.org> (raw)
In-Reply-To: <20210126060007.12904-4-bmeng.cn@gmail.com>

On 1/26/21 7:00 AM, Bin Meng wrote:
> From: Bin Meng <bin.meng@windriver.com>
> 
> This adds the SiFive SPI controller model for the FU540 SoC.
> The direct memory-mapped SPI flash mode is unsupported.
> 
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> 
> ---
> 
> Changes in v3:
> - Simplify flush txfifo logic
> 
> Changes in v2:
> - Log guest error when trying to write reserved registers
> - Log guest error when trying to access out-of-bounds registers
> - log guest error when writing to reserved bits for chip select
>   registers and watermark registers
> - Log unimplemented warning when trying to write direct-map flash
>   interface registers
> - Add test tx fifo full logic in sifive_spi_read(), hence remove
>   setting the tx fifo full flag in sifive_spi_write().
> - Populate register with their default value
> 
>  include/hw/ssi/sifive_spi.h |  47 +++++
>  hw/ssi/sifive_spi.c         | 358 ++++++++++++++++++++++++++++++++++++
>  hw/ssi/Kconfig              |   4 +
>  hw/ssi/meson.build          |   1 +
>  4 files changed, 410 insertions(+)
>  create mode 100644 include/hw/ssi/sifive_spi.h
>  create mode 100644 hw/ssi/sifive_spi.c

Missing MAINTAINERS entry (if there are no other comments on
this series, maybe the maintainer can directly add one).


  reply	other threads:[~2021-01-26  7:35 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-26  5:59 [PATCH v3 0/9] hw/riscv: sifive_u: Add missing SPI support Bin Meng
2021-01-26  5:59 ` [PATCH v3 1/9] hw/block: m25p80: Add ISSI SPI flash support Bin Meng
2021-01-28 20:56   ` Alistair Francis
2021-01-28 20:56     ` Alistair Francis
2021-01-26  6:00 ` [PATCH v3 2/9] hw/block: m25p80: Add various ISSI flash information Bin Meng
2021-01-26  6:00 ` [PATCH v3 3/9] hw/ssi: Add SiFive SPI controller support Bin Meng
2021-01-26  7:34   ` Philippe Mathieu-Daudé [this message]
2021-02-09  1:44     ` Alistair Francis
2021-02-09  1:44       ` Alistair Francis
2021-02-09  1:46       ` Bin Meng
2021-02-09  1:46         ` Bin Meng
2021-02-09  1:53       ` Palmer Dabbelt
2021-02-09  1:53         ` Palmer Dabbelt
2021-02-09  1:38   ` Alistair Francis
2021-02-09  1:38     ` Alistair Francis
2021-01-26  6:00 ` [PATCH v3 4/9] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash Bin Meng
2021-01-26  6:00 ` [PATCH v3 5/9] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card Bin Meng
2021-01-26  6:00 ` [PATCH v3 6/9] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value Bin Meng
2021-01-26  6:00 ` [PATCH v3 7/9] docs/system: Sort targets in alphabetical order Bin Meng
2021-01-26  6:00 ` [PATCH v3 8/9] docs/system: Add RISC-V documentation Bin Meng
2021-01-26  6:00 ` [PATCH v3 9/9] docs/system: riscv: Add documentation for sifive_u machine Bin Meng
2021-01-27  5:51   ` Palmer Dabbelt
2021-01-27  5:51     ` Palmer Dabbelt

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