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[88.26.246.243]) by smtp.gmail.com with ESMTPSA id g18sm4017848wmh.48.2020.02.11.07.29.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 11 Feb 2020 07:29:55 -0800 (PST) Subject: Re: [RFC PATCH 10/66] Hexagon register fields To: Taylor Simpson , qemu-devel@nongnu.org References: <1581381644-13678-1-git-send-email-tsimpson@quicinc.com> <1581381644-13678-11-git-send-email-tsimpson@quicinc.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <652c203f-b091-b63f-4b9c-85d46d3550df@redhat.com> Date: Tue, 11 Feb 2020 16:29:53 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <1581381644-13678-11-git-send-email-tsimpson@quicinc.com> Content-Language: en-US X-MC-Unique: SA_IMBCtNc2MaHpCcwrsFw-1 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/11/20 1:39 AM, Taylor Simpson wrote: > Declare bitfields within registers such as user status register (USR) > > Signed-off-by: Taylor Simpson > --- > target/hexagon/reg_fields.c | 28 +++++++++++ > target/hexagon/reg_fields.h | 40 +++++++++++++++ > target/hexagon/reg_fields_def.h | 109 ++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 177 insertions(+) > create mode 100644 target/hexagon/reg_fields.c > create mode 100644 target/hexagon/reg_fields.h > create mode 100644 target/hexagon/reg_fields_def.h > > diff --git a/target/hexagon/reg_fields.c b/target/hexagon/reg_fields.c > new file mode 100644 > index 0000000..983655e > --- /dev/null > +++ b/target/hexagon/reg_fields.c > @@ -0,0 +1,28 @@ > +/* > + * Copyright (c) 2019 Qualcomm Innovation Center, Inc. All Rights Reserved. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, see . > + */ > + > +#include Replace by: #include "qemu/osdep.h" > +#include "reg_fields.h" > + > +reg_field_t reg_field_info[] = { > +#define DEF_REG_FIELD(TAG, NAME, START, WIDTH, DESCRIPTION) \ > + {NAME, START, WIDTH, DESCRIPTION}, > +#include "reg_fields_def.h" > + {NULL, 0, 0} > +#undef DEF_REG_FIELD > +}; > + > diff --git a/target/hexagon/reg_fields.h b/target/hexagon/reg_fields.h > new file mode 100644 > index 0000000..79857c5 > --- /dev/null > +++ b/target/hexagon/reg_fields.h > @@ -0,0 +1,40 @@ > +/* > + * Copyright (c) 2019 Qualcomm Innovation Center, Inc. All Rights Reserved. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, see . > + */ > + > +#ifndef REGS_H > +#define REGS_H Maybe HEXAGON_REG_FIELDS? > + > +#define NUM_GEN_REGS 32 > + > +typedef struct { > + const char *name; > + int offset; > + int width; > + const char *description; > +} reg_field_t; > + > +extern reg_field_t reg_field_info[]; > + > +enum reg_fields_enum { > +#define DEF_REG_FIELD(TAG, NAME, START, WIDTH, DESCRIPTION) \ > + TAG, > +#include "reg_fields_def.h" > + NUM_REG_FIELDS > +#undef DEF_REG_FIELD > +}; > + > +#endif > diff --git a/target/hexagon/reg_fields_def.h b/target/hexagon/reg_fields_def.h > new file mode 100644 > index 0000000..095a776 > --- /dev/null > +++ b/target/hexagon/reg_fields_def.h > @@ -0,0 +1,109 @@ > +/* > + * Copyright (c) 2019 Qualcomm Innovation Center, Inc. All Rights Reserved. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, see . > + */ > + > +/* > + * For registers that have individual fields, explain them here > + * DEF_REG_FIELD(tag, > + * name, > + * bit start offset, > + * width, > + * description > + */ > + > +/* USR fields */ > +DEF_REG_FIELD(USR_OVF, > + "ovf", 0, 1, > + "Sticky Saturation Overflow - " > + "Set when saturation occurs while executing instruction that specifies " > + "optional saturation, remains set until explicitly cleared by a USR=Rs " > + "instruction.") > +DEF_REG_FIELD(USR_FPINVF, > + "fpinvf", 1, 1, > + "Floating-point IEEE Invalid Sticky Flag.") > +DEF_REG_FIELD(USR_FPDBZF, > + "fpdbzf", 2, 1, > + "Floating-point IEEE Divide-By-Zero Sticky Flag.") > +DEF_REG_FIELD(USR_FPOVFF, > + "fpovff", 3, 1, > + "Floating-point IEEE Overflow Sticky Flag.") > +DEF_REG_FIELD(USR_FPUNFF, > + "fpunff", 4, 1, > + "Floating-point IEEE Underflow Sticky Flag.") > +DEF_REG_FIELD(USR_FPINPF, > + "fpinpf", 5, 1, > + "Floating-point IEEE Inexact Sticky Flag.") > + > +DEF_REG_FIELD(USR_LPCFG, > + "lpcfg", 8, 2, > + "Hardware Loop Configuration: " > + "Number of loop iterations (0-3) remaining before pipeline predicate " > + "should be set.") > +DEF_REG_FIELD(USR_PKTCNT_U, > + "pktcnt_u", 10, 1, > + "Enable packet counting in User mode.") > +DEF_REG_FIELD(USR_PKTCNT_G, > + "pktcnt_g", 11, 1, > + "Enable packet counting in Guest mode.") > +DEF_REG_FIELD(USR_PKTCNT_M, > + "pktcnt_m", 12, 1, > + "Enable packet counting in Monitor mode.") > +DEF_REG_FIELD(USR_HFD, > + "hfd", 13, 2, > + "Two bits that let the user control the amount of L1 hardware data cache " > + "prefetching (up to 4 cache lines): " > + "00: No prefetching, " > + "01: Prefetch Loads with post-updating address mode when execution is " > + "within a hardware loop, " > + "10: Prefetch any hardware-detected striding Load when execution is within " > + "a hardware loop, " > + "11: Prefetch any hardware-detected striding Load.") > +DEF_REG_FIELD(USR_HFI, > + "hfi", 15, 2, > + "Two bits that let the user control the amount of L1 instruction cache " > + "prefetching. " > + "00: No prefetching, " > + "01: Allow prefetching of at most 1 additional cache line, " > + "10: Allow prefetching of at most 2 additional cache lines.") > + > +DEF_REG_FIELD(USR_FPRND, > + "fprnd", 22, 2, > + "Rounding Mode for Floating-Point Instructions: " > + "00: Round to nearest, ties to even (default), " > + "01: Toward zero, " > + "10: Downward (toward negative infinity), " > + "11: Upward (toward positive infinity).") > + > +DEF_REG_FIELD(USR_FPINVE, > + "fpinve", 25, 1, > + "Enable trap on IEEE Invalid.") > +DEF_REG_FIELD(USR_FPDBZE, > + "fpdbze", 26, 1, "Enable trap on IEEE Divide-By-Zero.") > +DEF_REG_FIELD(USR_FPOVFE, > + "fpovfe", 27, 1, > + "Enable trap on IEEE Overflow.") > +DEF_REG_FIELD(USR_FPUNFE, > + "fpunfe", 28, 1, > + "Enable trap on IEEE Underflow.") > +DEF_REG_FIELD(USR_FPINPE, > + "fpinpe", 29, 1, > + "Enable trap on IEEE Inexact.") > +DEF_REG_FIELD(USR_PFA, > + "pfa", 31, 1, > + "L2 Prefetch Active: Set when non-blocking l2fetch instruction is " > + "prefetching requested data, remains set until l2fetch prefetch operation " > + "is completed (or not active).") /* read-only */ > + >