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Tue, 17 Dec 2019 02:57:36 -0600 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Tue, 17 Dec 2019 02:57:35 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Tue, 17 Dec 2019 02:57:35 -0600 Received: from [172.24.145.199] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBH8vXXi076193; Tue, 17 Dec 2019 02:57:34 -0600 Subject: Re: flash_lock issue for n25q 128mb spi nor part To: , , References: <42e10e49-5ec0-e4a3-bd11-e9fa0cc0d9b1@microchip.com> <6ade1621-2d3f-6ddd-64a3-6405b07802c6@huawei.com> <36c733b3-acac-4779-480d-7f0ae1db710e@huawei.com> <00cf6eab-9798-b0e9-e4a2-5b2f8374b698@huawei.com> <9d41bfca-f4e3-beb2-ff7f-78be49e8d80e@microchip.com> <32a6af31-341b-67cf-a98d-d77a495c7ecc@huawei.com> From: Vignesh Raghavendra Message-ID: <6667f429-4732-d098-843a-7a030010f192@ti.com> Date: Tue, 17 Dec 2019 14:27:33 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.3.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191217_005749_060305_E891F6AF X-CRM114-Status: GOOD ( 14.98 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: broonie@kernel.org, fengsheng5@huawei.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org Hi Tudor, On 12/16/2019 11:39 PM, Tudor.Ambarus@microchip.com wrote: [...] >> >> But, as you may see, it seems that my change to spi_nor_write() is still >> required to stop the first unlock failure message, but it needs to be >> relocated to after write_err label, as we now jump there for >> spi_nor_wait_till_ready() failure. I guess the equivalent relocation is >> also required for spi_nor_erase(). >> >> Or maybe spi_nor_wait_till_ready() should clear this flag always. > > I reproduced this on a n25q256a, with both erase and write. Did a lock, > an erase or write, and then the unlock raises an error on the read back test: > it receives 0x02 to write (the prev operation let the SR.WE set to 1), > and after write, it reads back 0x00 (which is correct, WE is de-asserted). > > What is pretty strange is that Micron says about erase or program operations > that: "When the operation is in progress, the write in progress bit is set > to 1. The write enable latch bit is cleared to 0, whether the operation is > successful or not". > > So what I guess it happens, is that when an erase/write command tries to > modify a software protected area, the flash completely ignores the command, > so no Write In Progress, and no clearing of the WE. > >From PROGRAM Operations section of mt25q datasheet: " When a command is applied to a protected sector, the command is not executed, the write enable latch bit remains set to 1, and flag status register bits 1 and 4 are set." So, Data sheet is quite clear about this and SW would need to clear WEL (if required) after write failure. Regards Vignesh ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/