From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sowjanya Komatineni Subject: Re: [RFC PATCH v3 16/18] gpu: host1x: mipi: Split tegra_mipi_calibrate and tegra_mipi_wait Date: Thu, 16 Jul 2020 16:09:20 -0700 Message-ID: <66812127-38cf-2af3-51c0-50edbe446e73@nvidia.com> References: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> <1594786855-26506-17-git-send-email-skomatineni@nvidia.com> <20d63eca-4b2b-584e-a391-a4fb64a16b40@nvidia.com> <4690e682-8495-2327-87c7-c2f06a7a479d@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <4690e682-8495-2327-87c7-c2f06a7a479d-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Content-Language: en-US Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Dmitry Osipenko , thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org, frankc-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org, hverkuil-qWit8jRvyhVmR6Xm/wNWPw@public.gmane.org, sakari.ailus-X3B1VOXEql0@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, helen.koike-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org Cc: sboyd-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org, linux-media-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-tegra@vger.kernel.org On 7/16/20 4:06 PM, Sowjanya Komatineni wrote: > > On 7/16/20 4:01 PM, Dmitry Osipenko wrote: >> 17.07.2020 01:49, Sowjanya Komatineni =D0=BF=D0=B8=D1=88=D0=B5=D1=82: >>>> What keeps MIPI clock enabled after completion of the >>>> tegra_mipi_calibrate() invocation? >>> MIPI clock is disabled at end of tegra_mipi_calibrate and is re-enabled >>> during tegra_mipi_wait. >>> >>> I think I should fix this to keep the clock enabled till calibration >>> results are latched. >>> >>> All consumers of tegra_mipi_calibrate() will call tegra_mipi_wait(). >>> >>> So will remove clk_disable mipi clk at end of tegra_mipi_calibrate()=20 >>> and >>> clk_enable mipi_clk at beginning of tegra_mipi_wait() >> Isn't it possible to perform the calibration after enabling CSI and >> before of starting the sensor streaming? > Currently this is what I am doing. Triggering calibration start during=20 > CSI receiver being ready and then sensor streaming will happen where=20 > internal MIPI CAL detects for LP -> HS transition and applies results=20 > to pads. So checking for calibration results after sensor stream is=20 > enabled 1. Calling tegra_mipi_calibrate() during CSI streaming where CSI pads=20 are enabled and receiver is kept ready 2. Start Sensor stream 3. Calling tegra_mipi_wait() to check for MIPI Cal status. So as mipi cal clk need to be kept enabled till 3rd step, we can enable=20 clock during tegra_mipi_calibrate() and leave it enabled and disable it=20 in tegra_mipi_wait after status check. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.6 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7415C433E2 for ; Thu, 16 Jul 2020 23:08:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8B54A2100A for ; Thu, 16 Jul 2020 23:08:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="kw25KOP8" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727096AbgGPXIi (ORCPT ); Thu, 16 Jul 2020 19:08:38 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:14623 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726189AbgGPXIg (ORCPT ); Thu, 16 Jul 2020 19:08:36 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 16 Jul 2020 16:04:33 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 16 Jul 2020 16:06:29 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 16 Jul 2020 16:06:29 -0700 Received: from [10.2.163.115] (172.20.13.39) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 16 Jul 2020 23:06:27 +0000 Subject: Re: [RFC PATCH v3 16/18] gpu: host1x: mipi: Split tegra_mipi_calibrate and tegra_mipi_wait From: Sowjanya Komatineni To: Dmitry Osipenko , , , , , , , CC: , , , , , , References: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> <1594786855-26506-17-git-send-email-skomatineni@nvidia.com> <20d63eca-4b2b-584e-a391-a4fb64a16b40@nvidia.com> <4690e682-8495-2327-87c7-c2f06a7a479d@nvidia.com> Message-ID: <66812127-38cf-2af3-51c0-50edbe446e73@nvidia.com> Date: Thu, 16 Jul 2020 16:09:20 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <4690e682-8495-2327-87c7-c2f06a7a479d@nvidia.com> X-Originating-IP: [172.20.13.39] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: quoted-printable Content-Language: en-US DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1594940673; bh=Z4JZpBtLsxYQwYWYUS7JvDfbpdedkjBLLYi0PiWmXmk=; h=X-PGP-Universal:Subject:From:To:CC:References:Message-ID:Date: User-Agent:MIME-Version:In-Reply-To:X-Originating-IP: X-ClientProxiedBy:Content-Type:Content-Transfer-Encoding: Content-Language; b=kw25KOP8ZMu/3RgD066xjNLJQmMe1Yn3cDZuI6pFYiSjZP6mRBPPgRhCQQbpAmN3Q PRMHAmEOlmegOMdVPB2B7B2WS91FjBaAOAsFq0u7gX+vJ0QbKlLEksLJ2WECLXNpRY mPTZMMtIg+piKtlW8nq7wqbWd6v7/kOah8aRXyea0X8tDC8dAHKIFctIbtBiWqQAbz AizGcKDNNwHaPBVh7UB41U/Zq/RysGV0dJgV7Q9yT2y35aww8u7MyYqI4JvGsaHBi7 l06K+Pe6Uhb71lcOxypn3fA+QPLOODOerBWJaN5JB5dCvY42NSgzonbPxwIPKSRSVk G39XvkISUav8A== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 7/16/20 4:06 PM, Sowjanya Komatineni wrote: > > On 7/16/20 4:01 PM, Dmitry Osipenko wrote: >> 17.07.2020 01:49, Sowjanya Komatineni =D0=BF=D0=B8=D1=88=D0=B5=D1=82: >>>> What keeps MIPI clock enabled after completion of the >>>> tegra_mipi_calibrate() invocation? >>> MIPI clock is disabled at end of tegra_mipi_calibrate and is re-enabled >>> during tegra_mipi_wait. >>> >>> I think I should fix this to keep the clock enabled till calibration >>> results are latched. >>> >>> All consumers of tegra_mipi_calibrate() will call tegra_mipi_wait(). >>> >>> So will remove clk_disable mipi clk at end of tegra_mipi_calibrate()=20 >>> and >>> clk_enable mipi_clk at beginning of tegra_mipi_wait() >> Isn't it possible to perform the calibration after enabling CSI and >> before of starting the sensor streaming? > Currently this is what I am doing. Triggering calibration start during=20 > CSI receiver being ready and then sensor streaming will happen where=20 > internal MIPI CAL detects for LP -> HS transition and applies results=20 > to pads. So checking for calibration results after sensor stream is=20 > enabled 1. Calling tegra_mipi_calibrate() during CSI streaming where CSI pads=20 are enabled and receiver is kept ready 2. Start Sensor stream 3. Calling tegra_mipi_wait() to check for MIPI Cal status. So as mipi cal clk need to be kept enabled till 3rd step, we can enable=20 clock during tegra_mipi_calibrate() and leave it enabled and disable it=20 in tegra_mipi_wait after status check.