[PATCH v3 0/4] rockchip: Improve support for Bob chromebook and add support for Kevin

[PATCH v3 0/4] rockchip: Improve support for Bob chromebook and add support for Kevin

[Alper Nebi Yasak]

I have recently started testing booting U-Boot from SPI on my gru-kevin
(as opposed to chainloading it from vendor coreboot + depthcharge) and
brought it to a better working state based on an initial support patch
from Marty [1][2] and some follow-up work by Simon [3].

I tried to keep them as the git author when I took things from their
work, but squashing other changes into those and rewriting commit
messages makes things a bit weird in my opinion, especially for keeping
their signoff. Do tell me if there is a better way to that.

As the Kevin and Bob boards are very similar, I assumed the config and
devicetree changes will be appropriate for Bob as well, and applied them
to it first. I do not have a Bob, so could not test on one myself, but
Simon did test an earlier version of this and it appears to work [4].

Other useful things for these boards:
- Patch to fix a hang when usb controllers exit [5] (or [6])
- Series to support HS400ES mode as HS400 training fails [7]
  (but faster speeds are kept disabled in this series since v3)
- Hack to skip eMMC reinitialization so it keeps working [8]

[1] https://patchwork.ozlabs.org/patch/1053386/
[2] https://patchwork.ozlabs.org/comment/2488899/
[3] https://github.com/sjg20/u-boot/commits/kevin
[4] https://patchwork.ozlabs.org/comment/2799106/
[5] https://patchwork.ozlabs.org/project/uboot/patch/20210406151059.1187379-1-icenowy@aosc.io/
[6] https://patchwork.ozlabs.org/project/uboot/patch/20211224130549.20276-1-alpernebiyasak@gmail.com/
[7] https://patchwork.ozlabs.org/project/uboot/list/?series=269768
[8] https://patchwork.ozlabs.org/comment/2779784/

Changes in v3:
- Unset configs MMC_IO_VOLTAGE, MMC_UHS_SUPPORT, MMC_HS400_SUPPORT,
  MMC_HS400_ES_SUPPORT, MMC_SDHCI_SDMA.
- Add tag: "Reviewed-by: Kever Yang <kever.yang@rock-chips.com>"

v2: https://patchwork.ozlabs.org/project/uboot/list/?series=276629

Changes in v2:
- Drop unnecessary ifdef.
- Clarify commit message regarding 'values set in coreboot'.
- Rebase on u-boot/next, fixing conflict in board_debug_uart_init()

v1: https://patchwork.ozlabs.org/project/uboot/list/?series=273848

Alper Nebi Yasak (2):
  rockchip: gru: Set up SoC IO domain registers
  rockchip: bob: Enable more configs

Marty E. Plummer (1):
  rockchip: rk3399: Add support for chromebook_kevin

Simon Glass (1):
  rockchip: gru: Add more devicetree settings

 arch/arm/dts/Makefile                         |   1 +
 arch/arm/dts/rk3399-gru-kevin-u-boot.dtsi     |  11 ++
 arch/arm/dts/rk3399-gru-u-boot.dtsi           |  55 +++++++++
 arch/arm/mach-rockchip/rk3399/Kconfig         |  11 ++
 arch/arm/mach-rockchip/rk3399/rk3399.c        |   3 +-
 arch/arm/mach-rockchip/spl.c                  |   3 +-
 board/google/gru/Kconfig                      |  16 +++
 board/google/gru/MAINTAINERS                  |   8 ++
 board/google/gru/gru.c                        |  54 ++++++++-
 configs/chromebook_bob_defconfig              |  22 +++-
 configs/chromebook_kevin_defconfig            | 111 ++++++++++++++++++
 doc/board/rockchip/rockchip.rst               |   1 +
 include/configs/gru.h                         |   3 +
 include/dt-bindings/input/linux-event-codes.h |   3 +-
 14 files changed, 297 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/dts/rk3399-gru-kevin-u-boot.dtsi
 create mode 100644 configs/chromebook_kevin_defconfig

-- 
2.34.1

[PATCH v3 1/4] rockchip: gru: Set up SoC IO domain registers

[Alper Nebi Yasak]

The RK3399 SoC needs to know the voltage value provided by some
regulators, which is done by setting relevant register bits. Configure
these the way other RK3399 boards do, but with the same values as are
set in the equivalent code in coreboot.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
There is a driver for this on Rockchip's repo, I managed to forward-port
it and get it working. If that's more desirable than doing it per-board
like this I can send that upstream (but I'd prefer to do it after this).

Changes in v3:
- Add tag: "Reviewed-by: Kever Yang <kever.yang@rock-chips.com>"

Changes in v2:
- Drop unnecessary ifdef.
- Clarify commit message regarding 'values set in coreboot'.

 board/google/gru/gru.c | 52 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/board/google/gru/gru.c b/board/google/gru/gru.c
index 23080c1798b7..cbf62a9427c9 100644
--- a/board/google/gru/gru.c
+++ b/board/google/gru/gru.c
@@ -6,6 +6,17 @@
 #include <common.h>
 #include <dm.h>
 #include <init.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rk3399.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/misc.h>
+
+#define GRF_IO_VSEL_BT656_SHIFT 0
+#define GRF_IO_VSEL_AUDIO_SHIFT 1
+#define PMUGRF_CON0_VSEL_SHIFT 8
+#define PMUGRF_CON0_VOL_SHIFT 9
 
 #ifdef CONFIG_SPL_BUILD
 /* provided to defeat compiler optimisation in board_init_f() */
@@ -54,3 +65,44 @@ int board_early_init_r(void)
 	return 0;
 }
 #endif
+
+static void setup_iodomain(void)
+{
+	struct rk3399_grf_regs *grf =
+	   syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	struct rk3399_pmugrf_regs *pmugrf =
+	   syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
+
+	/* BT656 and audio is in 1.8v domain */
+	rk_setreg(&grf->io_vsel, (1 << GRF_IO_VSEL_BT656_SHIFT |
+				  1 << GRF_IO_VSEL_AUDIO_SHIFT));
+
+	/*
+	 * Set GPIO1 1.8v/3.0v source select to PMU1830_VOL
+	 * and explicitly configure that PMU1830_VOL to be 1.8V
+	 */
+	rk_setreg(&pmugrf->soc_con0, (1 << PMUGRF_CON0_VSEL_SHIFT |
+				      1 << PMUGRF_CON0_VOL_SHIFT));
+}
+
+int misc_init_r(void)
+{
+	const u32 cpuid_offset = 0x7;
+	const u32 cpuid_length = 0x10;
+	u8 cpuid[cpuid_length];
+	int ret;
+
+	setup_iodomain();
+
+	ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
+	if (ret)
+		return ret;
+
+	ret = rockchip_cpuid_set(cpuid, cpuid_length);
+	if (ret)
+		return ret;
+
+	ret = rockchip_setup_macaddr();
+
+	return ret;
+}
-- 
2.34.1

[PATCH v3 2/4] rockchip: gru: Add more devicetree settings

[Alper Nebi Yasak]

From: Simon Glass <sjg@chromium.org>

This adds some devicetree settings for the Gru-based boards, based on
what works on a Kevin board.

Gru-based boards usually have an 8MiB SPI flash chip and boot from it.
Make the u-boot.rom file intended to be flashed on it match its size.
Add properties for booting from SPI, and only try to boot from SPI as
MMC and SD card don't seem to work in SPL yet.

The Chromium OS EC needs a delay between transactions so it can get
itself ready. Also it currently uses a non-standard way of specifying
the interrupt. Add these so that the EC works reliably.

The Rockchip Embedded DisplayPort driver is looking for a rockchip,panel
property to find the panel it should work on. Add the property for the
Gru-based boards.

The U-Boot GPIO controlled regulator driver only considers the
"enable-gpios" devicetree property, not the singular "enable-gpio" one.
Some devicetree source files have the singular form as they were added
to Linux kernel when it used that form, and imported to U-Boot as is.
Fix one instance of this in the Gru boards' devicetree to the form that
works in U-Boot.

The PWM controlled regulator driver complains that there is no init
voltage set for a regulator it drives, though it's not clear which one.
Set them all to the voltage levels coreboot sets them: 900 mV.

The RK3399 SoC needs to know the voltage level that some supplies
provides, including one fixed 1.8V audio-related regulator. Although
this synchronization is currently statically done in the board init
functions, a not-so-hypothetical driver that does this dynamically would
query the regulator only to get -ENODATA and be confused. Make sure
U-Boot knows this supply is at 1.8V by setting its limits to that.

Most of this is a reapplication of commit 08c85b57a5ec ("rockchip: gru:
Add extra device-tree settings") whose changes were removed during a
sync with Linux at commit 167efc2c7a46 ("arm64: dts: rk3399: Sync
v5.7-rc1 from Linux"). Apply things to rk3399-gru-u-boot.dtsi instead so
they don't get lost again.

Signed-off-by: Simon Glass <sjg@chromium.org>
[Alper: move to -u-boot.dtsi, rewrite commit message, add more nodes]
Co-developed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
Kept sign-off and author as Simon based on the aforementioned commit.

Changes in v3:
- Add tag: "Reviewed-by: Kever Yang <kever.yang@rock-chips.com>"

 arch/arm/dts/rk3399-gru-u-boot.dtsi | 55 +++++++++++++++++++++++++++++
 1 file changed, 55 insertions(+)

diff --git a/arch/arm/dts/rk3399-gru-u-boot.dtsi b/arch/arm/dts/rk3399-gru-u-boot.dtsi
index 390ac2bb5a9a..33734e99be50 100644
--- a/arch/arm/dts/rk3399-gru-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-gru-u-boot.dtsi
@@ -5,6 +5,61 @@
 
 #include "rk3399-u-boot.dtsi"
 
+/ {
+	chosen {
+		u-boot,spl-boot-order = &spi_flash;
+	};
+
+	config {
+		u-boot,spl-payload-offset = <0x40000>;
+	};
+};
+
+&binman {
+	rom {
+		size = <0x800000>;
+	};
+};
+
+&cros_ec {
+	ec-interrupt = <&gpio0 RK_PA1 GPIO_ACTIVE_LOW>;
+};
+
+&edp {
+	rockchip,panel = <&edp_panel>;
+};
+
+&pp1800_audio {
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+};
+
+&ppvar_bigcpu_pwm {
+	regulator-init-microvolt = <900000>;
+};
+
+&ppvar_centerlogic_pwm {
+	regulator-init-microvolt = <900000>;
+};
+
+&ppvar_gpu_pwm {
+	regulator-init-microvolt = <900000>;
+};
+
+&ppvar_litcpu_pwm {
+	regulator-init-microvolt = <900000>;
+};
+
+&ppvar_sd_card_io {
+	enable-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+};
+
+&spi5 {
+	spi-activate-delay = <100>;
+	spi-max-frequency = <3000000>;
+	spi-deactivate-delay = <200>;
+};
+
 &spi_flash {
 	u-boot,dm-pre-reloc;
 };
-- 
2.34.1

[PATCH v3 3/4] rockchip: bob: Enable more configs

[Alper Nebi Yasak]

This patch enables some configs that should be working on the Bob board,
based on what is observed to work on the Kevin board.

The Bob board uses an Embedded DisplayPort panel compatible with the
simple panel and Rockchip eDP drivers. Its backlight is controlled by
the Chromium OS Embedded Controller Pulse Width Modulator. Enable these
for the board.

Also set VIDEO_ROCKCHIP_MAX_{XRES,YRES} to 1280x800, the resolution of
its panel. This had to be done for the Kevin board, but it's untested if
this is actually necessary for Bob.

The Rockchip video driver needs to assert/deassert some resets, so also
enable the reset controller. RESET_ROCKCHIP defaults to y for this board
when DM_RESET=y, so it's enough to set that.

The Bob board has two USB 3.0 Type-C ports and one USB 2.0 Type-A port
on its right side. Enable the configs relevant to USB devices so these
can be used. This is despite a known issue with RK3399 boards where USB
de-init causes a hang, as there is a known workaround.

Some other rk3399-based devices enable support for the SoC's random
number generator in commit a475bef5340c ("configs: rk3399: enable rng on
firefly/rock960/rockpro64"), as it can provide a KASLR seed when booting
using UEFI. Enable it for Bob as well.

The default misc_init_r() for Rockchip boards sets cpuid and ethernet
MAC address based on e-fuse block. A previous patch extends this on Gru
boards to set registers related to SoC IO domains as is necessary on
these boards. Enable this function and configs for it on Bob.

The microSD card slot on this board (and others based on Gru) is
connected to a GPIO controlled regulator (ppvar-sd-card-io), which must
be operable by U-Boot. Enable the relevant config option to allow this.

Bob boards also use the Winbond W25Q64DW SPI flash chip, enable support
for Winbond SPI flash chips in the board config so U-Boot can boot with
this chip.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---

Changes in v3:
- Unset configs MMC_IO_VOLTAGE, MMC_UHS_SUPPORT, MMC_HS400_SUPPORT,
  MMC_HS400_ES_SUPPORT, MMC_SDHCI_SDMA.
- Add tag: "Reviewed-by: Kever Yang <kever.yang@rock-chips.com>"

 configs/chromebook_bob_defconfig | 22 +++++++++++++++++++++-
 include/configs/gru.h            |  3 +++
 2 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig
index fe938c659172..3f6c088352eb 100644
--- a/configs/chromebook_bob_defconfig
+++ b/configs/chromebook_bob_defconfig
@@ -21,6 +21,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_MISC_INIT_R=y
 CONFIG_BLOBLIST=y
 CONFIG_BLOBLIST_SIZE=0x1000
 CONFIG_BLOBLIST_ADDR=0x100000
@@ -52,8 +53,9 @@ CONFIG_ROCKCHIP_GPIO=y
 CONFIG_I2C_CROS_EC_TUNNEL=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_I2C_MUX=y
-CONFIG_DM_KEYBOARD=y
 CONFIG_CROS_EC_KEYB=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_SPI=y
 CONFIG_PWRSEQ=y
@@ -65,13 +67,21 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
 CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_CROS_EC=y
 CONFIG_PWM_ROCKCHIP=y
+CONFIG_DM_RESET=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y
@@ -80,11 +90,21 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_KEYBOARD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_ASIX88179=y
 CONFIG_USB_ETHER_MCS7830=y
 CONFIG_USB_ETHER_RTL8152=y
 CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_VIDEO_ROCKCHIP_MAX_XRES=1280
+CONFIG_VIDEO_ROCKCHIP_MAX_YRES=800
+CONFIG_DISPLAY_ROCKCHIP_EDP=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
diff --git a/include/configs/gru.h b/include/configs/gru.h
index be2dc79968c0..b1084bb21d4d 100644
--- a/include/configs/gru.h
+++ b/include/configs/gru.h
@@ -13,4 +13,7 @@
 
 #include <configs/rk3399_common.h>
 
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+
 #endif
-- 
2.34.1

[PATCH v3 4/4] rockchip: rk3399: Add support for chromebook_kevin

[Alper Nebi Yasak]

From: "Marty E. Plummer" <hanetzer@startmail.com>

Add support for Kevin, an RK3399-based convertible chromebook that is
very similar to Bob. This patch is mostly based on existing support for
Bob, with only minor changes for Kevin-specific things.

Unlike other Gru boards, coreboot sets Kevin's center logic to 925 mV,
so adjust it here in the dts as well. The rk3399-gru-kevin devicetree
has an unknown event code reference which has to be defined, set it
to the Linux counterpart. The new defconfig is copied from Bob with the
diffconfig:

     DEFAULT_DEVICE_TREE "rk3399-gru-bob" -> "rk3399-gru-kevin"
     DEFAULT_FDT_FILE "rockchip/rk3399-gru-bob.dtb" -> "rockchip/rk3399-gru-kevin.dtb"
     VIDEO_ROCKCHIP_MAX_XRES 1280 -> 2400
     VIDEO_ROCKCHIP_MAX_YRES 800 -> 1600
    +TARGET_CHROMEBOOK_KEVIN y

With this Kevin can boot from SPI flash to a usable U-Boot prompt on the
display with the keyboard working, but cannot boot into Linux for
unknown reasons.

eMMC starts in a working state but fails to re-init, microSD card works
but at a lower-than-expected speed, USB works but causes a hang on
de-init. There are known workarounds to solve eMMC and USB issues.

Cc: Marty E. Plummer <hanetzer@startmail.com>
Cc: Simon Glass <sjg@chromium.org>
[Alper: commit message, resync config with Bob, update MAINTAINERS,
        add to Rockchip doc, add Kconfig help message, set regulator]
Co-developed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
Marty had signed-off an earlier version of this [1], but not the updated
version I continued on top of [2]. So I'm not sure if I can add his
sign-off to this as is, and I hope he can reply to this with a sign-off.

[1] https://patchwork.ozlabs.org/patch/1053386/
[2] https://patchwork.ozlabs.org/comment/2488899/

Changes in v3:
- Unset configs MMC_IO_VOLTAGE, MMC_UHS_SUPPORT, MMC_HS400_SUPPORT,
  MMC_HS400_ES_SUPPORT, MMC_SDHCI_SDMA.
- Add tag: "Reviewed-by: Kever Yang <kever.yang@rock-chips.com>"

Changes in v2:
- Rebase on u-boot/next, fixing conflict in board_debug_uart_init()

 arch/arm/dts/Makefile                         |   1 +
 arch/arm/dts/rk3399-gru-kevin-u-boot.dtsi     |  11 ++
 arch/arm/mach-rockchip/rk3399/Kconfig         |  11 ++
 arch/arm/mach-rockchip/rk3399/rk3399.c        |   3 +-
 arch/arm/mach-rockchip/spl.c                  |   3 +-
 board/google/gru/Kconfig                      |  16 +++
 board/google/gru/MAINTAINERS                  |   8 ++
 board/google/gru/gru.c                        |   2 +-
 configs/chromebook_kevin_defconfig            | 111 ++++++++++++++++++
 doc/board/rockchip/rockchip.rst               |   1 +
 include/dt-bindings/input/linux-event-codes.h |   3 +-
 11 files changed, 166 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/dts/rk3399-gru-kevin-u-boot.dtsi
 create mode 100644 configs/chromebook_kevin_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7f622fedbda7..d6883994f21a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -132,6 +132,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
 	rk3399-ficus.dtb \
 	rk3399-firefly.dtb \
 	rk3399-gru-bob.dtb \
+	rk3399-gru-kevin.dtb \
 	rk3399-khadas-edge.dtb \
 	rk3399-khadas-edge-captain.dtb \
 	rk3399-khadas-edge-v.dtb \
diff --git a/arch/arm/dts/rk3399-gru-kevin-u-boot.dtsi b/arch/arm/dts/rk3399-gru-kevin-u-boot.dtsi
new file mode 100644
index 000000000000..c03bd48e95d7
--- /dev/null
+++ b/arch/arm/dts/rk3399-gru-kevin-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "rk3399-gru-u-boot.dtsi"
+#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"
+
+&ppvar_centerlogic_pwm {
+	regulator-init-microvolt = <925000>;
+};
diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig
index 17628f917127..0833e083d9ef 100644
--- a/arch/arm/mach-rockchip/rk3399/Kconfig
+++ b/arch/arm/mach-rockchip/rk3399/Kconfig
@@ -14,6 +14,17 @@ config TARGET_CHROMEBOOK_BOB
 	  display. It includes a Chrome OS EC (Cortex-M3) to provide access to
 	  the keyboard and battery functions.
 
+config TARGET_CHROMEBOOK_KEVIN
+	bool "Samsung Chromebook Plus (RK3399)"
+	select HAS_ROM
+	select ROCKCHIP_SPI_IMAGE
+	help
+	  Kevin is a RK3399-based convertible chromebook. It has two USB 3.0
+	  Type-C ports, 4GB of SDRAM, WiFi and a 12.3" 2400x1600 display. It
+	  uses its USB ports for both power and external display. It includes
+	  a Chromium OS EC (Cortex-M3) to provide access to the keyboard and
+	  battery functions.
+
 config TARGET_EVB_RK3399
 	bool "RK3399 evaluation board"
 	help
diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c
index d40969c88898..01a05599cd0d 100644
--- a/arch/arm/mach-rockchip/rk3399/rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
@@ -140,7 +140,8 @@ void board_debug_uart_init(void)
 	struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
 
 	if (IS_ENABLED(CONFIG_SPL_BUILD) &&
-	    IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_BOB)) {
+	    (IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_BOB) ||
+	     IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_KEVIN))) {
 		rk_setreg(&grf->io_vsel, 1 << 0);
 
 		/*
diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c
index 02c40fb37ed6..7a8db632b80c 100644
--- a/arch/arm/mach-rockchip/spl.c
+++ b/arch/arm/mach-rockchip/spl.c
@@ -56,7 +56,8 @@ u32 spl_boot_device(void)
 		defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
 		defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \
 		defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY) || \
-		defined(CONFIG_TARGET_CHROMEBOOK_BOB)
+		defined(CONFIG_TARGET_CHROMEBOOK_BOB) || \
+		defined(CONFIG_TARGET_CHROMEBOOK_KEVIN)
 	return BOOT_DEVICE_SPI;
 #endif
 	if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
diff --git a/board/google/gru/Kconfig b/board/google/gru/Kconfig
index 61f7bbca989b..1455e1481dc2 100644
--- a/board/google/gru/Kconfig
+++ b/board/google/gru/Kconfig
@@ -13,3 +13,19 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 
 endif
+
+if TARGET_CHROMEBOOK_KEVIN
+
+config SYS_BOARD
+	default "gru"
+
+config SYS_VENDOR
+	default "google"
+
+config SYS_CONFIG_NAME
+	default "gru"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/board/google/gru/MAINTAINERS b/board/google/gru/MAINTAINERS
index e1cda756b8c8..53257c52a04b 100644
--- a/board/google/gru/MAINTAINERS
+++ b/board/google/gru/MAINTAINERS
@@ -4,3 +4,11 @@ S:	Maintained
 F:	board/google/gru/
 F:	include/configs/gru.h
 F:	configs/chromebook_bob_defconfig
+
+CHROMEBOOK KEVIN BOARD
+M:	Simon Glass <sjg@chromium.org>
+M:	Alper Nebi Yasak <alpernebiyasak@gmail.com>
+S:	Maintained
+F:	board/google/gru/
+F:	include/configs/gru.h
+F:	configs/chromebook_kevin_defconfig
diff --git a/board/google/gru/gru.c b/board/google/gru/gru.c
index cbf62a9427c9..fbcf845e87dd 100644
--- a/board/google/gru/gru.c
+++ b/board/google/gru/gru.c
@@ -26,7 +26,7 @@ void gru_dummy_function(int i)
 
 int board_early_init_f(void)
 {
-# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
+# if defined(CONFIG_TARGET_CHROMEBOOK_BOB) || defined(CONFIG_TARGET_CHROMEBOOK_KEVIN)
 	int sum, i;
 
 	/*
diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig
new file mode 100644
index 000000000000..831a6d3822b8
--- /dev/null
+++ b/configs/chromebook_kevin_defconfig
@@ -0,0 +1,111 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-kevin"
+CONFIG_SPL_TEXT_BASE=0xff8c2000
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_BOOT_MODE_REG=0
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
+# CONFIG_SPL_MMC is not set
+CONFIG_TARGET_CHROMEBOOK_KEVIN=y
+CONFIG_DEBUG_UART_BASE=0xff1a0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-kevin.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_MISC_INIT_R=y
+CONFIG_BLOBLIST=y
+CONFIG_BLOBLIST_SIZE=0x1000
+CONFIG_BLOBLIST_ADDR=0x100000
+CONFIG_HANDOFF=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_LOG=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_I2C_CROS_EC_TUNNEL=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_I2C_MUX=y
+CONFIG_CROS_EC_KEYB=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_SPI=y
+CONFIG_PWRSEQ=y
+CONFIG_MMC_PWRSEQ=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_CROS_EC=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_DM_RESET=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_VIDEO_ROCKCHIP_MAX_XRES=2400
+CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1600
+CONFIG_DISPLAY_ROCKCHIP_EDP=y
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_ERRNO_STR=y
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 144cb98ef941..a75e60b9fa30 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -66,6 +66,7 @@ List of mainline supported Rockchip boards:
      - FriendlyElec NanoPi M4B (nanopi-m4b-rk3399)
      - FriendlyARM NanoPi NEO4 (nanopi-neo4-rk3399)
      - Google Bob (chromebook_bob)
+     - Google Kevin (chromebook_kevin)
      - Khadas Edge (khadas-edge-rk3399)
      - Khadas Edge-Captain (khadas-edge-captain-rk3399)
      - Khadas Edge-V (hadas-edge-v-rk3399)
diff --git a/include/dt-bindings/input/linux-event-codes.h b/include/dt-bindings/input/linux-event-codes.h
index 87cf351bab03..331458c0e710 100644
--- a/include/dt-bindings/input/linux-event-codes.h
+++ b/include/dt-bindings/input/linux-event-codes.h
@@ -749,7 +749,8 @@
 #define SW_ROTATE_LOCK		0x0c  /* set = rotate locked/disabled */
 #define SW_LINEIN_INSERT	0x0d  /* set = inserted */
 #define SW_MUTE_DEVICE		0x0e  /* set = device disabled */
-#define SW_MAX			0x0f
+#define SW_PEN_INSERTED		0x0f  /* set = pen inserted */
+#define SW_MAX			0x10
 #define SW_CNT			(SW_MAX+1)
 
 /*
-- 
2.34.1

Re: [PATCH v3 1/4] rockchip: gru: Set up SoC IO domain registers

[Simon Glass]

On Fri, 24 Dec 2021 at 06:44, Alper Nebi Yasak <alpernebiyasak@gmail.com> wrote:
>
> The RK3399 SoC needs to know the voltage value provided by some
> regulators, which is done by setting relevant register bits. Configure
> these the way other RK3399 boards do, but with the same values as are
> set in the equivalent code in coreboot.
>
> Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> There is a driver for this on Rockchip's repo, I managed to forward-port
> it and get it working. If that's more desirable than doing it per-board
> like this I can send that upstream (but I'd prefer to do it after this).
>
> Changes in v3:
> - Add tag: "Reviewed-by: Kever Yang <kever.yang@rock-chips.com>"
>
> Changes in v2:
> - Drop unnecessary ifdef.
> - Clarify commit message regarding 'values set in coreboot'.
>
>  board/google/gru/gru.c | 52 ++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 52 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on bob, kevin
Tested-by: Simon Glass <sjg@chromium.org>

Yes I think a driver would be a good idea.

Re: [PATCH v3 2/4] rockchip: gru: Add more devicetree settings

[Simon Glass]

On Fri, 24 Dec 2021 at 06:44, Alper Nebi Yasak <alpernebiyasak@gmail.com> wrote:
>
> From: Simon Glass <sjg@chromium.org>
>
> This adds some devicetree settings for the Gru-based boards, based on
> what works on a Kevin board.
>
> Gru-based boards usually have an 8MiB SPI flash chip and boot from it.
> Make the u-boot.rom file intended to be flashed on it match its size.
> Add properties for booting from SPI, and only try to boot from SPI as
> MMC and SD card don't seem to work in SPL yet.
>
> The Chromium OS EC needs a delay between transactions so it can get
> itself ready. Also it currently uses a non-standard way of specifying
> the interrupt. Add these so that the EC works reliably.
>
> The Rockchip Embedded DisplayPort driver is looking for a rockchip,panel
> property to find the panel it should work on. Add the property for the
> Gru-based boards.
>
> The U-Boot GPIO controlled regulator driver only considers the
> "enable-gpios" devicetree property, not the singular "enable-gpio" one.
> Some devicetree source files have the singular form as they were added
> to Linux kernel when it used that form, and imported to U-Boot as is.
> Fix one instance of this in the Gru boards' devicetree to the form that
> works in U-Boot.
>
> The PWM controlled regulator driver complains that there is no init
> voltage set for a regulator it drives, though it's not clear which one.
> Set them all to the voltage levels coreboot sets them: 900 mV.
>
> The RK3399 SoC needs to know the voltage level that some supplies
> provides, including one fixed 1.8V audio-related regulator. Although
> this synchronization is currently statically done in the board init
> functions, a not-so-hypothetical driver that does this dynamically would
> query the regulator only to get -ENODATA and be confused. Make sure
> U-Boot knows this supply is at 1.8V by setting its limits to that.
>
> Most of this is a reapplication of commit 08c85b57a5ec ("rockchip: gru:
> Add extra device-tree settings") whose changes were removed during a
> sync with Linux at commit 167efc2c7a46 ("arm64: dts: rk3399: Sync
> v5.7-rc1 from Linux"). Apply things to rk3399-gru-u-boot.dtsi instead so
> they don't get lost again.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> [Alper: move to -u-boot.dtsi, rewrite commit message, add more nodes]
> Co-developed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
> Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> Kept sign-off and author as Simon based on the aforementioned commit.
>
> Changes in v3:
> - Add tag: "Reviewed-by: Kever Yang <kever.yang@rock-chips.com>"
>
>  arch/arm/dts/rk3399-gru-u-boot.dtsi | 55 +++++++++++++++++++++++++++++
>  1 file changed, 55 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on bob, kevin
Tested-by: Simon Glass <sjg@chromium.org>

Re: [PATCH v3 3/4] rockchip: bob: Enable more configs

[Simon Glass]

On Fri, 24 Dec 2021 at 06:44, Alper Nebi Yasak <alpernebiyasak@gmail.com> wrote:
>
> This patch enables some configs that should be working on the Bob board,
> based on what is observed to work on the Kevin board.
>
> The Bob board uses an Embedded DisplayPort panel compatible with the
> simple panel and Rockchip eDP drivers. Its backlight is controlled by
> the Chromium OS Embedded Controller Pulse Width Modulator. Enable these
> for the board.
>
> Also set VIDEO_ROCKCHIP_MAX_{XRES,YRES} to 1280x800, the resolution of
> its panel. This had to be done for the Kevin board, but it's untested if
> this is actually necessary for Bob.
>
> The Rockchip video driver needs to assert/deassert some resets, so also
> enable the reset controller. RESET_ROCKCHIP defaults to y for this board
> when DM_RESET=y, so it's enough to set that.
>
> The Bob board has two USB 3.0 Type-C ports and one USB 2.0 Type-A port
> on its right side. Enable the configs relevant to USB devices so these
> can be used. This is despite a known issue with RK3399 boards where USB
> de-init causes a hang, as there is a known workaround.
>
> Some other rk3399-based devices enable support for the SoC's random
> number generator in commit a475bef5340c ("configs: rk3399: enable rng on
> firefly/rock960/rockpro64"), as it can provide a KASLR seed when booting
> using UEFI. Enable it for Bob as well.
>
> The default misc_init_r() for Rockchip boards sets cpuid and ethernet
> MAC address based on e-fuse block. A previous patch extends this on Gru
> boards to set registers related to SoC IO domains as is necessary on
> these boards. Enable this function and configs for it on Bob.
>
> The microSD card slot on this board (and others based on Gru) is
> connected to a GPIO controlled regulator (ppvar-sd-card-io), which must
> be operable by U-Boot. Enable the relevant config option to allow this.
>
> Bob boards also use the Winbond W25Q64DW SPI flash chip, enable support
> for Winbond SPI flash chips in the board config so U-Boot can boot with
> this chip.
>
> Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> Changes in v3:
> - Unset configs MMC_IO_VOLTAGE, MMC_UHS_SUPPORT, MMC_HS400_SUPPORT,
>   MMC_HS400_ES_SUPPORT, MMC_SDHCI_SDMA.
> - Add tag: "Reviewed-by: Kever Yang <kever.yang@rock-chips.com>"
>
>  configs/chromebook_bob_defconfig | 22 +++++++++++++++++++++-
>  include/configs/gru.h            |  3 +++
>  2 files changed, 24 insertions(+), 1 deletion(-)
>

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on bob, kevin
Tested-by: Simon Glass <sjg@chromium.org>

Re: [PATCH v3 4/4] rockchip: rk3399: Add support for chromebook_kevin

[Simon Glass]

On Fri, 24 Dec 2021 at 06:44, Alper Nebi Yasak <alpernebiyasak@gmail.com> wrote:
>
> From: "Marty E. Plummer" <hanetzer@startmail.com>
>
> Add support for Kevin, an RK3399-based convertible chromebook that is
> very similar to Bob. This patch is mostly based on existing support for
> Bob, with only minor changes for Kevin-specific things.
>
> Unlike other Gru boards, coreboot sets Kevin's center logic to 925 mV,
> so adjust it here in the dts as well. The rk3399-gru-kevin devicetree
> has an unknown event code reference which has to be defined, set it
> to the Linux counterpart. The new defconfig is copied from Bob with the
> diffconfig:
>
>      DEFAULT_DEVICE_TREE "rk3399-gru-bob" -> "rk3399-gru-kevin"
>      DEFAULT_FDT_FILE "rockchip/rk3399-gru-bob.dtb" -> "rockchip/rk3399-gru-kevin.dtb"
>      VIDEO_ROCKCHIP_MAX_XRES 1280 -> 2400
>      VIDEO_ROCKCHIP_MAX_YRES 800 -> 1600
>     +TARGET_CHROMEBOOK_KEVIN y
>
> With this Kevin can boot from SPI flash to a usable U-Boot prompt on the
> display with the keyboard working, but cannot boot into Linux for
> unknown reasons.
>
> eMMC starts in a working state but fails to re-init, microSD card works
> but at a lower-than-expected speed, USB works but causes a hang on
> de-init. There are known workarounds to solve eMMC and USB issues.
>
> Cc: Marty E. Plummer <hanetzer@startmail.com>
> Cc: Simon Glass <sjg@chromium.org>
> [Alper: commit message, resync config with Bob, update MAINTAINERS,
>         add to Rockchip doc, add Kconfig help message, set regulator]
> Co-developed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
> Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> Marty had signed-off an earlier version of this [1], but not the updated
> version I continued on top of [2]. So I'm not sure if I can add his
> sign-off to this as is, and I hope he can reply to this with a sign-off.
>
> [1] https://patchwork.ozlabs.org/patch/1053386/
> [2] https://patchwork.ozlabs.org/comment/2488899/
>
> Changes in v3:
> - Unset configs MMC_IO_VOLTAGE, MMC_UHS_SUPPORT, MMC_HS400_SUPPORT,
>   MMC_HS400_ES_SUPPORT, MMC_SDHCI_SDMA.
> - Add tag: "Reviewed-by: Kever Yang <kever.yang@rock-chips.com>"
>
> Changes in v2:
> - Rebase on u-boot/next, fixing conflict in board_debug_uart_init()
>
>  arch/arm/dts/Makefile                         |   1 +
>  arch/arm/dts/rk3399-gru-kevin-u-boot.dtsi     |  11 ++
>  arch/arm/mach-rockchip/rk3399/Kconfig         |  11 ++
>  arch/arm/mach-rockchip/rk3399/rk3399.c        |   3 +-
>  arch/arm/mach-rockchip/spl.c                  |   3 +-
>  board/google/gru/Kconfig                      |  16 +++
>  board/google/gru/MAINTAINERS                  |   8 ++
>  board/google/gru/gru.c                        |   2 +-
>  configs/chromebook_kevin_defconfig            | 111 ++++++++++++++++++
>  doc/board/rockchip/rockchip.rst               |   1 +
>  include/dt-bindings/input/linux-event-codes.h |   3 +-
>  11 files changed, 166 insertions(+), 4 deletions(-)
>  create mode 100644 arch/arm/dts/rk3399-gru-kevin-u-boot.dtsi
>  create mode 100644 configs/chromebook_kevin_defconfig

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on bob, kevin
Tested-by: Simon Glass <sjg@chromium.org>

Re: [PATCH v3 1/4] rockchip: gru: Set up SoC IO domain registers

[Jagan Teki]

On Fri, Dec 24, 2021 at 7:14 PM Alper Nebi Yasak
<alpernebiyasak@gmail.com> wrote:
>
> The RK3399 SoC needs to know the voltage value provided by some
> regulators, which is done by setting relevant register bits. Configure
> these the way other RK3399 boards do, but with the same values as are
> set in the equivalent code in coreboot.
>
> Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> There is a driver for this on Rockchip's repo, I managed to forward-port
> it and get it working. If that's more desirable than doing it per-board
> like this I can send that upstream (but I'd prefer to do it after this).
>
> Changes in v3:
> - Add tag: "Reviewed-by: Kever Yang <kever.yang@rock-chips.com>"
>
> Changes in v2:
> - Drop unnecessary ifdef.
> - Clarify commit message regarding 'values set in coreboot'.
>
>  board/google/gru/gru.c | 52 ++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 52 insertions(+)
>
> diff --git a/board/google/gru/gru.c b/board/google/gru/gru.c
> index 23080c1798b7..cbf62a9427c9 100644
> --- a/board/google/gru/gru.c
> +++ b/board/google/gru/gru.c
> @@ -6,6 +6,17 @@
>  #include <common.h>
>  #include <dm.h>
>  #include <init.h>
> +#include <syscon.h>
> +#include <asm/io.h>
> +#include <asm/arch-rockchip/clock.h>
> +#include <asm/arch-rockchip/grf_rk3399.h>
> +#include <asm/arch-rockchip/hardware.h>
> +#include <asm/arch-rockchip/misc.h>
> +
> +#define GRF_IO_VSEL_BT656_SHIFT 0
> +#define GRF_IO_VSEL_AUDIO_SHIFT 1
> +#define PMUGRF_CON0_VSEL_SHIFT 8
> +#define PMUGRF_CON0_VOL_SHIFT 9
>
>  #ifdef CONFIG_SPL_BUILD
>  /* provided to defeat compiler optimisation in board_init_f() */
> @@ -54,3 +65,44 @@ int board_early_init_r(void)
>         return 0;
>  }
>  #endif
> +
> +static void setup_iodomain(void)
> +{
> +       struct rk3399_grf_regs *grf =
> +          syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> +       struct rk3399_pmugrf_regs *pmugrf =
> +          syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
> +
> +       /* BT656 and audio is in 1.8v domain */
> +       rk_setreg(&grf->io_vsel, (1 << GRF_IO_VSEL_BT656_SHIFT |
> +                                 1 << GRF_IO_VSEL_AUDIO_SHIFT));
> +
> +       /*
> +        * Set GPIO1 1.8v/3.0v source select to PMU1830_VOL
> +        * and explicitly configure that PMU1830_VOL to be 1.8V
> +        */
> +       rk_setreg(&pmugrf->soc_con0, (1 << PMUGRF_CON0_VSEL_SHIFT |
> +                                     1 << PMUGRF_CON0_VOL_SHIFT));
> +}
> +
> +int misc_init_r(void)
> +{
> +       const u32 cpuid_offset = 0x7;
> +       const u32 cpuid_length = 0x10;
> +       u8 cpuid[cpuid_length];
> +       int ret;
> +
> +       setup_iodomain();
> +
> +       ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
> +       if (ret)
> +               return ret;
> +
> +       ret = rockchip_cpuid_set(cpuid, cpuid_length);
> +       if (ret)
> +               return ret;
> +
> +       ret = rockchip_setup_macaddr();
> +
> +       return ret;
> +}

This looks like a board hack code for me, which is difficult to
maintain in the long run. Better go with UCLASS_POWER_DOMAIN, I
believe it would be a straightforward implementation.

Thanks,
Jagan.

Re: [PATCH v3 3/4] rockchip: bob: Enable more configs

[Jagan Teki]

On Fri, Dec 24, 2021 at 7:14 PM Alper Nebi Yasak
<alpernebiyasak@gmail.com> wrote:
>
> This patch enables some configs that should be working on the Bob board,
> based on what is observed to work on the Kevin board.
>
> The Bob board uses an Embedded DisplayPort panel compatible with the
> simple panel and Rockchip eDP drivers. Its backlight is controlled by
> the Chromium OS Embedded Controller Pulse Width Modulator. Enable these
> for the board.
>
> Also set VIDEO_ROCKCHIP_MAX_{XRES,YRES} to 1280x800, the resolution of
> its panel. This had to be done for the Kevin board, but it's untested if
> this is actually necessary for Bob.
>
> The Rockchip video driver needs to assert/deassert some resets, so also
> enable the reset controller. RESET_ROCKCHIP defaults to y for this board
> when DM_RESET=y, so it's enough to set that.
>
> The Bob board has two USB 3.0 Type-C ports and one USB 2.0 Type-A port
> on its right side. Enable the configs relevant to USB devices so these
> can be used. This is despite a known issue with RK3399 boards where USB
> de-init causes a hang, as there is a known workaround.
>
> Some other rk3399-based devices enable support for the SoC's random
> number generator in commit a475bef5340c ("configs: rk3399: enable rng on
> firefly/rock960/rockpro64"), as it can provide a KASLR seed when booting
> using UEFI. Enable it for Bob as well.
>
> The default misc_init_r() for Rockchip boards sets cpuid and ethernet
> MAC address based on e-fuse block. A previous patch extends this on Gru
> boards to set registers related to SoC IO domains as is necessary on
> these boards. Enable this function and configs for it on Bob.
>
> The microSD card slot on this board (and others based on Gru) is
> connected to a GPIO controlled regulator (ppvar-sd-card-io), which must
> be operable by U-Boot. Enable the relevant config option to allow this.
>
> Bob boards also use the Winbond W25Q64DW SPI flash chip, enable support
> for Winbond SPI flash chips in the board config so U-Boot can boot with
> this chip.
>
> Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> Changes in v3:
> - Unset configs MMC_IO_VOLTAGE, MMC_UHS_SUPPORT, MMC_HS400_SUPPORT,
>   MMC_HS400_ES_SUPPORT, MMC_SDHCI_SDMA.
> - Add tag: "Reviewed-by: Kever Yang <kever.yang@rock-chips.com>"
>
>  configs/chromebook_bob_defconfig | 22 +++++++++++++++++++++-
>  include/configs/gru.h            |  3 +++
>  2 files changed, 24 insertions(+), 1 deletion(-)
>
> diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig
> index fe938c659172..3f6c088352eb 100644
> --- a/configs/chromebook_bob_defconfig
> +++ b/configs/chromebook_bob_defconfig
> @@ -21,6 +21,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb"
>  # CONFIG_DISPLAY_CPUINFO is not set
>  CONFIG_DISPLAY_BOARDINFO_LATE=y
>  CONFIG_BOARD_EARLY_INIT_R=y
> +CONFIG_MISC_INIT_R=y
>  CONFIG_BLOBLIST=y
>  CONFIG_BLOBLIST_SIZE=0x1000
>  CONFIG_BLOBLIST_ADDR=0x100000
> @@ -52,8 +53,9 @@ CONFIG_ROCKCHIP_GPIO=y
>  CONFIG_I2C_CROS_EC_TUNNEL=y
>  CONFIG_SYS_I2C_ROCKCHIP=y
>  CONFIG_I2C_MUX=y
> -CONFIG_DM_KEYBOARD=y
>  CONFIG_CROS_EC_KEYB=y
> +CONFIG_MISC=y
> +CONFIG_ROCKCHIP_EFUSE=y
>  CONFIG_CROS_EC=y
>  CONFIG_CROS_EC_SPI=y
>  CONFIG_PWRSEQ=y
> @@ -65,13 +67,21 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y
>  CONFIG_SF_DEFAULT_BUS=1
>  CONFIG_SF_DEFAULT_SPEED=20000000
>  CONFIG_SPI_FLASH_GIGADEVICE=y
> +CONFIG_SPI_FLASH_WINBOND=y
>  CONFIG_DM_ETH=y
>  CONFIG_ETH_DESIGNWARE=y
>  CONFIG_GMAC_ROCKCHIP=y
> +CONFIG_PHY_ROCKCHIP_INNO_USB2=y
> +CONFIG_PHY_ROCKCHIP_TYPEC=y
>  CONFIG_PMIC_RK8XX=y
>  CONFIG_REGULATOR_PWM=y
> +CONFIG_DM_REGULATOR_GPIO=y
>  CONFIG_REGULATOR_RK8XX=y
> +CONFIG_PWM_CROS_EC=y
>  CONFIG_PWM_ROCKCHIP=y
> +CONFIG_DM_RESET=y
> +CONFIG_DM_RNG=y
> +CONFIG_RNG_ROCKCHIP=y
>  CONFIG_DEBUG_UART_SHIFT=2
>  CONFIG_ROCKCHIP_SPI=y
>  CONFIG_SYSRESET=y
> @@ -80,11 +90,21 @@ CONFIG_USB_XHCI_HCD=y
>  CONFIG_USB_XHCI_DWC3=y
>  CONFIG_USB_EHCI_HCD=y
>  CONFIG_USB_EHCI_GENERIC=y
> +CONFIG_USB_OHCI_HCD=y
> +CONFIG_USB_OHCI_GENERIC=y
> +CONFIG_USB_DWC3=y
> +CONFIG_USB_KEYBOARD=y
>  CONFIG_USB_HOST_ETHER=y
>  CONFIG_USB_ETHER_ASIX=y
>  CONFIG_USB_ETHER_ASIX88179=y
>  CONFIG_USB_ETHER_MCS7830=y
>  CONFIG_USB_ETHER_RTL8152=y
>  CONFIG_USB_ETHER_SMSC95XX=y
> +CONFIG_DM_VIDEO=y
> +CONFIG_DISPLAY=y
> +CONFIG_VIDEO_ROCKCHIP=y
> +CONFIG_VIDEO_ROCKCHIP_MAX_XRES=1280
> +CONFIG_VIDEO_ROCKCHIP_MAX_YRES=800
> +CONFIG_DISPLAY_ROCKCHIP_EDP=y
>  CONFIG_CMD_DHRYSTONE=y
>  CONFIG_ERRNO_STR=y
> diff --git a/include/configs/gru.h b/include/configs/gru.h
> index be2dc79968c0..b1084bb21d4d 100644
> --- a/include/configs/gru.h
> +++ b/include/configs/gru.h
> @@ -13,4 +13,7 @@
>
>  #include <configs/rk3399_common.h>
>
> +#define CONFIG_USB_OHCI_NEW
> +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS     2

Can you move them to Kconfig?

Jagan.

Re: [PATCH v3 4/4] rockchip: rk3399: Add support for chromebook_kevin

[Jagan Teki]

On Fri, Dec 24, 2021 at 7:14 PM Alper Nebi Yasak
<alpernebiyasak@gmail.com> wrote:
>
> From: "Marty E. Plummer" <hanetzer@startmail.com>
>
> Add support for Kevin, an RK3399-based convertible chromebook that is
> very similar to Bob. This patch is mostly based on existing support for
> Bob, with only minor changes for Kevin-specific things.
>
> Unlike other Gru boards, coreboot sets Kevin's center logic to 925 mV,
> so adjust it here in the dts as well. The rk3399-gru-kevin devicetree
> has an unknown event code reference which has to be defined, set it
> to the Linux counterpart. The new defconfig is copied from Bob with the
> diffconfig:
>
>      DEFAULT_DEVICE_TREE "rk3399-gru-bob" -> "rk3399-gru-kevin"
>      DEFAULT_FDT_FILE "rockchip/rk3399-gru-bob.dtb" -> "rockchip/rk3399-gru-kevin.dtb"
>      VIDEO_ROCKCHIP_MAX_XRES 1280 -> 2400
>      VIDEO_ROCKCHIP_MAX_YRES 800 -> 1600
>     +TARGET_CHROMEBOOK_KEVIN y
>
> With this Kevin can boot from SPI flash to a usable U-Boot prompt on the
> display with the keyboard working, but cannot boot into Linux for
> unknown reasons.
>
> eMMC starts in a working state but fails to re-init, microSD card works
> but at a lower-than-expected speed, USB works but causes a hang on
> de-init. There are known workarounds to solve eMMC and USB issues.
>
> Cc: Marty E. Plummer <hanetzer@startmail.com>
> Cc: Simon Glass <sjg@chromium.org>
> [Alper: commit message, resync config with Bob, update MAINTAINERS,
>         add to Rockchip doc, add Kconfig help message, set regulator]
> Co-developed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
> Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> Marty had signed-off an earlier version of this [1], but not the updated
> version I continued on top of [2]. So I'm not sure if I can add his
> sign-off to this as is, and I hope he can reply to this with a sign-off.
>
> [1] https://patchwork.ozlabs.org/patch/1053386/
> [2] https://patchwork.ozlabs.org/comment/2488899/
>
> Changes in v3:
> - Unset configs MMC_IO_VOLTAGE, MMC_UHS_SUPPORT, MMC_HS400_SUPPORT,
>   MMC_HS400_ES_SUPPORT, MMC_SDHCI_SDMA.
> - Add tag: "Reviewed-by: Kever Yang <kever.yang@rock-chips.com>"
>
> Changes in v2:
> - Rebase on u-boot/next, fixing conflict in board_debug_uart_init()
>
>  arch/arm/dts/Makefile                         |   1 +
>  arch/arm/dts/rk3399-gru-kevin-u-boot.dtsi     |  11 ++
>  arch/arm/mach-rockchip/rk3399/Kconfig         |  11 ++
>  arch/arm/mach-rockchip/rk3399/rk3399.c        |   3 +-
>  arch/arm/mach-rockchip/spl.c                  |   3 +-
>  board/google/gru/Kconfig                      |  16 +++
>  board/google/gru/MAINTAINERS                  |   8 ++
>  board/google/gru/gru.c                        |   2 +-
>  configs/chromebook_kevin_defconfig            | 111 ++++++++++++++++++
>  doc/board/rockchip/rockchip.rst               |   1 +
>  include/dt-bindings/input/linux-event-codes.h |   3 +-
>  11 files changed, 166 insertions(+), 4 deletions(-)
>  create mode 100644 arch/arm/dts/rk3399-gru-kevin-u-boot.dtsi
>  create mode 100644 configs/chromebook_kevin_defconfig
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 7f622fedbda7..d6883994f21a 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -132,6 +132,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
>         rk3399-ficus.dtb \
>         rk3399-firefly.dtb \
>         rk3399-gru-bob.dtb \
> +       rk3399-gru-kevin.dtb \
>         rk3399-khadas-edge.dtb \
>         rk3399-khadas-edge-captain.dtb \
>         rk3399-khadas-edge-v.dtb \
> diff --git a/arch/arm/dts/rk3399-gru-kevin-u-boot.dtsi b/arch/arm/dts/rk3399-gru-kevin-u-boot.dtsi
> new file mode 100644
> index 000000000000..c03bd48e95d7
> --- /dev/null
> +++ b/arch/arm/dts/rk3399-gru-kevin-u-boot.dtsi
> @@ -0,0 +1,11 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
> + */
> +
> +#include "rk3399-gru-u-boot.dtsi"
> +#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"
> +
> +&ppvar_centerlogic_pwm {
> +       regulator-init-microvolt = <925000>;
> +};
> diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig
> index 17628f917127..0833e083d9ef 100644
> --- a/arch/arm/mach-rockchip/rk3399/Kconfig
> +++ b/arch/arm/mach-rockchip/rk3399/Kconfig
> @@ -14,6 +14,17 @@ config TARGET_CHROMEBOOK_BOB
>           display. It includes a Chrome OS EC (Cortex-M3) to provide access to
>           the keyboard and battery functions.
>
> +config TARGET_CHROMEBOOK_KEVIN
> +       bool "Samsung Chromebook Plus (RK3399)"
> +       select HAS_ROM
> +       select ROCKCHIP_SPI_IMAGE
> +       help
> +         Kevin is a RK3399-based convertible chromebook. It has two USB 3.0
> +         Type-C ports, 4GB of SDRAM, WiFi and a 12.3" 2400x1600 display. It
> +         uses its USB ports for both power and external display. It includes
> +         a Chromium OS EC (Cortex-M3) to provide access to the keyboard and
> +         battery functions.
> +
>  config TARGET_EVB_RK3399
>         bool "RK3399 evaluation board"
>         help
> diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c
> index d40969c88898..01a05599cd0d 100644
> --- a/arch/arm/mach-rockchip/rk3399/rk3399.c
> +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
> @@ -140,7 +140,8 @@ void board_debug_uart_init(void)
>         struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
>
>         if (IS_ENABLED(CONFIG_SPL_BUILD) &&
> -           IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_BOB)) {
> +           (IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_BOB) ||
> +            IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_KEVIN))) {
>                 rk_setreg(&grf->io_vsel, 1 << 0);
>
>                 /*
> diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c
> index 02c40fb37ed6..7a8db632b80c 100644
> --- a/arch/arm/mach-rockchip/spl.c
> +++ b/arch/arm/mach-rockchip/spl.c
> @@ -56,7 +56,8 @@ u32 spl_boot_device(void)
>                 defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
>                 defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \
>                 defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY) || \
> -               defined(CONFIG_TARGET_CHROMEBOOK_BOB)
> +               defined(CONFIG_TARGET_CHROMEBOOK_BOB) || \
> +               defined(CONFIG_TARGET_CHROMEBOOK_KEVIN)
>         return BOOT_DEVICE_SPI;
>  #endif
>         if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
> diff --git a/board/google/gru/Kconfig b/board/google/gru/Kconfig
> index 61f7bbca989b..1455e1481dc2 100644
> --- a/board/google/gru/Kconfig
> +++ b/board/google/gru/Kconfig
> @@ -13,3 +13,19 @@ config BOARD_SPECIFIC_OPTIONS # dummy
>         def_bool y
>
>  endif
> +
> +if TARGET_CHROMEBOOK_KEVIN
> +
> +config SYS_BOARD
> +       default "gru"
> +
> +config SYS_VENDOR
> +       default "google"
> +
> +config SYS_CONFIG_NAME
> +       default "gru"
> +
> +config BOARD_SPECIFIC_OPTIONS # dummy
> +       def_bool y
> +
> +endif
> diff --git a/board/google/gru/MAINTAINERS b/board/google/gru/MAINTAINERS
> index e1cda756b8c8..53257c52a04b 100644
> --- a/board/google/gru/MAINTAINERS
> +++ b/board/google/gru/MAINTAINERS
> @@ -4,3 +4,11 @@ S:     Maintained
>  F:     board/google/gru/
>  F:     include/configs/gru.h
>  F:     configs/chromebook_bob_defconfig
> +
> +CHROMEBOOK KEVIN BOARD
> +M:     Simon Glass <sjg@chromium.org>
> +M:     Alper Nebi Yasak <alpernebiyasak@gmail.com>
> +S:     Maintained
> +F:     board/google/gru/
> +F:     include/configs/gru.h
> +F:     configs/chromebook_kevin_defconfig
> diff --git a/board/google/gru/gru.c b/board/google/gru/gru.c
> index cbf62a9427c9..fbcf845e87dd 100644
> --- a/board/google/gru/gru.c
> +++ b/board/google/gru/gru.c
> @@ -26,7 +26,7 @@ void gru_dummy_function(int i)
>
>  int board_early_init_f(void)
>  {
> -# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
> +# if defined(CONFIG_TARGET_CHROMEBOOK_BOB) || defined(CONFIG_TARGET_CHROMEBOOK_KEVIN)
>         int sum, i;
>
>         /*
> diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig
> new file mode 100644
> index 000000000000..831a6d3822b8
> --- /dev/null
> +++ b/configs/chromebook_kevin_defconfig
> @@ -0,0 +1,111 @@
> +CONFIG_ARM=y
> +CONFIG_SKIP_LOWLEVEL_INIT=y
> +CONFIG_ARCH_ROCKCHIP=y
> +CONFIG_SYS_TEXT_BASE=0x00200000
> +CONFIG_SPL_GPIO=y
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_ENV_OFFSET=0x3F8000
> +CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-kevin"
> +CONFIG_SPL_TEXT_BASE=0xff8c2000
> +CONFIG_ROCKCHIP_RK3399=y
> +CONFIG_ROCKCHIP_BOOT_MODE_REG=0
> +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
> +# CONFIG_SPL_MMC is not set
> +CONFIG_TARGET_CHROMEBOOK_KEVIN=y
> +CONFIG_DEBUG_UART_BASE=0xff1a0000
> +CONFIG_DEBUG_UART_CLOCK=24000000
> +CONFIG_SPL_SPI_FLASH_SUPPORT=y
> +CONFIG_SPL_SPI=y
> +CONFIG_DEBUG_UART=y
> +CONFIG_SYS_LOAD_ADDR=0x800800
> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-kevin.dtb"
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_DISPLAY_BOARDINFO_LATE=y
> +CONFIG_BOARD_EARLY_INIT_R=y
> +CONFIG_MISC_INIT_R=y
> +CONFIG_BLOBLIST=y
> +CONFIG_BLOBLIST_SIZE=0x1000
> +CONFIG_BLOBLIST_ADDR=0x100000
> +CONFIG_HANDOFF=y
> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> +CONFIG_SPL_STACK_R=y
> +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
> +CONFIG_SPL_SPI_LOAD=y
> +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
> +CONFIG_CMD_BOOTZ=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_GPT=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_SF_TEST=y
> +CONFIG_CMD_SPI=y
> +CONFIG_CMD_USB=y
> +# CONFIG_CMD_SETEXPR is not set
> +CONFIG_CMD_TIME=y
> +CONFIG_CMD_PMIC=y
> +CONFIG_CMD_REGULATOR=y
> +CONFIG_CMD_LOG=y
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_SPL_DM_SEQ_ALIAS=y
> +CONFIG_ROCKCHIP_GPIO=y
> +CONFIG_I2C_CROS_EC_TUNNEL=y
> +CONFIG_SYS_I2C_ROCKCHIP=y
> +CONFIG_I2C_MUX=y
> +CONFIG_CROS_EC_KEYB=y
> +CONFIG_MISC=y
> +CONFIG_ROCKCHIP_EFUSE=y
> +CONFIG_CROS_EC=y
> +CONFIG_CROS_EC_SPI=y
> +CONFIG_PWRSEQ=y
> +CONFIG_MMC_PWRSEQ=y
> +CONFIG_MMC_DW=y
> +CONFIG_MMC_DW_ROCKCHIP=y
> +CONFIG_MMC_SDHCI=y
> +CONFIG_MMC_SDHCI_ROCKCHIP=y
> +CONFIG_SF_DEFAULT_BUS=1
> +CONFIG_SF_DEFAULT_SPEED=20000000
> +CONFIG_SPI_FLASH_GIGADEVICE=y
> +CONFIG_SPI_FLASH_WINBOND=y
> +CONFIG_DM_ETH=y
> +CONFIG_ETH_DESIGNWARE=y
> +CONFIG_GMAC_ROCKCHIP=y
> +CONFIG_PHY_ROCKCHIP_INNO_USB2=y
> +CONFIG_PHY_ROCKCHIP_TYPEC=y
> +CONFIG_PMIC_RK8XX=y
> +CONFIG_REGULATOR_PWM=y
> +CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_REGULATOR_RK8XX=y
> +CONFIG_PWM_CROS_EC=y
> +CONFIG_PWM_ROCKCHIP=y
> +CONFIG_DM_RESET=y
> +CONFIG_DM_RNG=y
> +CONFIG_RNG_ROCKCHIP=y
> +CONFIG_DEBUG_UART_SHIFT=2
> +CONFIG_ROCKCHIP_SPI=y
> +CONFIG_SYSRESET=y
> +CONFIG_USB=y
> +CONFIG_USB_XHCI_HCD=y
> +CONFIG_USB_XHCI_DWC3=y
> +CONFIG_USB_EHCI_HCD=y
> +CONFIG_USB_EHCI_GENERIC=y
> +CONFIG_USB_OHCI_HCD=y
> +CONFIG_USB_OHCI_GENERIC=y
> +CONFIG_USB_DWC3=y
> +CONFIG_USB_KEYBOARD=y
> +CONFIG_USB_HOST_ETHER=y
> +CONFIG_USB_ETHER_ASIX=y
> +CONFIG_USB_ETHER_ASIX88179=y
> +CONFIG_USB_ETHER_MCS7830=y
> +CONFIG_USB_ETHER_RTL8152=y
> +CONFIG_USB_ETHER_SMSC95XX=y
> +CONFIG_DM_VIDEO=y
> +CONFIG_DISPLAY=y
> +CONFIG_VIDEO_ROCKCHIP=y
> +CONFIG_VIDEO_ROCKCHIP_MAX_XRES=2400
> +CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1600
> +CONFIG_DISPLAY_ROCKCHIP_EDP=y
> +CONFIG_CMD_DHRYSTONE=y
> +CONFIG_ERRNO_STR=y
> diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
> index 144cb98ef941..a75e60b9fa30 100644
> --- a/doc/board/rockchip/rockchip.rst
> +++ b/doc/board/rockchip/rockchip.rst
> @@ -66,6 +66,7 @@ List of mainline supported Rockchip boards:
>       - FriendlyElec NanoPi M4B (nanopi-m4b-rk3399)
>       - FriendlyARM NanoPi NEO4 (nanopi-neo4-rk3399)
>       - Google Bob (chromebook_bob)
> +     - Google Kevin (chromebook_kevin)
>       - Khadas Edge (khadas-edge-rk3399)
>       - Khadas Edge-Captain (khadas-edge-captain-rk3399)
>       - Khadas Edge-V (hadas-edge-v-rk3399)
> diff --git a/include/dt-bindings/input/linux-event-codes.h b/include/dt-bindings/input/linux-event-codes.h
> index 87cf351bab03..331458c0e710 100644
> --- a/include/dt-bindings/input/linux-event-codes.h
> +++ b/include/dt-bindings/input/linux-event-codes.h
> @@ -749,7 +749,8 @@
>  #define SW_ROTATE_LOCK         0x0c  /* set = rotate locked/disabled */
>  #define SW_LINEIN_INSERT       0x0d  /* set = inserted */
>  #define SW_MUTE_DEVICE         0x0e  /* set = device disabled */
> -#define SW_MAX                 0x0f
> +#define SW_PEN_INSERTED                0x0f  /* set = pen inserted */
> +#define SW_MAX                 0x10

This change is not related to the actual patch - remove it from here.

Jagan.

Re: [PATCH v3 1/4] rockchip: gru: Set up SoC IO domain registers

[Alper Nebi Yasak]

On 11/03/2022 22:49, Jagan Teki wrote:
> On Fri, Dec 24, 2021 at 7:14 PM Alper Nebi Yasak
> <alpernebiyasak@gmail.com> wrote:
>>
>> The RK3399 SoC needs to know the voltage value provided by some
>> regulators, which is done by setting relevant register bits. Configure
>> these the way other RK3399 boards do, but with the same values as are
>> set in the equivalent code in coreboot.
>>
>> Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
>> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
>> ---
>> There is a driver for this on Rockchip's repo, I managed to forward-port
>> it and get it working. If that's more desirable than doing it per-board
>> like this I can send that upstream (but I'd prefer to do it after this).
>>
>> [...]
> 
> This looks like a board hack code for me, which is difficult to
> maintain in the long run. Better go with UCLASS_POWER_DOMAIN, I
> believe it would be a straightforward implementation.

Yeah, it's a board hack that several other boards also do. I've got a
driver working for this as mentioned above, but that adds a new
UCLASS_IO_DOMAIN instead of using UCLASS_POWER_DOMAIN like you suggest.

I had been tired of carrying these patches, so wanted to get any working
version merged before attempting to upstream the driver and remove the
hacky parts from all boards at once. I'm not sure how long would that
take, and I didn't want this to be blocked by that.

I've got to work on binman things for a while, so I might not be able to
get to that and your other suggestions soon enough.

Re: [PATCH v3 3/4] rockchip: bob: Enable more configs

[Alper Nebi Yasak]

On 11/03/2022 23:01, Jagan Teki wrote:
> On Fri, Dec 24, 2021 at 7:14 PM Alper Nebi Yasak
> <alpernebiyasak@gmail.com> wrote:
>> The Bob board has two USB 3.0 Type-C ports and one USB 2.0 Type-A port
>> on its right side. Enable the configs relevant to USB devices so these
>> can be used.
>>
>> [...]
>> --- a/include/configs/gru.h
>> +++ b/include/configs/gru.h
>> @@ -13,4 +13,7 @@
>>
>>  #include <configs/rk3399_common.h>
>>
>> +#define CONFIG_USB_OHCI_NEW
>> +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS     2
> 
> Can you move them to Kconfig?

I'll try. Not much experience with the USB subsystem though, I may need
to do some reading if things aren't trivial.

Re: [PATCH v3 4/4] rockchip: rk3399: Add support for chromebook_kevin

[Alper Nebi Yasak]

On 11/03/2022 23:02, Jagan Teki wrote:
> On Fri, Dec 24, 2021 at 7:14 PM Alper Nebi Yasak
> <alpernebiyasak@gmail.com> wrote:
>> [...] The rk3399-gru-kevin devicetree
>> has an unknown event code reference which has to be defined, set it
>> to the Linux counterpart. 
>>
>> [...]
>> diff --git a/include/dt-bindings/input/linux-event-codes.h b/include/dt-bindings/input/linux-event-codes.h
>> index 87cf351bab03..331458c0e710 100644
>> --- a/include/dt-bindings/input/linux-event-codes.h
>> +++ b/include/dt-bindings/input/linux-event-codes.h
>> @@ -749,7 +749,8 @@
>>  #define SW_ROTATE_LOCK         0x0c  /* set = rotate locked/disabled */
>>  #define SW_LINEIN_INSERT       0x0d  /* set = inserted */
>>  #define SW_MUTE_DEVICE         0x0e  /* set = device disabled */
>> -#define SW_MAX                 0x0f
>> +#define SW_PEN_INSERTED                0x0f  /* set = pen inserted */
>> +#define SW_MAX                 0x10
> 
> This change is not related to the actual patch - remove it from here.

The definition's necessary to build rk3399-gru-kevin.dtb. But yes, it'd
be better to sync linux-event-codes.h from Linux in a separate patch.

Re: [PATCH v3 3/4] rockchip: bob: Enable more configs

[Simon Glass]

Hi,

On Mon, 14 Mar 2022 at 15:32, Alper Nebi Yasak <alpernebiyasak@gmail.com> wrote:
>
> On 11/03/2022 23:01, Jagan Teki wrote:
> > On Fri, Dec 24, 2021 at 7:14 PM Alper Nebi Yasak
> > <alpernebiyasak@gmail.com> wrote:
> >> The Bob board has two USB 3.0 Type-C ports and one USB 2.0 Type-A port
> >> on its right side. Enable the configs relevant to USB devices so these
> >> can be used.
> >>
> >> [...]
> >> --- a/include/configs/gru.h
> >> +++ b/include/configs/gru.h
> >> @@ -13,4 +13,7 @@
> >>
> >>  #include <configs/rk3399_common.h>
> >>
> >> +#define CONFIG_USB_OHCI_NEW
> >> +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS     2
> >
> > Can you move them to Kconfig?
>
> I'll try. Not much experience with the USB subsystem though, I may need
> to do some reading if things aren't trivial.

That should not block this patch, though.

Regards,
Simon

Re: [PATCH v3 1/4] rockchip: gru: Set up SoC IO domain registers

[Simon Glass]

Hi,

On Mon, 14 Mar 2022 at 15:32, Alper Nebi Yasak <alpernebiyasak@gmail.com> wrote:
>
> On 11/03/2022 22:49, Jagan Teki wrote:
> > On Fri, Dec 24, 2021 at 7:14 PM Alper Nebi Yasak
> > <alpernebiyasak@gmail.com> wrote:
> >>
> >> The RK3399 SoC needs to know the voltage value provided by some
> >> regulators, which is done by setting relevant register bits. Configure
> >> these the way other RK3399 boards do, but with the same values as are
> >> set in the equivalent code in coreboot.
> >>
> >> Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
> >> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
> >> ---
> >> There is a driver for this on Rockchip's repo, I managed to forward-port
> >> it and get it working. If that's more desirable than doing it per-board
> >> like this I can send that upstream (but I'd prefer to do it after this).
> >>
> >> [...]
> >
> > This looks like a board hack code for me, which is difficult to
> > maintain in the long run. Better go with UCLASS_POWER_DOMAIN, I
> > believe it would be a straightforward implementation.
>
> Yeah, it's a board hack that several other boards also do. I've got a
> driver working for this as mentioned above, but that adds a new
> UCLASS_IO_DOMAIN instead of using UCLASS_POWER_DOMAIN like you suggest.
>
> I had been tired of carrying these patches, so wanted to get any working
> version merged before attempting to upstream the driver and remove the
> hacky parts from all boards at once. I'm not sure how long would that
> take, and I didn't want this to be blocked by that.

+1 let's get this merged as I have been waiting two releases for this
now. I can't really test anything since the base hardware is not
functional on mainline.

>
> I've got to work on binman things for a while, so I might not be able to
> get to that and your other suggestions soon enough.

Regards,
Simon