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Mon, 15 May 2023 08:32:19 +0000 (GMT) Message-ID: <67fcac44-675b-67b3-ba7b-61730c356f50@linux.ibm.com> Date: Mon, 15 May 2023 14:02:17 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH 6/6] target/ppc: Implement HEIR SPR To: Nicholas Piggin Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org References: <20230323022237.1807512-1-npiggin@gmail.com> <20230323022237.1807512-6-npiggin@gmail.com> Content-Language: en-US From: Harsh Prateek Bora In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: s5yp-JZeBFj9pM8bjpiZUZ-J9wFVbIDH X-Proofpoint-GUID: MLFUOG9JmD7uV2iJLhnMn4sa47_XP_Rf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-15_06,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 mlxscore=0 suspectscore=0 mlxlogscore=878 malwarescore=0 priorityscore=1501 impostorscore=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305150073 Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.93, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 5/15/23 13:56, Nicholas Piggin wrote: > On Tue May 9, 2023 at 7:51 PM AEST, Harsh Prateek Bora wrote: >> On Thu, Mar 23, 2023 at 12:22:37PM +1000, Nicholas Piggin wrote: >>> The hypervisor emulation assistance interrupt modifies HEIR to >>> contain the value of the instruction which caused the exception. >>> >>> Signed-off-by: Nicholas Piggin >>> --- >>> target/ppc/cpu.h | 1 + >>> target/ppc/cpu_init.c | 23 +++++++++++++++++++++++ >>> target/ppc/excp_helper.c | 12 +++++++++++- >>> 3 files changed, 35 insertions(+), 1 deletion(-) >>> >> >> >> >>> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c >>> index 2e0321ab69..d206903562 100644 >>> --- a/target/ppc/excp_helper.c >>> +++ b/target/ppc/excp_helper.c >>> @@ -1614,13 +1614,23 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp) >>> case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ >>> case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ >>> case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */ >>> - case POWERPC_EXCP_HV_EMU: >>> case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */ >>> srr0 = SPR_HSRR0; >>> srr1 = SPR_HSRR1; >>> new_msr |= (target_ulong)MSR_HVB; >>> new_msr |= env->msr & ((target_ulong)1 << MSR_RI); >>> break; >>> + case POWERPC_EXCP_HV_EMU: >>> + env->spr[SPR_HEIR] = insn; >>> + if (is_prefix_excp(env, insn)) { >>> + uint32_t insn2 = ppc_ldl_code(env, env->nip + 4); >>> + env->spr[SPR_HEIR] |= (uint64_t)insn2 << 32; >>> + } >>> + srr0 = SPR_HSRR0; >>> + srr1 = SPR_HSRR1; >>> + new_msr |= (target_ulong)MSR_HVB; >>> + new_msr |= env->msr & ((target_ulong)1 << MSR_RI); >>> + break; >> >> Since there is a common code, this could be better written like: >> case POWERPC_EXCP_HV_EMU: >> env->spr[SPR_HEIR] = insn; >> if (is_prefix_excp(env, insn)) { >> uint32_t insn2 = ppc_ldl_code(env, env->nip + 4); >> env->spr[SPR_HEIR] |= (uint64_t)insn2 << 32; >> } >> /* fall through below common code for EXCP_HVIRT */ >> case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */ >> srr0 = SPR_HSRR0; >> srr1 = SPR_HSRR1; >> new_msr |= (target_ulong)MSR_HVB; >> new_msr |= env->msr & ((target_ulong)1 << MSR_RI); >> break; > > That would be wrong for the other HSRR fallthroughs above it. > Oh yeh, in that case, may be move it to top of the EXCP_HISI, it would need duplicating one line of assignment though (relatively better?). regards, Harsh > Thanks, > Nick >