From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dr. Philipp Tomsich Date: Wed, 13 Sep 2017 22:44:18 +0200 Subject: [U-Boot] [U-Boot, 6/8] clk: rockchip: Add rk3368 Saradc clock support In-Reply-To: References: <1505302336-74720-1-git-send-email-david.wu@rock-chips.com> Message-ID: <6878D2E3-EEE2-492D-91FF-24F2F2DEB504@theobroma-systems.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: quoted-printable To: u-boot@lists.denx.de > On 13 Sep 2017, at 22:41, Philipp Tomsich wrote: >=20 >=20 >=20 > On Wed, 13 Sep 2017, David Wu wrote: >=20 >> The clk_saradc is dividing from the 24M, clk_saradc=3D24MHz/(saradc_div_= con+1). >> Saradc integer divider control register is 8-bits width. >>=20 >> Signed-off-by: David Wu > >=20 > Reviewed-by: Philipp Tomsich > >=20 > See below for comments. >=20 >> --- >> arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 5 ++++ >> drivers/clk/rockchip/clk_rk3368.c | 32 +++++++++++++++++++= ++++++ >> 2 files changed, 37 insertions(+) >>=20 >> diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/= include/asm/arch-rockchip/cru_rk3368.h >> index 2b1197f..31f7685 100644 >> --- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h >> +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h >> @@ -89,6 +89,11 @@ enum { >> MCU_CLK_DIV_SHIFT =3D 0, >> MCU_CLK_DIV_MASK =3D GENMASK(4, 0), >>=20 >> + /* CLKSEL_CON25 */ >> + CLK_SARADC_DIV_CON_SHIFT =3D 8, >> + CLK_SARADC_DIV_CON_MASK =3D 0xff << CLK_SARADC_DIV_CON_SHIFT, >=20 > Please use GENMASK. >=20 >> + CLK_SARADC_DIV_CON_WIDTH =3D 8, >> + >> /* CLKSEL43_CON */ >> GMAC_MUX_SEL_EXTCLK =3D BIT(8), >>=20 >> diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/cl= k_rk3368.c >> index 2be1f57..2eedf77 100644 >> --- a/drivers/clk/rockchip/clk_rk3368.c >> +++ b/drivers/clk/rockchip/clk_rk3368.c >> @@ -12,6 +12,7 @@ >> #include >> #include >> #include >> +#include >> #include >> #include >> #include >> @@ -397,6 +398,31 @@ static ulong rk3368_spi_set_clk(struct rk3368_cru *= cru, ulong clk_id, uint hz) >> return rk3368_spi_get_clk(cru, clk_id); >> } >>=20 >> +static ulong rk3368_saradc_get_clk(struct rk3368_cru *cru) >> +{ >> + u32 div, val; >> + >> + val =3D readl(&cru->clksel_con[25]); >> + div =3D bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, >> + CLK_SARADC_DIV_CON_WIDTH); >=20 > Please reuse the functions from bitfield.h. It=E2=80=99s apparently too late to do code reviews: please ignore this com= ment. >=20 >> + >> + return DIV_TO_RATE(OSC_HZ, div); >> +} >> + >> +static ulong rk3368_saradc_set_clk(struct rk3368_cru *cru, uint hz) >> +{ >> + int src_clk_div; >> + >> + src_clk_div =3D DIV_ROUND_UP(OSC_HZ, hz) - 1; >> + assert(src_clk_div < 128); >> + >> + rk_clrsetreg(&cru->clksel_con[25], >> + CLK_SARADC_DIV_CON_MASK, >> + src_clk_div << CLK_SARADC_DIV_CON_SHIFT); >> + >> + return rk3368_saradc_get_clk(cru); >> +} >> + >> static ulong rk3368_clk_get_rate(struct clk *clk) >> { >> struct rk3368_clk_priv *priv =3D dev_get_priv(clk->dev); >> @@ -419,6 +445,9 @@ static ulong rk3368_clk_get_rate(struct clk *clk) >> rate =3D rk3368_mmc_get_clk(priv->cru, clk->id); >> break; >> #endif >> + case SCLK_SARADC: >> + rate =3D rk3368_saradc_get_clk(priv->cru); >> + break; >> default: >> return -ENOENT; >> } >> @@ -453,6 +482,9 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ul= ong rate) >> ret =3D rk3368_gmac_set_clk(priv->cru, clk->id, rate); >> break; >> #endif >> + case SCLK_SARADC: >> + ret =3D rk3368_saradc_set_clk(priv->cru, rate); >> + break; >> default: >> return -ENOENT; >> }