From: Richard Henderson <richard.henderson@linaro.org>
To: Chris Howard <cvz185@web.de>, qemu-devel@nongnu.org
Subject: Re: Possible bug when setting aarch64 watchpoints
Date: Tue, 26 Apr 2022 22:14:04 -0700 [thread overview]
Message-ID: <68e1b1dc-f396-7b2f-8aac-b01138116d43@linaro.org> (raw)
In-Reply-To: <DF7731C2-424F-4438-BD46-A09CAAE21835@web.de>
On 4/24/22 04:40, Chris Howard wrote:
> Hi, I’m new to qemu (and even bug-reporting) so apologies in advance…
>
> The MASK field in DBGWCRx_EL1 is **5** bits wide [28:24].
>
> In target/arm/kvm64.c I found the line:
>
> wp.wcr = deposit32(wp.wcr, 24, 4, bits); // ie **4** bits instead of **5**
>
>
> If it’s not copying (or calculating?) the number of bits correctly this would explain the behaviour I’m seeing:
>
> If I set
>
> DBGWVR0_EL1 = 0x00800000
>
> and
>
> DBGWCR0_EL1 = 0x1F<<24 | 0xFF<<5 | 0b11<<3 | 0b11<<1 | 0b1<<0
>
> and then access memory [0x00807FFF] I get a watchpoint exception. (ie. watchpoints ARE working/enabled)
>
> But if I access [0x008080000] I *don’t* get an exception.
>
> **If the MASK field gets set to 0b1111 instead of 0b11111 then only the bottom 15 bits of the address get masked (instead of 31) and the masked address isn’t 0x00800000, and the exception won’t be triggered.**
>
>
> Unfortunately, changing the 4 to a 5 and recompiling had no effect :-(
>
> I may well have misunderstood something. :-/
You're not. It's a typo, repeated twice. Will fix.
r~
prev parent reply other threads:[~2022-04-27 5:14 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-24 11:40 Possible bug when setting aarch64 watchpoints Chris Howard
2022-04-24 12:27 ` Chris Howard
2022-04-27 5:14 ` Richard Henderson [this message]
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