From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26A85C47094 for ; Thu, 10 Jun 2021 15:39:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 07148613C9 for ; Thu, 10 Jun 2021 15:39:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231690AbhFJPlH (ORCPT ); Thu, 10 Jun 2021 11:41:07 -0400 Received: from foss.arm.com ([217.140.110.172]:34812 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231658AbhFJPk6 (ORCPT ); Thu, 10 Jun 2021 11:40:58 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9B7BF106F; Thu, 10 Jun 2021 08:39:01 -0700 (PDT) Received: from [10.57.74.218] (unknown [10.57.74.218]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0C4FB3F719; Thu, 10 Jun 2021 08:38:58 -0700 (PDT) Subject: Re: [PATCH v1 2/3] coresight: tmc-etr: Use perf_output_handle::head for AUX ring buffer To: Leo Yan , Arnaldo Carvalho de Melo , Mathieu Poirier , Mike Leach , Alexander Shishkin , John Garry , Will Deacon , Peter Zijlstra , Ingo Molnar , Jiri Olsa , Namhyung Kim , Daniel Kiss , Denis Nikitin , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org References: <20210528161552.654907-1-leo.yan@linaro.org> <20210528161552.654907-3-leo.yan@linaro.org> From: Suzuki K Poulose Message-ID: <68f0fb5e-6f91-66c3-855a-9473bee7de15@arm.com> Date: Thu, 10 Jun 2021 16:38:57 +0100 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210528161552.654907-3-leo.yan@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Leo On 28/05/2021 17:15, Leo Yan wrote: > When enable the Arm CoreSight PMU event, the context for AUX ring buffer > is prepared in the structure perf_output_handle, and its field "head" > points the head of the AUX ring buffer and it is updated after filling > AUX trace data into buffer. > > Current code uses an extra field etr_perf_buffer::head to maintain the > header for the AUX ring buffer, thus it's not necessary and it's better > to directly perf_output_handle::head. > > This patch removes the header etr_perf_buffer::head and directly used > perf_output_handle::head as the header for AUX ring buffer. > > Signed-off-by: Leo Yan > --- > drivers/hwtracing/coresight/coresight-tmc-etr.c | 10 +++------- > 1 file changed, 3 insertions(+), 7 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c > index acdb59e0e661..b22823d67680 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c > @@ -32,7 +32,6 @@ struct etr_flat_buf { > * @etr_buf - Actual buffer used by the ETR > * @pid - The PID this etr_perf_buffer belongs to. > * @snaphost - Perf session mode > - * @head - handle->head at the beginning of the session. > * @nr_pages - Number of pages in the ring buffer. > * @pages - Array of Pages in the ring buffer. > */ > @@ -41,7 +40,6 @@ struct etr_perf_buffer { > struct etr_buf *etr_buf; > pid_t pid; > bool snapshot; > - unsigned long head; > int nr_pages; > void **pages; > }; > @@ -1437,16 +1435,16 @@ static void tmc_free_etr_buffer(void *config) > * buffer to the perf ring buffer. > */ > static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf, > + unsigned long head, > unsigned long src_offset, > unsigned long to_copy) > { > long bytes; > long pg_idx, pg_offset; > - unsigned long head = etr_perf->head; > char **dst_pages, *src_buf; > struct etr_buf *etr_buf = etr_perf->etr_buf; > > - head = etr_perf->head; > + head = PERF_IDX2OFF(head, etr_perf); > pg_idx = head >> PAGE_SHIFT; > pg_offset = head & (PAGE_SIZE - 1); > dst_pages = (char **)etr_perf->pages; > @@ -1553,7 +1551,7 @@ tmc_update_etr_buffer(struct coresight_device *csdev, > /* Insert barrier packets at the beginning, if there was an overflow */ > if (lost) > tmc_etr_buf_insert_barrier_packet(etr_buf, offset); > - tmc_etr_sync_perf_buffer(etr_perf, offset, size); > + tmc_etr_sync_perf_buffer(etr_perf, handle->head, offset, size); > > /* > * In snapshot mode we simply increment the head by the number of byte > @@ -1605,8 +1603,6 @@ static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, void *data) > goto unlock_out; > } > > - etr_perf->head = PERF_IDX2OFF(handle->head, etr_perf); > - > /* > * No HW configuration is needed if the sink is already in > * use for this session. > This looks good to me and could avoid any potential issues with stale offset cached in the etr_perf_buffer. Reviewed-by: Suzuki K Poulose From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A0CFC47094 for ; Thu, 10 Jun 2021 15:40:45 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E55C8613D9 for ; Thu, 10 Jun 2021 15:40:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E55C8613D9 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Cc:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=pdV4U7SGPuSHIM2ieSlllG7YucNwjvKLWFB3bPZCwOM=; b=MLV3754XlofGd+ouwBzA04VjpK RQ3k1PqMvDSfsf3AfXpxClTVWKAmWJbtRph5qFjBgoT8eRMK9e8LDXQhuO0NrcnJ9zkdxe34glWGs 64HlSOPKO9oyo6h+atb2ZznyBGyLz22KW0WiMcyMIRu1XKaOYAKPAYSLfp15Yl6B4UBm81fF5Syqo tt7P/R3Iwfgdh4xkfFasGlkxb7fyTsJny/An2Q6zceuGlqIV6XBF7Ugl078z400C8MGNkEy5IsVcz 9wNBd4ZV9+LC2shbK+CcX99gX7BOevb8tb8ChMLY81k4jYinNiif1GJVPLjuj8a/QP9HfEGfK9Cgi q4Y9vnUg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lrMlx-001OEg-Dk; Thu, 10 Jun 2021 15:39:09 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lrMlt-001ODf-O6 for linux-arm-kernel@lists.infradead.org; Thu, 10 Jun 2021 15:39:07 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9B7BF106F; Thu, 10 Jun 2021 08:39:01 -0700 (PDT) Received: from [10.57.74.218] (unknown [10.57.74.218]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0C4FB3F719; Thu, 10 Jun 2021 08:38:58 -0700 (PDT) Subject: Re: [PATCH v1 2/3] coresight: tmc-etr: Use perf_output_handle::head for AUX ring buffer To: Leo Yan , Arnaldo Carvalho de Melo , Mathieu Poirier , Mike Leach , Alexander Shishkin , John Garry , Will Deacon , Peter Zijlstra , Ingo Molnar , Jiri Olsa , Namhyung Kim , Daniel Kiss , Denis Nikitin , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org References: <20210528161552.654907-1-leo.yan@linaro.org> <20210528161552.654907-3-leo.yan@linaro.org> From: Suzuki K Poulose Message-ID: <68f0fb5e-6f91-66c3-855a-9473bee7de15@arm.com> Date: Thu, 10 Jun 2021 16:38:57 +0100 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210528161552.654907-3-leo.yan@linaro.org> Content-Language: en-GB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210610_083905_920237_D56A4575 X-CRM114-Status: GOOD ( 28.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Leo On 28/05/2021 17:15, Leo Yan wrote: > When enable the Arm CoreSight PMU event, the context for AUX ring buffer > is prepared in the structure perf_output_handle, and its field "head" > points the head of the AUX ring buffer and it is updated after filling > AUX trace data into buffer. > > Current code uses an extra field etr_perf_buffer::head to maintain the > header for the AUX ring buffer, thus it's not necessary and it's better > to directly perf_output_handle::head. > > This patch removes the header etr_perf_buffer::head and directly used > perf_output_handle::head as the header for AUX ring buffer. > > Signed-off-by: Leo Yan > --- > drivers/hwtracing/coresight/coresight-tmc-etr.c | 10 +++------- > 1 file changed, 3 insertions(+), 7 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c > index acdb59e0e661..b22823d67680 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c > @@ -32,7 +32,6 @@ struct etr_flat_buf { > * @etr_buf - Actual buffer used by the ETR > * @pid - The PID this etr_perf_buffer belongs to. > * @snaphost - Perf session mode > - * @head - handle->head at the beginning of the session. > * @nr_pages - Number of pages in the ring buffer. > * @pages - Array of Pages in the ring buffer. > */ > @@ -41,7 +40,6 @@ struct etr_perf_buffer { > struct etr_buf *etr_buf; > pid_t pid; > bool snapshot; > - unsigned long head; > int nr_pages; > void **pages; > }; > @@ -1437,16 +1435,16 @@ static void tmc_free_etr_buffer(void *config) > * buffer to the perf ring buffer. > */ > static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf, > + unsigned long head, > unsigned long src_offset, > unsigned long to_copy) > { > long bytes; > long pg_idx, pg_offset; > - unsigned long head = etr_perf->head; > char **dst_pages, *src_buf; > struct etr_buf *etr_buf = etr_perf->etr_buf; > > - head = etr_perf->head; > + head = PERF_IDX2OFF(head, etr_perf); > pg_idx = head >> PAGE_SHIFT; > pg_offset = head & (PAGE_SIZE - 1); > dst_pages = (char **)etr_perf->pages; > @@ -1553,7 +1551,7 @@ tmc_update_etr_buffer(struct coresight_device *csdev, > /* Insert barrier packets at the beginning, if there was an overflow */ > if (lost) > tmc_etr_buf_insert_barrier_packet(etr_buf, offset); > - tmc_etr_sync_perf_buffer(etr_perf, offset, size); > + tmc_etr_sync_perf_buffer(etr_perf, handle->head, offset, size); > > /* > * In snapshot mode we simply increment the head by the number of byte > @@ -1605,8 +1603,6 @@ static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, void *data) > goto unlock_out; > } > > - etr_perf->head = PERF_IDX2OFF(handle->head, etr_perf); > - > /* > * No HW configuration is needed if the sink is already in > * use for this session. > This looks good to me and could avoid any potential issues with stale offset cached in the etr_perf_buffer. Reviewed-by: Suzuki K Poulose _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel