From mboxrd@z Thu Jan 1 00:00:00 1970 From: Joao Pinto Subject: Re: [PATCH 02/37] PCI: dwc: designware: Add new *ops* for cpu addr fixup Date: Fri, 13 Jan 2017 16:34:26 +0000 Message-ID: <68f59de0-104f-41aa-886d-52d43ecd8e6b@synopsys.com> References: <1484216786-17292-1-git-send-email-kishon@ti.com> <1484216786-17292-3-git-send-email-kishon@ti.com> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: <1484216786-17292-3-git-send-email-kishon@ti.com> Sender: linux-doc-owner@vger.kernel.org To: Kishon Vijay Abraham I , Bjorn Helgaas , Jingoo Han , Joao Pinto , Arnd Bergmann Cc: linux-pci@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@axis.com, linux-arm-msm@vger.kernel.org, nsekhar@ti.com List-Id: linux-arm-msm@vger.kernel.org Hi Kishon, Ās 10:25 AM de 1/12/2017, Kishon Vijay Abraham I escreveu: > Some platforms (like dra7xx) require only the least 28 bits of the > corresponding 32 bit CPU address to be programmed in the address > translation unit. This modified address is stored in io_base/mem_base/ > cfg0_base/cfg1_base in dra7xx_pcie_host_init. While this is okay for > host mode where the address range is fixed, device mode requires > different addresses to be programmed based on the host buffer address. > Add a new ops to get the least 28 bits of the corresponding 32 bit > CPU address and invoke it before programming the address translation > unit. > > Signed-off-by: Kishon Vijay Abraham I > --- > drivers/pci/dwc/pcie-designware.c | 3 +++ > drivers/pci/dwc/pcie-designware.h | 1 + > 2 files changed, 4 insertions(+) > > diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c > index bed1999..d68bc7b 100644 > --- a/drivers/pci/dwc/pcie-designware.c > +++ b/drivers/pci/dwc/pcie-designware.c > @@ -195,6 +195,9 @@ static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index, > { > u32 retries, val; > > + if (pp->ops->cpu_addr_fixup) > + cpu_addr = pp->ops->cpu_addr_fixup(cpu_addr); > + > if (pp->iatu_unroll_enabled) { > dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_LOWER_BASE, > lower_32_bits(cpu_addr)); > diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h > index a567ea2..32f4602 100644 > --- a/drivers/pci/dwc/pcie-designware.h > +++ b/drivers/pci/dwc/pcie-designware.h > @@ -54,6 +54,7 @@ struct pcie_port { > }; > > struct pcie_host_ops { > + u64 (*cpu_addr_fixup)(u64 cpu_addr); > u32 (*readl_rc)(struct pcie_port *pp, u32 reg); > void (*writel_rc)(struct pcie_port *pp, u32 reg, u32 val); > int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val); > I think this is an acceptable fixup, I am ok with it. Reviewed-By: Joao Pinto Joao From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752132AbdAMQgF (ORCPT ); Fri, 13 Jan 2017 11:36:05 -0500 Received: from us01smtprelay-2.synopsys.com ([198.182.47.9]:50104 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750919AbdAMQgB (ORCPT ); Fri, 13 Jan 2017 11:36:01 -0500 Subject: Re: [PATCH 02/37] PCI: dwc: designware: Add new *ops* for cpu addr fixup To: Kishon Vijay Abraham I , Bjorn Helgaas , Jingoo Han , Joao Pinto , Arnd Bergmann References: <1484216786-17292-1-git-send-email-kishon@ti.com> <1484216786-17292-3-git-send-email-kishon@ti.com> CC: , , , , , , , , , , From: Joao Pinto Message-ID: <68f59de0-104f-41aa-886d-52d43ecd8e6b@synopsys.com> Date: Fri, 13 Jan 2017 16:34:26 +0000 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.6.0 MIME-Version: 1.0 In-Reply-To: <1484216786-17292-3-git-send-email-kishon@ti.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.107.19.116] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Kishon, Ās 10:25 AM de 1/12/2017, Kishon Vijay Abraham I escreveu: > Some platforms (like dra7xx) require only the least 28 bits of the > corresponding 32 bit CPU address to be programmed in the address > translation unit. This modified address is stored in io_base/mem_base/ > cfg0_base/cfg1_base in dra7xx_pcie_host_init. While this is okay for > host mode where the address range is fixed, device mode requires > different addresses to be programmed based on the host buffer address. > Add a new ops to get the least 28 bits of the corresponding 32 bit > CPU address and invoke it before programming the address translation > unit. > > Signed-off-by: Kishon Vijay Abraham I > --- > drivers/pci/dwc/pcie-designware.c | 3 +++ > drivers/pci/dwc/pcie-designware.h | 1 + > 2 files changed, 4 insertions(+) > > diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c > index bed1999..d68bc7b 100644 > --- a/drivers/pci/dwc/pcie-designware.c > +++ b/drivers/pci/dwc/pcie-designware.c > @@ -195,6 +195,9 @@ static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index, > { > u32 retries, val; > > + if (pp->ops->cpu_addr_fixup) > + cpu_addr = pp->ops->cpu_addr_fixup(cpu_addr); > + > if (pp->iatu_unroll_enabled) { > dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_LOWER_BASE, > lower_32_bits(cpu_addr)); > diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h > index a567ea2..32f4602 100644 > --- a/drivers/pci/dwc/pcie-designware.h > +++ b/drivers/pci/dwc/pcie-designware.h > @@ -54,6 +54,7 @@ struct pcie_port { > }; > > struct pcie_host_ops { > + u64 (*cpu_addr_fixup)(u64 cpu_addr); > u32 (*readl_rc)(struct pcie_port *pp, u32 reg); > void (*writel_rc)(struct pcie_port *pp, u32 reg, u32 val); > int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val); > I think this is an acceptable fixup, I am ok with it. Reviewed-By: Joao Pinto Joao From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Return-Path: Subject: Re: [PATCH 02/37] PCI: dwc: designware: Add new *ops* for cpu addr fixup To: Kishon Vijay Abraham I , Bjorn Helgaas , Jingoo Han , Joao Pinto , Arnd Bergmann References: <1484216786-17292-1-git-send-email-kishon@ti.com> <1484216786-17292-3-git-send-email-kishon@ti.com> From: Joao Pinto Message-ID: <68f59de0-104f-41aa-886d-52d43ecd8e6b@synopsys.com> Date: Fri, 13 Jan 2017 16:34:26 +0000 MIME-Version: 1.0 In-Reply-To: <1484216786-17292-3-git-send-email-kishon@ti.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-doc@vger.kernel.org, linux-pci@vger.kernel.org, nsekhar@ti.com, linux-kernel@vger.kernel.org, linux-arm-kernel@axis.com, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="windows-1252" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+bjorn=helgaas.com@lists.infradead.org List-ID: Hi Kishon, =C0s 10:25 AM de 1/12/2017, Kishon Vijay Abraham I escreveu: > Some platforms (like dra7xx) require only the least 28 bits of the > corresponding 32 bit CPU address to be programmed in the address > translation unit. This modified address is stored in io_base/mem_base/ > cfg0_base/cfg1_base in dra7xx_pcie_host_init. While this is okay for > host mode where the address range is fixed, device mode requires > different addresses to be programmed based on the host buffer address. > Add a new ops to get the least 28 bits of the corresponding 32 bit > CPU address and invoke it before programming the address translation > unit. > = > Signed-off-by: Kishon Vijay Abraham I > --- > drivers/pci/dwc/pcie-designware.c | 3 +++ > drivers/pci/dwc/pcie-designware.h | 1 + > 2 files changed, 4 insertions(+) > = > diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-des= ignware.c > index bed1999..d68bc7b 100644 > --- a/drivers/pci/dwc/pcie-designware.c > +++ b/drivers/pci/dwc/pcie-designware.c > @@ -195,6 +195,9 @@ static void dw_pcie_prog_outbound_atu(struct pcie_por= t *pp, int index, > { > u32 retries, val; > = > + if (pp->ops->cpu_addr_fixup) > + cpu_addr =3D pp->ops->cpu_addr_fixup(cpu_addr); > + > if (pp->iatu_unroll_enabled) { > dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_LOWER_BASE, > lower_32_bits(cpu_addr)); > diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-des= ignware.h > index a567ea2..32f4602 100644 > --- a/drivers/pci/dwc/pcie-designware.h > +++ b/drivers/pci/dwc/pcie-designware.h > @@ -54,6 +54,7 @@ struct pcie_port { > }; > = > struct pcie_host_ops { > + u64 (*cpu_addr_fixup)(u64 cpu_addr); > u32 (*readl_rc)(struct pcie_port *pp, u32 reg); > void (*writel_rc)(struct pcie_port *pp, u32 reg, u32 val); > int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val); > = I think this is an acceptable fixup, I am ok with it. Reviewed-By: Joao Pinto Joao _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 From: Joao.Pinto@synopsys.com (Joao Pinto) Date: Fri, 13 Jan 2017 16:34:26 +0000 Subject: [PATCH 02/37] PCI: dwc: designware: Add new *ops* for cpu addr fixup In-Reply-To: <1484216786-17292-3-git-send-email-kishon@ti.com> References: <1484216786-17292-1-git-send-email-kishon@ti.com> <1484216786-17292-3-git-send-email-kishon@ti.com> Message-ID: <68f59de0-104f-41aa-886d-52d43ecd8e6b@synopsys.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Kishon, ?s 10:25 AM de 1/12/2017, Kishon Vijay Abraham I escreveu: > Some platforms (like dra7xx) require only the least 28 bits of the > corresponding 32 bit CPU address to be programmed in the address > translation unit. This modified address is stored in io_base/mem_base/ > cfg0_base/cfg1_base in dra7xx_pcie_host_init. While this is okay for > host mode where the address range is fixed, device mode requires > different addresses to be programmed based on the host buffer address. > Add a new ops to get the least 28 bits of the corresponding 32 bit > CPU address and invoke it before programming the address translation > unit. > > Signed-off-by: Kishon Vijay Abraham I > --- > drivers/pci/dwc/pcie-designware.c | 3 +++ > drivers/pci/dwc/pcie-designware.h | 1 + > 2 files changed, 4 insertions(+) > > diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c > index bed1999..d68bc7b 100644 > --- a/drivers/pci/dwc/pcie-designware.c > +++ b/drivers/pci/dwc/pcie-designware.c > @@ -195,6 +195,9 @@ static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index, > { > u32 retries, val; > > + if (pp->ops->cpu_addr_fixup) > + cpu_addr = pp->ops->cpu_addr_fixup(cpu_addr); > + > if (pp->iatu_unroll_enabled) { > dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_LOWER_BASE, > lower_32_bits(cpu_addr)); > diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h > index a567ea2..32f4602 100644 > --- a/drivers/pci/dwc/pcie-designware.h > +++ b/drivers/pci/dwc/pcie-designware.h > @@ -54,6 +54,7 @@ struct pcie_port { > }; > > struct pcie_host_ops { > + u64 (*cpu_addr_fixup)(u64 cpu_addr); > u32 (*readl_rc)(struct pcie_port *pp, u32 reg); > void (*writel_rc)(struct pcie_port *pp, u32 reg, u32 val); > int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val); > I think this is an acceptable fixup, I am ok with it. Reviewed-By: Joao Pinto Joao