[Qemu-devel] [RFC PATCH 02/34] tcg+qom: QOMify core CPU defintions

[Peter Crosthwaite <crosthwaitepeter@gmail.com>]

These definitions are defined per-target and globall linked/defined
between core code and target-foo. QOMify them. Provide weakly linked
conditional default implementations for the non-qomified global fns.
This means converted architectures which install a QOM hook do not need
to define a function for the old globals even the common code expects
to link against something.

The top level definition of some functions is still left up to the
individual target cpu.h files, making the QOMified code paths opt-in
per target.

Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
---
 include/qom/cpu.h  | 24 ++++++++++++++++++++++++
 qom/cpu.c          |  6 ++++++
 softmmu_template.h |  6 ++++++
 translate-all.c    | 47 ++++++++++++++++++++++++++++++++++++++++++++---
 4 files changed, 80 insertions(+), 3 deletions(-)

diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 363c928..2cb89ab 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -119,6 +119,7 @@ struct TranslationBlock;
  * @cpu_exec_exit: Callback for cpu_exec cleanup.
  * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec.
  * @disas_set_info: Setup architecture specific components of disassembly info
+ * @cpu_mmu_index: Get MMU index for normal load stores
  *
  * Represents a CPU family or model.
  */
@@ -176,6 +177,17 @@ typedef struct CPUClass {
     bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
 
     void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
+    int (*cpu_mmu_index)(CPUState *cpu);
+    void (*cpu_get_tb_cpu_state)(CPUState *cpu,
+                                 void *pc, /* target_long * */
+                                 void *cs_base, /* target_long */
+                                 int *flags);
+    void (*gen_intermediate_code)(void *env, struct TranslationBlock *tb);
+    void (*gen_intermediate_code_pc)(void *env, struct TranslationBlock *tb);
+    void (*restore_state_to_opc)(void *env, struct TranslationBlock *tb,
+                                 int pc_pos);
+    void (*tlb_fill)(CPUState *cs, uint64_t addr, int is_write, int mmu_idx,
+                     uintptr_t retaddr);
 } CPUClass;
 
 #ifdef HOST_WORDS_BIGENDIAN
@@ -319,6 +331,18 @@ struct CPUState {
        (absolute value) offset as small as possible.  This reduces code
        size, especially for hosts without large memory offsets.  */
     volatile sig_atomic_t tcg_exit_req;
+
+    int (*cpu_mmu_index)(CPUState *cpu);
+    void (*cpu_get_tb_cpu_state)(CPUState *cpu,
+                                 void *pc, /* target_long * */
+                                 void *cs_base, /* target_long */
+                                 int *flags);
+    void (*gen_intermediate_code)(void *env, struct TranslationBlock *tb);
+    void (*gen_intermediate_code_pc)(void *env, struct TranslationBlock *tb);
+    void (*restore_state_to_opc)(void *env, struct TranslationBlock *tb,
+                                 int pc_pos);
+    void (*tlb_fill)(CPUState *cs, uint64_t addr, int is_write, int mmu_idx,
+                     uintptr_t retaddr);
 };
 
 QTAILQ_HEAD(CPUTailQ, CPUState);
diff --git a/qom/cpu.c b/qom/cpu.c
index 108bfa2..3fd7869 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -313,6 +313,12 @@ static void cpu_common_initfn(Object *obj)
     CPUClass *cc = CPU_GET_CLASS(obj);
 
     cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs;
+    cpu->cpu_mmu_index = cc->cpu_mmu_index;
+    cpu->cpu_get_tb_cpu_state = cc->cpu_get_tb_cpu_state;
+    cpu->gen_intermediate_code = cc->gen_intermediate_code;
+    cpu->gen_intermediate_code_pc = cc->gen_intermediate_code_pc;
+    cpu->restore_state_to_opc = cc->restore_state_to_opc;
+    cpu->tlb_fill = cc->tlb_fill;
 }
 
 static int64_t cpu_common_get_arch_id(CPUState *cpu)
diff --git a/softmmu_template.h b/softmmu_template.h
index 16b0852..dea12d2 100644
--- a/softmmu_template.h
+++ b/softmmu_template.h
@@ -141,6 +141,10 @@
     vidx >= 0;                                                                \
 })
 
+#define tlb_fill(cpu, a, f, i, r) \
+    ((cpu)->tlb_fill ? (cpu)->tlb_fill((cpu), (a), (f), (i), (r)) \
+                     : tlb_fill((cpu), (a), (f), (i), (r)))
+
 #ifndef SOFTMMU_CODE_ACCESS
 static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
                                               CPUIOTLBEntry *iotlbentry,
@@ -576,3 +580,5 @@ glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
 #undef helper_be_st_name
 #undef helper_te_ld_name
 #undef helper_te_st_name
+
+#undef tlb_fill
diff --git a/translate-all.c b/translate-all.c
index 65a76c5..1b9a405 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -144,6 +144,7 @@ void cpu_gen_init(void)
 */
 int cpu_gen_code(CPUArchState *env, TranslationBlock *tb, int *gen_code_size_ptr)
 {
+    CPUState *cs = ENV_GET_CPU(env);
     TCGContext *s = &tcg_ctx;
     tcg_insn_unit *gen_code_buf;
     int gen_code_size;
@@ -158,7 +159,11 @@ int cpu_gen_code(CPUArchState *env, TranslationBlock *tb, int *gen_code_size_ptr
 #endif
     tcg_func_start(s);
 
-    gen_intermediate_code(env, tb);
+    if (cs->gen_intermediate_code) {
+        cs->gen_intermediate_code(env, tb);
+    } else {
+        gen_intermediate_code(env, tb);
+    }
 
     trace_translate_block(tb, tb->pc, tb->tc_ptr);
 
@@ -217,7 +222,11 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
 #endif
     tcg_func_start(s);
 
-    gen_intermediate_code_pc(env, tb);
+    if (cpu->gen_intermediate_code_pc) {
+        cpu->gen_intermediate_code_pc(env, tb);
+    } else {
+        gen_intermediate_code_pc(env, tb);
+    }
 
     if (tb->cflags & CF_USE_ICOUNT) {
         /* Reset the cycle counter to the start of the block.  */
@@ -249,7 +258,11 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
     }
     cpu->icount_decr.u16.low -= s->gen_opc_icount[j];
 
-    restore_state_to_opc(env, tb, j);
+    if (cpu->restore_state_to_opc) {
+        cpu->restore_state_to_opc(env, tb, j);
+    } else {
+        restore_state_to_opc(env, tb, j);
+    }
 
 #ifdef CONFIG_PROFILER
     s->restore_time += profile_getclock() - ti;
@@ -1889,3 +1902,31 @@ int page_unprotect(target_ulong address, uintptr_t pc, void *puc)
     return 0;
 }
 #endif /* CONFIG_USER_ONLY */
+
+void __attribute__((weak)) gen_intermediate_code(CPUArchState *env,
+                                                 struct TranslationBlock *tb)
+{
+    abort();
+}
+
+void __attribute__((weak)) gen_intermediate_code_pc(CPUArchState *env,
+                                                    struct TranslationBlock *tb)
+{
+    abort();
+}
+
+void __attribute__((weak)) restore_state_to_opc(CPUArchState *env,
+                                                struct TranslationBlock *tb,
+                                                int pc_pos)
+{
+    abort();
+}
+
+#if !defined(CONFIG_USER_ONLY)
+void __attribute__((weak)) tlb_fill(CPUState *cpu, target_ulong addr,
+                                    int is_write, int mmu_idx,
+                                    uintptr_t retaddr)
+{
+    abort();
+}
+#endif
-- 
1.9.1