Re: [PATCH] Add freesync ioctl interface

From: "Christian König" <deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
To: Dave Airlie <airlied-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	Hawking Zhang <Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>
Cc: amd-gfx mailing list
	<amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Subject: Re: [PATCH] Add freesync ioctl interface
Date: Wed, 3 Aug 2016 13:16:50 +0200	[thread overview]
Message-ID: <693daa46-aec4-06f9-bf95-d9c9c40f789a@vodafone.de> (raw)
In-Reply-To: <CAPM=9twBgjLJNZ4F5xzoAk6zw-8=7ck7xfTnQOczr1TVNLnMTQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>

Am 03.08.2016 um 03:04 schrieb Dave Airlie:
> On 2 August 2016 at 12:26, Hawking Zhang <Hawking.Zhang@amd.com> wrote:
>> Change-Id: I38cb3a80e75a904cee875ae47bc0a39a3d471aca
>> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
>> ---
>>   include/drm/amdgpu_drm.h | 15 +++++++++++++++
>>   1 file changed, 15 insertions(+)
>>
>> diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
>> index 46a3c40..a4f816c 100644
>> --- a/include/drm/amdgpu_drm.h
>> +++ b/include/drm/amdgpu_drm.h
>> @@ -48,6 +48,7 @@
>>   #define DRM_AMDGPU_GEM_USERPTR         0x11
>>   #define DRM_AMDGPU_WAIT_FENCES         0x12
>>   #define DRM_AMDGPU_GEM_FIND_BO          0x13
>> +#define DRM_AMDGPU_FREESYNC             0x14
>>
>>   #define DRM_IOCTL_AMDGPU_GEM_CREATE    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
>>   #define DRM_IOCTL_AMDGPU_GEM_MMAP      DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
>> @@ -63,6 +64,7 @@
>>   #define DRM_IOCTL_AMDGPU_GEM_USERPTR   DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
>>   #define DRM_IOCTL_AMDGPU_WAIT_FENCES   DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
>>   #define DRM_IOCTL_AMDGPU_GEM_FIND_BO      DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo)
>> +#define DRM_IOCTL_AMDGPU_FREESYNC       DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync)
>>
>>   #define AMDGPU_GEM_DOMAIN_CPU          0x1
>>   #define AMDGPU_GEM_DOMAIN_GTT          0x2
>> @@ -706,4 +708,17 @@ struct drm_amdgpu_virtual_range {
>>          uint64_t start;
>>          uint64_t end;
>>   };
>> +
>> +/*
>> + * Definition of free sync enter and exit signals
>> + * We may have more options in the future
>> + */
>> +#define AMDGPU_FREESYNC_FULLSCREEN_ENTER                1
>> +#define AMDGPU_FREESYNC_FULLSCREEN_EXIT                 2
>> +
>> +struct drm_amdgpu_freesync {
>> +        __u32 op;                       /* AMDGPU_FREESYNC_FULLSCREEN_ENTER or */
>> +                                        /* AMDGPU_FREESYNC_FULLSCREEN_ENTER */
>> +        __u32 spare[7];
>> +};
>>   #endif
> Isn't freesync meant to be a generic non-driver useful thing?

Yeah, agree. Actually the general idea is so old that I've done similar 
things on the very first computer I had.

Basically instead of begin and end of the vertical blanking period 
you've got begin and max/min end.

Every hardware which can a) generate an interrupt when vertical blanking 
starts and b) adjust the vertical scan out position by the CPU should be 
able to implement that.

Regards,
Christian.

>
> This should be integrated with atomic modesetting API or just the KMS APIs.
>
> Dave.
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx

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