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From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: guochun.mao@mediatek.com, Mark Brown <broonie@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>
Cc: Zhen Zhang <zhen.zhang@mediatek.com>,
	Bayi Cheng <bayi.cheng@mediatek.com>,
	Chuanhong Guo <gch981213@gmail.com>,
	linux-mediatek@lists.infradead.org, srv_heupstream@mediatek.com
Subject: Re: [PATCH v1 2/4] spi: spi-mtk-nor: improve device table for adding more capabilities
Date: Fri, 14 Jan 2022 11:40:27 +0100	[thread overview]
Message-ID: <698a603b-574c-01ca-9e6b-edecdbc5959e@collabora.com> (raw)
In-Reply-To: <20220114062408.9077-3-guochun.mao@mediatek.com>

Il 14/01/22 07:24, guochun.mao@mediatek.com ha scritto:
> From: Guochun Mao <guochun.mao@mediatek.com>

Hello Guochun,

thanks for the patch! However, I have some comments...

> 
> Define a structure for adding more capabilities.

Please also mention that you're adding the extra_dummy_bit feature
in the commit description.

> 
> Signed-off-by: Guochun Mao <guochun.mao@mediatek.com>
> Signed-off-by: Zhen Zhang <zhen.zhang@mediatek.com>
> ---
>   drivers/spi/spi-mtk-nor.c | 40 +++++++++++++++++++++++++++++++--------
>   1 file changed, 32 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/spi/spi-mtk-nor.c b/drivers/spi/spi-mtk-nor.c
> index 5c93730615f8..f3bcdc1d4d8b 100644
> --- a/drivers/spi/spi-mtk-nor.c
> +++ b/drivers/spi/spi-mtk-nor.c
> @@ -95,6 +95,11 @@
>   
>   #define CLK_TO_US(sp, clkcnt)		DIV_ROUND_UP(clkcnt, sp->spi_freq / 1000000)
>   
> +struct mtk_nor_caps {
> +	u32 dma_bits;

dma_bits can be u8: I really don't think that we'll ever see more than
0xff bits...

> +	u32 extra_dummy_bit;

This one looks a bit strange, can you please add a comment explaining the
reason why we have this "extra dummy bit"?

> +};
> +
>   struct mtk_nor {
>   	struct spi_controller *ctlr;
>   	struct device *dev;
> @@ -109,6 +114,7 @@ struct mtk_nor {
>   	bool has_irq;
>   	bool high_dma;
>   	struct completion op_done;
> +	const struct mtk_nor_caps *caps;
>   };
>   
>   static inline void mtk_nor_rmw(struct mtk_nor *sp, u32 reg, u32 set, u32 clr)
> @@ -554,7 +560,12 @@ static int mtk_nor_spi_mem_prg(struct mtk_nor *sp, const struct spi_mem_op *op)
>   	}
>   
>   	// trigger op
> -	writel(prg_len * BITS_PER_BYTE, sp->base + MTK_NOR_REG_PRG_CNT);
> +	if (rx_len)
> +		writel(prg_len * BITS_PER_BYTE + sp->caps->extra_dummy_bit,
> +		       sp->base + MTK_NOR_REG_PRG_CNT);
> +	else
> +		writel(prg_len * BITS_PER_BYTE, sp->base + MTK_NOR_REG_PRG_CNT);
> +
>   	ret = mtk_nor_cmd_exec(sp, MTK_NOR_CMD_PROGRAM,
>   			       prg_len * BITS_PER_BYTE);
>   	if (ret)
> @@ -743,9 +754,19 @@ static const struct spi_controller_mem_ops mtk_nor_mem_ops = {
>   	.exec_op = mtk_nor_exec_op
>   };
>   
> +const struct mtk_nor_caps mtk_nor_caps_mt8173 = {
> +	.dma_bits = 32,
> +	.extra_dummy_bit = 0,
> +};
> +
> +const struct mtk_nor_caps mtk_nor_caps_mt8192 = {
> +	.dma_bits = 36,
> +	.extra_dummy_bit = 0,
> +};
> +
>   static const struct of_device_id mtk_nor_match[] = {
> -	{ .compatible = "mediatek,mt8192-nor", .data = (void *)36 },
> -	{ .compatible = "mediatek,mt8173-nor", .data = (void *)32 },
> +	{ .compatible = "mediatek,mt8173-nor", .data = &mtk_nor_caps_mt8173 },
> +	{ .compatible = "mediatek,mt8192-nor", .data = &mtk_nor_caps_mt8192 },
>   	{ /* sentinel */ }
>   };
>   MODULE_DEVICE_TABLE(of, mtk_nor_match);
> @@ -754,10 +775,10 @@ static int mtk_nor_probe(struct platform_device *pdev)
>   {
>   	struct spi_controller *ctlr;
>   	struct mtk_nor *sp;
> +	struct mtk_nor_caps *caps;
>   	void __iomem *base;
>   	struct clk *spi_clk, *ctlr_clk, *axi_clk;
>   	int ret, irq;
> -	unsigned long dma_bits;
>   
>   	base = devm_platform_ioremap_resource(pdev, 0);
>   	if (IS_ERR(base))
> @@ -775,9 +796,11 @@ static int mtk_nor_probe(struct platform_device *pdev)
>   	if (IS_ERR(axi_clk))
>   		return PTR_ERR(axi_clk);
>   
> -	dma_bits = (unsigned long)of_device_get_match_data(&pdev->dev);
> -	if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits))) {
> -		dev_err(&pdev->dev, "failed to set dma mask(%lu)\n", dma_bits);
> +	caps = (struct mtk_nor_caps *)of_device_get_match_data(&pdev->dev);
> +	if (dma_set_mask_and_coherent(&pdev->dev,
> +				      DMA_BIT_MASK(caps->dma_bits))) {

While you're at it, can you please also make this return the right value?
The function dma_set_mask_and_coherent() may return an error code, so it's
worth it to just return that.

P.S.: 83 columns is ok

	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(caps->dma_bits));
	if (ret) {

> +		dev_err(&pdev->dev, "failed to set dma mask(%u)\n",
> +			caps->dma_bits);
>   		return -EINVAL;
>   	}
>   
> @@ -808,7 +831,8 @@ static int mtk_nor_probe(struct platform_device *pdev)
>   	sp->spi_clk = spi_clk;
>   	sp->ctlr_clk = ctlr_clk;
>   	sp->axi_clk = axi_clk;
> -	sp->high_dma = (dma_bits > 32);
> +	sp->caps = caps;
> +	sp->high_dma = caps->dma_bits > 32;
>   	sp->buffer = dmam_alloc_coherent(&pdev->dev,
>   				MTK_NOR_BOUNCE_BUF_SIZE + MTK_NOR_DMA_ALIGN,
>   				&sp->buffer_dma, GFP_KERNEL);
> 

Regards,
- Angelo

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  reply	other threads:[~2022-01-14 10:40 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-14  6:24 [PATCH V1 0/4] mainly add a new SoC support for spi-mtk-nor guochun.mao
2022-01-14  6:24 ` [PATCH v1 1/4] dt-bindings: spi: add mt8186-nor compatible string guochun.mao
2022-01-14 14:54   ` Rob Herring
2022-01-17  2:08     ` Guochun Mao
2022-01-14  6:24 ` [PATCH v1 2/4] spi: spi-mtk-nor: improve device table for adding more capabilities guochun.mao
2022-01-14 10:40   ` AngeloGioacchino Del Regno [this message]
2022-01-17  2:30     ` Guochun Mao
2022-01-17 10:16       ` AngeloGioacchino Del Regno
2022-01-18  1:12         ` Guochun Mao
2022-01-14  6:24 ` [PATCH v1 3/4] spi: spi-mtk-nor: add new soc mt8186 support guochun.mao
2022-01-14  6:24 ` [PATCH v1 4/4] spi: spi-mtk-nor: add axi_s clock for mt8186 guochun.mao
2022-01-14 10:41   ` AngeloGioacchino Del Regno

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