From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH 04/15] target/arm: Implement VSCCLRM insn
Date: Tue, 17 Nov 2020 11:31:40 -0800 [thread overview]
Message-ID: <698b908c-0406-cdb9-4bdf-253693a85655@linaro.org> (raw)
In-Reply-To: <20201116160831.31000-5-peter.maydell@linaro.org>
On 11/16/20 8:08 AM, Peter Maydell wrote:
> + aspen = load_cpu_field(v7m.fpccr[M_REG_S]);
> + sfpa = load_cpu_field(v7m.control[M_REG_S]);
> + tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
> + tcg_gen_subi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
xori would be clearer, i think.
> + /* Zero the Sregs from btmreg to topreg inclusive. */
> + zero64 = tcg_const_i64(0);
> + zero32 = tcg_const_i32(0);
> + if (btmreg & 1) {
> + write_neon_element32(zero32, btmreg >> 1, 1, MO_32);
> + btmreg++;
> + }
> + for (; btmreg + 1 <= topreg; btmreg += 2) {
> + write_neon_element64(zero64, btmreg >> 1, 0, MO_64);
> + }
> + if (btmreg == topreg) {
> + write_neon_element32(zero32, btmreg >> 1, 0, MO_32);
> + btmreg++;
> + }
I hadn't implemented MO_32 for write_neon_element64 because there were no
users. Better to just add the case there using tcg_gen_st32_i64, then you
don't need a 32-bit zero.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2020-11-17 19:33 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-16 16:08 [PATCH 00/15] target/arm: More v8.1M features Peter Maydell
2020-11-16 16:08 ` [PATCH 01/15] hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault Peter Maydell
2020-11-17 19:07 ` Richard Henderson
2020-11-16 16:08 ` [PATCH 02/15] target/arm: Implement v8.1M PXN extension Peter Maydell
2020-11-17 19:10 ` Richard Henderson
2020-11-16 16:08 ` [PATCH 03/15] target/arm: Don't clobber ID_PFR1.Security on M-profile cores Peter Maydell
2020-11-17 19:12 ` Richard Henderson
2020-11-16 16:08 ` [PATCH 04/15] target/arm: Implement VSCCLRM insn Peter Maydell
2020-11-17 19:31 ` Richard Henderson [this message]
2020-11-16 16:08 ` [PATCH 05/15] target/arm: Implement CLRM instruction Peter Maydell
2020-11-17 19:38 ` Richard Henderson
2020-11-16 16:08 ` [PATCH 06/15] target/arm: Enforce M-profile VMRS/VMSR register restrictions Peter Maydell
2020-11-17 19:42 ` Richard Henderson
2020-11-17 21:18 ` Peter Maydell
2020-11-16 16:08 ` [PATCH 07/15] target/arm: Refactor M-profile VMSR/VMRS handling Peter Maydell
2020-11-16 16:08 ` [PATCH 08/15] target/arm: Move general-use constant expanders up in translate.c Peter Maydell
2020-11-17 19:47 ` Richard Henderson
2020-11-16 16:08 ` [PATCH 09/15] target/arm: Implement VLDR/VSTR system register Peter Maydell
2020-11-16 16:08 ` [PATCH 10/15] target/arm: Implement M-profile FPSCR_nzcvqc Peter Maydell
2020-11-16 16:08 ` [PATCH 11/15] target/arm: Use new FPCR_NZCV_MASK constant Peter Maydell
2020-11-17 19:49 ` Richard Henderson
2020-11-16 16:08 ` [PATCH 12/15] target/arm: Factor out preserve-fp-state from full_vfp_access_check() Peter Maydell
2020-11-17 19:50 ` Richard Henderson
2020-11-16 16:08 ` [PATCH 13/15] target/arm: Implement FPCXT_S fp system register Peter Maydell
2020-11-16 16:08 ` [PATCH 14/15] target/arm: Implement FPCXT_NS " Peter Maydell
2020-11-16 16:08 ` [PATCH 15/15] hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M Peter Maydell
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