From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:36291) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMP96-0001ru-Uj for qemu-devel@nongnu.org; Thu, 02 May 2019 23:46:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hMP96-0003iv-1b for qemu-devel@nongnu.org; Thu, 02 May 2019 23:46:00 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:40115) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hMP95-0003iO-Q5 for qemu-devel@nongnu.org; Thu, 02 May 2019 23:45:59 -0400 Received: by mail-pl1-x641.google.com with SMTP id b3so2026500plr.7 for ; Thu, 02 May 2019 20:45:59 -0700 (PDT) References: <20190502141019.6385-1-david@redhat.com> <20190502141019.6385-3-david@redhat.com> From: Richard Henderson Message-ID: <69b8508d-9586-ab11-3318-83d21ddd4d25@linaro.org> Date: Thu, 2 May 2019 20:45:55 -0700 MIME-Version: 1.0 In-Reply-To: <20190502141019.6385-3-david@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v3 02/40] s390x/tcg: Implement VECTOR ADD COMPUTE CARRY List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Hildenbrand , qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Cornelia Huck , Thomas Huth , Richard Henderson On 5/2/19 7:09 AM, David Hildenbrand wrote: > 128-bit handling courtesy of Richard H. > > Signed-off-by: David Hildenbrand > --- > target/s390x/insn-data.def | 2 + > target/s390x/translate_vx.inc.c | 94 +++++++++++++++++++++++++++++++++ > 2 files changed, 96 insertions(+) Reviewed-by: Richard Henderson > +static void gen_acc(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, uint8_t es) > +{ > + const uint8_t msb_bit_nr = NUM_VEC_ELEMENT_BITS(es) - 1; > + TCGv_i64 msb_mask = tcg_const_i64(dup_const(es, 1ull << msb_bit_nr)); > + TCGv_i64 t1 = tcg_temp_new_i64(); > + TCGv_i64 t2 = tcg_temp_new_i64(); > + TCGv_i64 t3 = tcg_temp_new_i64(); > + > + /* Calculate the carry into the MSB, ignoring the old MSBs */ > + tcg_gen_andc_i64(t1, a, msb_mask); > + tcg_gen_andc_i64(t2, b, msb_mask); > + tcg_gen_add_i64(t1, t1, t2); > + /* Calculate the MSB without any carry into it */ > + tcg_gen_xor_i64(t3, a, b); > + /* Calculate the carry out of the MSB in the MSB bit position */ > + tcg_gen_and_i64(d, a, b); > + tcg_gen_and_i64(t1, t1, t3); > + tcg_gen_or_i64(d, d, t1); > + /* Isolate and shift the carry into position */ > + tcg_gen_and_i64(d, d, msb_mask); > + tcg_gen_shri_i64(d, d, msb_bit_nr); > + > + tcg_temp_free_i64(t1); > + tcg_temp_free_i64(t2); > + tcg_temp_free_i64(t3); > +} ...> +static void gen_acc32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) > +{ > + gen_acc(d, a, b, ES_32); > +} > + > +static void gen_acc_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) > +{ > + TCGv_i64 t = tcg_temp_new_i64(); > + > + tcg_gen_add_i64(t, a, b); > + tcg_gen_setcond_i64(TCG_COND_LTU, d, t, b); > + tcg_temp_free_i64(t); > +} As an aside, I think the 32-bit version should use 32-bit ops, as per gen_acc_i64. That would be 4 * 2 operations instead of 2 * 9 over the 128-bit vector. r~