From: <Claudiu.Beznea@microchip.com> To: <firstname.lastname@example.org>, <email@example.com>, <firstname.lastname@example.org>, <Nicolas.Ferre@microchip.com>, <Kavyasree.Kotagiri@microchip.com> Cc: <email@example.com>, <firstname.lastname@example.org> Subject: Re: [PATCH] ARM: dts: lan966x: fix sys_clk frequency Date: Mon, 18 Jul 2022 06:36:48 +0000 [thread overview] Message-ID: <email@example.com> (raw) In-Reply-To: <firstname.lastname@example.org> On 15.07.2022 21:41, Michael Walle wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > [+ Claudiu as he seems to pick patches for at91, too] > > Am 2022-06-22 13:51, schrieb Michael Walle: >> Am 2022-04-28 10:49, schrieb Michael Walle: >>> Am 2022-03-26 20:40, schrieb Michael Walle: >>>> The sys_clk frequency is 165.625MHz. The register reference of the >>>> Generic Clock controller lists the CPU clock as 600MHz, the DDR clock >>>> as >>>> 300MHz and the SYS clock as 162.5MHz. This is wrong. It was first >>>> noticed during the fan driver development and it was measured and >>>> verified via the CLK_MON output of the SoC which can be configured to >>>> output sys_clk/64. >>>> >>>> The core PLL settings (which drives the SYS clock) seems to be as >>>> follows: >>>> DIVF = 52 >>>> DIVQ = 3 >>>> DIVR = 1 >>>> >>>> With a refernce clock of 25MHz, this means we have a post divider >>>> clock >>>> Fpfd = Fref / (DIVR + 1) = 25MHz / (1 + 1) = 12.5MHz >>>> >>>> The resulting VCO frequency is then >>>> Fvco = Fpfd * (DIVF + 1) * 2 = 12.5MHz * (52 + 1) * 2 = 1325MHz >>>> >>>> And the output frequency is >>>> Fout = Fvco / 2^DIVQ = 1325MHz / 2^3 = 165.625Mhz >>>> >>>> This all adds up to the constrains of the PLL: >>>> 10MHz <= Fpfd <= 200MHz >>>> 20MHz <= Fout <= 1000MHz >>>> 1000MHz <= Fvco <= 2000MHz >>>> >>>> Fixes: 290deaa10c50 ("ARM: dts: add DT for lan966 SoC and 2-port >>>> board pcb8291") >>>> Signed-off-by: Michael Walle <email@example.com> Applied to at91-fixes, thanks! >>> >>> Ping :) >>> >>> Btw. this is also true for the new B0 silicon. I just verified it >>> with the CLK_MON output. >> >> Ping #2. >> >> Could this please be picked up because most drivers use this property >> to calculate output frequencies and so on, e.g. the PWM driver. > > Ping #3. Now it even got a Reviewed-by. > > -michael
next prev parent reply other threads:[~2022-07-18 6:37 UTC|newest] Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-03-26 19:40 Michael Walle 2022-04-28 8:49 ` Michael Walle 2022-06-22 11:51 ` Michael Walle 2022-07-15 18:41 ` Michael Walle 2022-07-18 6:36 ` Claudiu.Beznea [this message] 2022-06-29 11:40 ` Kavyasree.Kotagiri
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