From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751787AbdCHJfm (ORCPT ); Wed, 8 Mar 2017 04:35:42 -0500 Received: from foss.arm.com ([217.140.101.70]:56788 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750728AbdCHJfi (ORCPT ); Wed, 8 Mar 2017 04:35:38 -0500 Subject: Re: [PATCH] reset: sunxi: fix for 64-bit compilation To: Chen-Yu Tsai References: <1488764156-22197-1-git-send-email-andre.przywara@arm.com> Cc: Maxime Ripard , Philipp Zabel , linux-arm-kernel , linux-kernel From: Andre Przywara Message-ID: <6a0e362b-8ebf-6254-6387-12967ec8c484@arm.com> Date: Wed, 8 Mar 2017 09:26:01 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.7.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 08/03/17 04:28, Chen-Yu Tsai wrote: > On Mon, Mar 6, 2017 at 9:35 AM, Andre Przywara wrote: >> The Allwinner reset controller has 32-bit registers, so translating >> the reset cell number into a register and bit offset should not use >> any architecture dependent data size. Otherwise this breaks for 64-bit >> architectures like arm64. >> Fix this by making it clear that it's the hardware register width which >> matters here in the calculation. >> >> Signed-off-by: Andre Przywara > > Acked-by: Chen-Yu Tsai Thanks a lot! > Though I don't expect this driver to be used with arm64 chips. Well, weren't we toying with the idea of using this for the A64 PRCM support? Also the driver is actually pretty generic, and I have (renaming) patches lying around to make this obvious. This is partly driven by a side project for some (arm64) SoC support, which can happily use that driver to tackle its device reset support. So as this is an obvious bug, I'd rather see this fixed now. Cheers, Andre. From mboxrd@z Thu Jan 1 00:00:00 1970 From: andre.przywara@arm.com (Andre Przywara) Date: Wed, 8 Mar 2017 09:26:01 +0000 Subject: [PATCH] reset: sunxi: fix for 64-bit compilation In-Reply-To: References: <1488764156-22197-1-git-send-email-andre.przywara@arm.com> Message-ID: <6a0e362b-8ebf-6254-6387-12967ec8c484@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi, On 08/03/17 04:28, Chen-Yu Tsai wrote: > On Mon, Mar 6, 2017 at 9:35 AM, Andre Przywara wrote: >> The Allwinner reset controller has 32-bit registers, so translating >> the reset cell number into a register and bit offset should not use >> any architecture dependent data size. Otherwise this breaks for 64-bit >> architectures like arm64. >> Fix this by making it clear that it's the hardware register width which >> matters here in the calculation. >> >> Signed-off-by: Andre Przywara > > Acked-by: Chen-Yu Tsai Thanks a lot! > Though I don't expect this driver to be used with arm64 chips. Well, weren't we toying with the idea of using this for the A64 PRCM support? Also the driver is actually pretty generic, and I have (renaming) patches lying around to make this obvious. This is partly driven by a side project for some (arm64) SoC support, which can happily use that driver to tackle its device reset support. So as this is an obvious bug, I'd rather see this fixed now. Cheers, Andre.