From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41344) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fLSpa-0002ZZ-9f for qemu-devel@nongnu.org; Wed, 23 May 2018 08:25:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fLSpW-0003ER-Ek for qemu-devel@nongnu.org; Wed, 23 May 2018 08:25:26 -0400 Received: from mail-qt0-x242.google.com ([2607:f8b0:400d:c0d::242]:40833) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fLSpW-0003EL-A1 for qemu-devel@nongnu.org; Wed, 23 May 2018 08:25:22 -0400 Received: by mail-qt0-x242.google.com with SMTP id h2-v6so27735833qtp.7 for ; Wed, 23 May 2018 05:25:22 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= References: <1527034517-7851-1-git-send-email-mjc@sifive.com> <1527034517-7851-12-git-send-email-mjc@sifive.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <6a7f5b63-21bc-6632-ea9d-c8d2f9a6d240@amsat.org> Date: Wed, 23 May 2018 09:25:17 -0300 MIME-Version: 1.0 In-Reply-To: <1527034517-7851-12-git-send-email-mjc@sifive.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH v1 11/30] RISC-V: Split out mstatus_fs from tb_flags List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Michael Clark , qemu-devel@nongnu.org Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Richard Henderson , Alistair Francis , patches@groups.riscv.org On 05/22/2018 09:14 PM, Michael Clark wrote: > From: Richard Henderson > > Cc: Sagar Karandikar > Cc: Bastian Koppelmann > Cc: Palmer Dabbelt > Cc: Alistair Francis > Cc: Richard Henderson > Signed-off-by: Michael Clark > Reviewed-by: Michael Clark Reviewed-by: Philippe Mathieu-Daudé > --- > target/riscv/cpu.h | 6 +++--- > target/riscv/translate.c | 10 +++++----- > 2 files changed, 8 insertions(+), 8 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 3a3d91447736..242a8fcbe180 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -276,8 +276,8 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env, > target_ulong cpu_riscv_get_fflags(CPURISCVState *env); > void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong); > > -#define TB_FLAGS_MMU_MASK 3 > -#define TB_FLAGS_FP_ENABLE MSTATUS_FS > +#define TB_FLAGS_MMU_MASK 3 > +#define TB_FLAGS_MSTATUS_FS MSTATUS_FS > > static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, > target_ulong *cs_base, uint32_t *flags) > @@ -285,7 +285,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, > *pc = env->pc; > *cs_base = 0; > #ifdef CONFIG_USER_ONLY > - *flags = TB_FLAGS_FP_ENABLE; > + *flags = TB_FLAGS_MSTATUS_FS; > #else > *flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS); > #endif > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index ee2bbc55b051..466b9551cbd9 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -44,7 +44,7 @@ typedef struct DisasContext { > /* pc_succ_insn points to the instruction following base.pc_next */ > target_ulong pc_succ_insn; > uint32_t opcode; > - uint32_t flags; > + uint32_t mstatus_fs; > uint32_t mem_idx; > /* Remember the rounding mode encoded in the previous fp instruction, > which we have already installed into env->fp_status. Or -1 for > @@ -656,7 +656,7 @@ static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, > { > TCGv t0; > > - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) { > + if (ctx->mstatus_fs == 0) { > gen_exception_illegal(ctx); > return; > } > @@ -686,7 +686,7 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1, > { > TCGv t0; > > - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) { > + if (ctx->mstatus_fs == 0) { > gen_exception_illegal(ctx); > return; > } > @@ -945,7 +945,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, > { > TCGv t0 = NULL; > > - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) { > + if (ctx->mstatus_fs == 0) { > goto do_illegal; > } > > @@ -1810,8 +1810,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) > DisasContext *ctx = container_of(dcbase, DisasContext, base); > > ctx->pc_succ_insn = ctx->base.pc_first; > - ctx->flags = ctx->base.tb->flags; > ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK; > + ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS; > ctx->frm = -1; /* unknown rounding mode */ > } > >