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[88.21.205.111]) by smtp.gmail.com with ESMTPSA id c2sm28645232wrf.68.2020.11.30.04.13.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 30 Nov 2020 04:13:10 -0800 (PST) Subject: Re: [PATCH v2 1/3] target/nios2: Move IIC code into CPU object proper To: Peter Maydell , qemu-devel@nongnu.org References: <20201129174022.26530-1-peter.maydell@linaro.org> <20201129174022.26530-2-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <6ac9a9b2-f8f9-2437-c4f1-953b8c66729d@amsat.org> Date: Mon, 30 Nov 2020 13:13:09 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.4.0 MIME-Version: 1.0 In-Reply-To: <20201129174022.26530-2-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x441.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Sandra Loosemore , Chris Wulff , Wentong Wu Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 11/29/20 6:40 PM, Peter Maydell wrote: > The Nios2 architecture supports two different interrupt controller > options: > > * The IIC (Internal Interrupt Controller) is part of the CPU itself; > it has 32 IRQ input lines and no NMI support. Interrupt status is > queried and controlled via the CPU's ipending and istatus > registers. > > * The EIC (External Interrupt Controller) interface allows the CPU > to connect to an external interrupt controller. The interface > allows the interrupt controller to present a packet of information > containing: > - handler address > - interrupt level > - register set > - NMI mode > > QEMU does not model an EIC currently. We do model the IIC, but its > implementation is split across code in hw/nios2/cpu_pic.c and > hw/intc/nios2_iic.c. The code in those two files has no state of its > own -- the IIC state is in the Nios2CPU state struct. > > Because CPU objects now inherit (indirectly) from TYPE_DEVICE, they > can have GPIO input lines themselves, so we can implement the IIC > directly in the CPU object the same way that real hardware does. > > Create named "IRQ" GPIO inputs to the Nios2 CPU object, and make the > only user of the IIC wire up directly to those instead. > > Note that the old code had an "NMI" concept which was entirely unused > and also as far as I can see not architecturally correct, since only > the EIC has a concept of an NMI. > > This fixes a Coverity-reported trivial memory leak of the IRQ array > allocated in nios2_cpu_pic_init(). > > Fixes: Coverity CID 1421916 > Signed-off-by: Peter Maydell > --- > target/nios2/cpu.h | 1 - > hw/intc/nios2_iic.c | 95 --------------------------------------- > hw/nios2/10m50_devboard.c | 13 +----- > hw/nios2/cpu_pic.c | 31 ------------- > target/nios2/cpu.c | 30 +++++++++++++ > MAINTAINERS | 1 - > hw/intc/meson.build | 1 - > 7 files changed, 32 insertions(+), 140 deletions(-) > delete mode 100644 hw/intc/nios2_iic.c Reviewed-by: Philippe Mathieu-Daudé