* [PATCH v3 00/20] Support UXL filed in xstatus
@ 2021-11-11 5:57 ` LIU Zhiwei
0 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, richard.henderson, bin.meng, Alistair.Francis, LIU Zhiwei
In this patch set, we process the pc reigsters writes,
gdb reads and writes, and address calculation under
different UXLEN settings.
The patch set v3 mainly address Richard comments on v2.
Patch 1,2,3,5,6,16,17 have been reviewed.
v3:
Merge gen_pm_adjust_address into a canonical address function
Adjust address for RVA with XLEN
Split pm_enabled into pm_mask_enabled and pm_base_enabled
Replace array of pm tcg globals with one scalar tcg global
Split and change patch sequence
v2:
Split out vill from vtype
Remove context switch when xlen changes at exception
Use XL instead of OL in many places
Use pointer masking and XLEN for vector address
Define an common fuction to calculate address for ldst
LIU Zhiwei (20):
target/riscv: Don't save pc when exception return
target/riscv: Sign extend pc for different XLEN
target/riscv: Ignore the pc bits above XLEN
target/riscv: Extend pc for runtime pc write
target/riscv: Use gdb xml according to max mxlen
target/riscv: Relax debug check for pm write
target/riscv: Adjust csr write mask with XLEN
target/riscv: Create current pm fields in env
target/riscv: Alloc tcg global for cur_pm[mask|base]
target/riscv: Calculate address according to XLEN
target/riscv: Split pm_enabled into mask and base
target/riscv: Split out the vill from vtype
target/riscv: Fix RESERVED field length in VTYPE
target/riscv: Adjust vsetvl according to XLEN
target/riscv: Remove VILL field in VTYPE
target/riscv: Ajdust vector atomic check with XLEN
target/riscv: Fix check range for first fault only
target/riscv: Adjust vector address with mask
target/riscv: Adjust scalar reg in vector with XLEN
target/riscv: Enable uxl field write
target/riscv/cpu.c | 23 +++++-
target/riscv/cpu.h | 13 +++-
target/riscv/cpu_helper.c | 66 ++++++++++++----
target/riscv/csr.c | 40 +++++++++-
target/riscv/gdbstub.c | 71 ++++++++++++-----
target/riscv/helper.h | 6 +-
.../riscv/insn_trans/trans_privileged.c.inc | 7 +-
target/riscv/insn_trans/trans_rva.c.inc | 9 +--
target/riscv/insn_trans/trans_rvd.c.inc | 19 +----
target/riscv/insn_trans/trans_rvf.c.inc | 19 +----
target/riscv/insn_trans/trans_rvi.c.inc | 22 +-----
target/riscv/insn_trans/trans_rvv.c.inc | 51 ++++++++----
target/riscv/machine.c | 11 +++
target/riscv/op_helper.c | 7 +-
target/riscv/translate.c | 77 +++++++++----------
target/riscv/vector_helper.c | 38 +++++----
16 files changed, 293 insertions(+), 186 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v3 00/20] Support UXL filed in xstatus
@ 2021-11-11 5:57 ` LIU Zhiwei
0 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Alistair.Francis, palmer, bin.meng, richard.henderson, LIU Zhiwei
In this patch set, we process the pc reigsters writes,
gdb reads and writes, and address calculation under
different UXLEN settings.
The patch set v3 mainly address Richard comments on v2.
Patch 1,2,3,5,6,16,17 have been reviewed.
v3:
Merge gen_pm_adjust_address into a canonical address function
Adjust address for RVA with XLEN
Split pm_enabled into pm_mask_enabled and pm_base_enabled
Replace array of pm tcg globals with one scalar tcg global
Split and change patch sequence
v2:
Split out vill from vtype
Remove context switch when xlen changes at exception
Use XL instead of OL in many places
Use pointer masking and XLEN for vector address
Define an common fuction to calculate address for ldst
LIU Zhiwei (20):
target/riscv: Don't save pc when exception return
target/riscv: Sign extend pc for different XLEN
target/riscv: Ignore the pc bits above XLEN
target/riscv: Extend pc for runtime pc write
target/riscv: Use gdb xml according to max mxlen
target/riscv: Relax debug check for pm write
target/riscv: Adjust csr write mask with XLEN
target/riscv: Create current pm fields in env
target/riscv: Alloc tcg global for cur_pm[mask|base]
target/riscv: Calculate address according to XLEN
target/riscv: Split pm_enabled into mask and base
target/riscv: Split out the vill from vtype
target/riscv: Fix RESERVED field length in VTYPE
target/riscv: Adjust vsetvl according to XLEN
target/riscv: Remove VILL field in VTYPE
target/riscv: Ajdust vector atomic check with XLEN
target/riscv: Fix check range for first fault only
target/riscv: Adjust vector address with mask
target/riscv: Adjust scalar reg in vector with XLEN
target/riscv: Enable uxl field write
target/riscv/cpu.c | 23 +++++-
target/riscv/cpu.h | 13 +++-
target/riscv/cpu_helper.c | 66 ++++++++++++----
target/riscv/csr.c | 40 +++++++++-
target/riscv/gdbstub.c | 71 ++++++++++++-----
target/riscv/helper.h | 6 +-
.../riscv/insn_trans/trans_privileged.c.inc | 7 +-
target/riscv/insn_trans/trans_rva.c.inc | 9 +--
target/riscv/insn_trans/trans_rvd.c.inc | 19 +----
target/riscv/insn_trans/trans_rvf.c.inc | 19 +----
target/riscv/insn_trans/trans_rvi.c.inc | 22 +-----
target/riscv/insn_trans/trans_rvv.c.inc | 51 ++++++++----
target/riscv/machine.c | 11 +++
target/riscv/op_helper.c | 7 +-
target/riscv/translate.c | 77 +++++++++----------
target/riscv/vector_helper.c | 38 +++++----
16 files changed, 293 insertions(+), 186 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v3 01/20] target/riscv: Don't save pc when exception return
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 5:57 ` LIU Zhiwei
-1 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, richard.henderson, bin.meng, Alistair.Francis, LIU Zhiwei
As pc will be written by the xepc in exception return, just ignore
pc in translation.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/helper.h | 4 ++--
target/riscv/insn_trans/trans_privileged.c.inc | 7 ++-----
target/riscv/op_helper.c | 4 ++--
3 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index c7a5376227..c5098380dd 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -67,8 +67,8 @@ DEF_HELPER_2(csrr, tl, env, int)
DEF_HELPER_3(csrw, void, env, int, tl)
DEF_HELPER_4(csrrw, tl, env, int, tl, tl)
#ifndef CONFIG_USER_ONLY
-DEF_HELPER_2(sret, tl, env, tl)
-DEF_HELPER_2(mret, tl, env, tl)
+DEF_HELPER_1(sret, tl, env)
+DEF_HELPER_1(mret, tl, env)
DEF_HELPER_1(wfi, void, env)
DEF_HELPER_1(tlb_flush, void, env)
#endif
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index 75c6ef80a6..6077bbbf11 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -74,10 +74,8 @@ static bool trans_uret(DisasContext *ctx, arg_uret *a)
static bool trans_sret(DisasContext *ctx, arg_sret *a)
{
#ifndef CONFIG_USER_ONLY
- tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-
if (has_ext(ctx, RVS)) {
- gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
+ gen_helper_sret(cpu_pc, cpu_env);
tcg_gen_exit_tb(NULL, 0); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
} else {
@@ -92,8 +90,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
static bool trans_mret(DisasContext *ctx, arg_mret *a)
{
#ifndef CONFIG_USER_ONLY
- tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
- gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
+ gen_helper_mret(cpu_pc, cpu_env);
tcg_gen_exit_tb(NULL, 0); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
return true;
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index ee7c24efe7..095d39671b 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -71,7 +71,7 @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
#ifndef CONFIG_USER_ONLY
-target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
+target_ulong helper_sret(CPURISCVState *env)
{
uint64_t mstatus;
target_ulong prev_priv, prev_virt;
@@ -132,7 +132,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
return retpc;
}
-target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
+target_ulong helper_mret(CPURISCVState *env)
{
if (!(env->priv >= PRV_M)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 01/20] target/riscv: Don't save pc when exception return
@ 2021-11-11 5:57 ` LIU Zhiwei
0 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Alistair.Francis, palmer, bin.meng, richard.henderson, LIU Zhiwei
As pc will be written by the xepc in exception return, just ignore
pc in translation.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/helper.h | 4 ++--
target/riscv/insn_trans/trans_privileged.c.inc | 7 ++-----
target/riscv/op_helper.c | 4 ++--
3 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index c7a5376227..c5098380dd 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -67,8 +67,8 @@ DEF_HELPER_2(csrr, tl, env, int)
DEF_HELPER_3(csrw, void, env, int, tl)
DEF_HELPER_4(csrrw, tl, env, int, tl, tl)
#ifndef CONFIG_USER_ONLY
-DEF_HELPER_2(sret, tl, env, tl)
-DEF_HELPER_2(mret, tl, env, tl)
+DEF_HELPER_1(sret, tl, env)
+DEF_HELPER_1(mret, tl, env)
DEF_HELPER_1(wfi, void, env)
DEF_HELPER_1(tlb_flush, void, env)
#endif
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index 75c6ef80a6..6077bbbf11 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -74,10 +74,8 @@ static bool trans_uret(DisasContext *ctx, arg_uret *a)
static bool trans_sret(DisasContext *ctx, arg_sret *a)
{
#ifndef CONFIG_USER_ONLY
- tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-
if (has_ext(ctx, RVS)) {
- gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
+ gen_helper_sret(cpu_pc, cpu_env);
tcg_gen_exit_tb(NULL, 0); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
} else {
@@ -92,8 +90,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
static bool trans_mret(DisasContext *ctx, arg_mret *a)
{
#ifndef CONFIG_USER_ONLY
- tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
- gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
+ gen_helper_mret(cpu_pc, cpu_env);
tcg_gen_exit_tb(NULL, 0); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
return true;
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index ee7c24efe7..095d39671b 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -71,7 +71,7 @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
#ifndef CONFIG_USER_ONLY
-target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
+target_ulong helper_sret(CPURISCVState *env)
{
uint64_t mstatus;
target_ulong prev_priv, prev_virt;
@@ -132,7 +132,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
return retpc;
}
-target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
+target_ulong helper_mret(CPURISCVState *env)
{
if (!(env->priv >= PRV_M)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 02/20] target/riscv: Sign extend pc for different XLEN
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 5:57 ` LIU Zhiwei
-1 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, richard.henderson, bin.meng, Alistair.Francis, LIU Zhiwei
When pc is written, it is sign-extended to fill the widest supported XLEN.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/translate.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 1d57bc97b5..a6a73ced9e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -150,16 +150,24 @@ static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
}
+static void gen_set_pc(DisasContext *ctx, target_ulong dest)
+{
+ if (get_xl(ctx) == MXL_RV32) {
+ dest = (int32_t)dest;
+ }
+ tcg_gen_movi_tl(cpu_pc, dest);
+}
+
static void generate_exception(DisasContext *ctx, int excp)
{
- tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+ gen_set_pc(ctx, ctx->base.pc_next);
gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
ctx->base.is_jmp = DISAS_NORETURN;
}
static void generate_exception_mtval(DisasContext *ctx, int excp)
{
- tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+ gen_set_pc(ctx, ctx->base.pc_next);
tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
ctx->base.is_jmp = DISAS_NORETURN;
@@ -179,10 +187,10 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
{
if (translator_use_goto_tb(&ctx->base, dest)) {
tcg_gen_goto_tb(n);
- tcg_gen_movi_tl(cpu_pc, dest);
+ gen_set_pc(ctx, dest);
tcg_gen_exit_tb(ctx->base.tb, n);
} else {
- tcg_gen_movi_tl(cpu_pc, dest);
+ gen_set_pc(ctx, dest);
tcg_gen_lookup_and_goto_ptr();
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 02/20] target/riscv: Sign extend pc for different XLEN
@ 2021-11-11 5:57 ` LIU Zhiwei
0 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Alistair.Francis, palmer, bin.meng, richard.henderson, LIU Zhiwei
When pc is written, it is sign-extended to fill the widest supported XLEN.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/translate.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 1d57bc97b5..a6a73ced9e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -150,16 +150,24 @@ static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
}
+static void gen_set_pc(DisasContext *ctx, target_ulong dest)
+{
+ if (get_xl(ctx) == MXL_RV32) {
+ dest = (int32_t)dest;
+ }
+ tcg_gen_movi_tl(cpu_pc, dest);
+}
+
static void generate_exception(DisasContext *ctx, int excp)
{
- tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+ gen_set_pc(ctx, ctx->base.pc_next);
gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
ctx->base.is_jmp = DISAS_NORETURN;
}
static void generate_exception_mtval(DisasContext *ctx, int excp)
{
- tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+ gen_set_pc(ctx, ctx->base.pc_next);
tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
ctx->base.is_jmp = DISAS_NORETURN;
@@ -179,10 +187,10 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
{
if (translator_use_goto_tb(&ctx->base, dest)) {
tcg_gen_goto_tb(n);
- tcg_gen_movi_tl(cpu_pc, dest);
+ gen_set_pc(ctx, dest);
tcg_gen_exit_tb(ctx->base.tb, n);
} else {
- tcg_gen_movi_tl(cpu_pc, dest);
+ gen_set_pc(ctx, dest);
tcg_gen_lookup_and_goto_ptr();
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 03/20] target/riscv: Ignore the pc bits above XLEN
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 5:57 ` LIU Zhiwei
-1 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, richard.henderson, bin.meng, Alistair.Francis, LIU Zhiwei
The read from PC for translation is in cpu_get_tb_cpu_state, before translation.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu_helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 9eeed38c7e..4c048cc266 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -70,8 +70,9 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *pflags)
{
uint32_t flags = 0;
+ RISCVMXL xl = cpu_get_xl(env);
- *pc = env->pc;
+ *pc = xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
*cs_base = 0;
if (riscv_has_ext(env, RVV)) {
@@ -127,7 +128,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
}
#endif
- flags = FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env));
+ flags = FIELD_DP32(flags, TB_FLAGS, XL, xl);
*pflags = flags;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 03/20] target/riscv: Ignore the pc bits above XLEN
@ 2021-11-11 5:57 ` LIU Zhiwei
0 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Alistair.Francis, palmer, bin.meng, richard.henderson, LIU Zhiwei
The read from PC for translation is in cpu_get_tb_cpu_state, before translation.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu_helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 9eeed38c7e..4c048cc266 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -70,8 +70,9 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *pflags)
{
uint32_t flags = 0;
+ RISCVMXL xl = cpu_get_xl(env);
- *pc = env->pc;
+ *pc = xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
*cs_base = 0;
if (riscv_has_ext(env, RVV)) {
@@ -127,7 +128,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
}
#endif
- flags = FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env));
+ flags = FIELD_DP32(flags, TB_FLAGS, XL, xl);
*pflags = flags;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 04/20] target/riscv: Extend pc for runtime pc write
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 5:57 ` LIU Zhiwei
-1 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, richard.henderson, bin.meng, Alistair.Francis, LIU Zhiwei
In some cases, we must restore the guest PC to the address of the start of
the TB, such as when the instruction counter hits zero. So extend pc register
according to current xlen for these cases.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/cpu.c | 22 +++++++++++++++++++---
target/riscv/cpu.h | 2 ++
target/riscv/cpu_helper.c | 2 +-
3 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f812998123..0d2d175fa2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -319,7 +319,12 @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
- env->pc = value;
+
+ if (cpu_get_xl(env) == MXL_RV32) {
+ env->pc = (int32_t)value;
+ } else {
+ env->pc = value;
+ }
}
static void riscv_cpu_synchronize_from_tb(CPUState *cs,
@@ -327,7 +332,13 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs,
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
- env->pc = tb->pc;
+ RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
+
+ if (xl == MXL_RV32) {
+ env->pc = (int32_t)tb->pc;
+ } else {
+ env->pc = tb->pc;
+ }
}
static bool riscv_cpu_has_work(CPUState *cs)
@@ -348,7 +359,12 @@ static bool riscv_cpu_has_work(CPUState *cs)
void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
target_ulong *data)
{
- env->pc = data[0];
+ RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
+ if (xl == MXL_RV32) {
+ env->pc = (int32_t)data[0];
+ } else {
+ env->pc = data[0];
+ }
}
static void riscv_cpu_reset(DeviceState *dev)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0760c0af93..8befff0166 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -420,6 +420,8 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
}
#endif
+RISCVMXL cpu_get_xl(CPURISCVState *env);
+
/*
* A simplification for VLMAX
* = (1 << LMUL) * VLEN / (8 * (1 << SEW))
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 4c048cc266..79aba9c880 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -35,7 +35,7 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
#endif
}
-static RISCVMXL cpu_get_xl(CPURISCVState *env)
+RISCVMXL cpu_get_xl(CPURISCVState *env)
{
#if defined(TARGET_RISCV32)
return MXL_RV32;
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 04/20] target/riscv: Extend pc for runtime pc write
@ 2021-11-11 5:57 ` LIU Zhiwei
0 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Alistair.Francis, palmer, bin.meng, richard.henderson, LIU Zhiwei
In some cases, we must restore the guest PC to the address of the start of
the TB, such as when the instruction counter hits zero. So extend pc register
according to current xlen for these cases.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/cpu.c | 22 +++++++++++++++++++---
target/riscv/cpu.h | 2 ++
target/riscv/cpu_helper.c | 2 +-
3 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f812998123..0d2d175fa2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -319,7 +319,12 @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
- env->pc = value;
+
+ if (cpu_get_xl(env) == MXL_RV32) {
+ env->pc = (int32_t)value;
+ } else {
+ env->pc = value;
+ }
}
static void riscv_cpu_synchronize_from_tb(CPUState *cs,
@@ -327,7 +332,13 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs,
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
- env->pc = tb->pc;
+ RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
+
+ if (xl == MXL_RV32) {
+ env->pc = (int32_t)tb->pc;
+ } else {
+ env->pc = tb->pc;
+ }
}
static bool riscv_cpu_has_work(CPUState *cs)
@@ -348,7 +359,12 @@ static bool riscv_cpu_has_work(CPUState *cs)
void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
target_ulong *data)
{
- env->pc = data[0];
+ RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
+ if (xl == MXL_RV32) {
+ env->pc = (int32_t)data[0];
+ } else {
+ env->pc = data[0];
+ }
}
static void riscv_cpu_reset(DeviceState *dev)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0760c0af93..8befff0166 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -420,6 +420,8 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
}
#endif
+RISCVMXL cpu_get_xl(CPURISCVState *env);
+
/*
* A simplification for VLMAX
* = (1 << LMUL) * VLEN / (8 * (1 << SEW))
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 4c048cc266..79aba9c880 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -35,7 +35,7 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
#endif
}
-static RISCVMXL cpu_get_xl(CPURISCVState *env)
+RISCVMXL cpu_get_xl(CPURISCVState *env)
{
#if defined(TARGET_RISCV32)
return MXL_RV32;
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 05/20] target/riscv: Use gdb xml according to max mxlen
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 5:57 ` LIU Zhiwei
-1 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, richard.henderson, bin.meng, Alistair.Francis, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/gdbstub.c | 71 +++++++++++++++++++++++++++++++-----------
1 file changed, 52 insertions(+), 19 deletions(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 23429179e2..8d0f9139d7 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -24,11 +24,23 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
+ target_ulong tmp;
if (n < 32) {
- return gdb_get_regl(mem_buf, env->gpr[n]);
+ tmp = env->gpr[n];
} else if (n == 32) {
- return gdb_get_regl(mem_buf, env->pc);
+ tmp = env->pc;
+ } else {
+ return 0;
+ }
+
+ switch (env->misa_mxl_max) {
+ case MXL_RV32:
+ return gdb_get_reg32(mem_buf, tmp);
+ case MXL_RV64:
+ return gdb_get_reg64(mem_buf, tmp);
+ default:
+ g_assert_not_reached();
}
return 0;
}
@@ -37,18 +49,32 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
-
- if (n == 0) {
- /* discard writes to x0 */
- return sizeof(target_ulong);
- } else if (n < 32) {
- env->gpr[n] = ldtul_p(mem_buf);
- return sizeof(target_ulong);
+ int length = 0;
+ target_ulong tmp;
+
+ switch (env->misa_mxl_max) {
+ case MXL_RV32:
+ tmp = (int32_t)ldl_p(mem_buf);
+ length = 4;
+ break;
+ case MXL_RV64:
+ if (cpu_get_xl(env) < MXL_RV64) {
+ tmp = (int32_t)ldq_p(mem_buf);
+ } else {
+ tmp = ldq_p(mem_buf);
+ }
+ length = 8;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ if (n > 0 && n < 32) {
+ env->gpr[n] = tmp;
} else if (n == 32) {
- env->pc = ldtul_p(mem_buf);
- return sizeof(target_ulong);
+ env->pc = tmp;
}
- return 0;
+
+ return length;
}
static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
@@ -198,13 +224,20 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
36, "riscv-32bit-fpu.xml", 0);
}
-#if defined(TARGET_RISCV32)
- gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
- 1, "riscv-32bit-virtual.xml", 0);
-#elif defined(TARGET_RISCV64)
- gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
- 1, "riscv-64bit-virtual.xml", 0);
-#endif
+ switch (env->misa_mxl_max) {
+ case MXL_RV32:
+ gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
+ riscv_gdb_set_virtual,
+ 1, "riscv-32bit-virtual.xml", 0);
+ break;
+ case MXL_RV64:
+ gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
+ riscv_gdb_set_virtual,
+ 1, "riscv-64bit-virtual.xml", 0);
+ break;
+ default:
+ g_assert_not_reached();
+ }
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
riscv_gen_dynamic_csr_xml(cs, cs->gdb_num_regs),
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 05/20] target/riscv: Use gdb xml according to max mxlen
@ 2021-11-11 5:57 ` LIU Zhiwei
0 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Alistair.Francis, palmer, bin.meng, richard.henderson, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/gdbstub.c | 71 +++++++++++++++++++++++++++++++-----------
1 file changed, 52 insertions(+), 19 deletions(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 23429179e2..8d0f9139d7 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -24,11 +24,23 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
+ target_ulong tmp;
if (n < 32) {
- return gdb_get_regl(mem_buf, env->gpr[n]);
+ tmp = env->gpr[n];
} else if (n == 32) {
- return gdb_get_regl(mem_buf, env->pc);
+ tmp = env->pc;
+ } else {
+ return 0;
+ }
+
+ switch (env->misa_mxl_max) {
+ case MXL_RV32:
+ return gdb_get_reg32(mem_buf, tmp);
+ case MXL_RV64:
+ return gdb_get_reg64(mem_buf, tmp);
+ default:
+ g_assert_not_reached();
}
return 0;
}
@@ -37,18 +49,32 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
-
- if (n == 0) {
- /* discard writes to x0 */
- return sizeof(target_ulong);
- } else if (n < 32) {
- env->gpr[n] = ldtul_p(mem_buf);
- return sizeof(target_ulong);
+ int length = 0;
+ target_ulong tmp;
+
+ switch (env->misa_mxl_max) {
+ case MXL_RV32:
+ tmp = (int32_t)ldl_p(mem_buf);
+ length = 4;
+ break;
+ case MXL_RV64:
+ if (cpu_get_xl(env) < MXL_RV64) {
+ tmp = (int32_t)ldq_p(mem_buf);
+ } else {
+ tmp = ldq_p(mem_buf);
+ }
+ length = 8;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ if (n > 0 && n < 32) {
+ env->gpr[n] = tmp;
} else if (n == 32) {
- env->pc = ldtul_p(mem_buf);
- return sizeof(target_ulong);
+ env->pc = tmp;
}
- return 0;
+
+ return length;
}
static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
@@ -198,13 +224,20 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
36, "riscv-32bit-fpu.xml", 0);
}
-#if defined(TARGET_RISCV32)
- gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
- 1, "riscv-32bit-virtual.xml", 0);
-#elif defined(TARGET_RISCV64)
- gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
- 1, "riscv-64bit-virtual.xml", 0);
-#endif
+ switch (env->misa_mxl_max) {
+ case MXL_RV32:
+ gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
+ riscv_gdb_set_virtual,
+ 1, "riscv-32bit-virtual.xml", 0);
+ break;
+ case MXL_RV64:
+ gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
+ riscv_gdb_set_virtual,
+ 1, "riscv-64bit-virtual.xml", 0);
+ break;
+ default:
+ g_assert_not_reached();
+ }
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
riscv_gen_dynamic_csr_xml(cs, cs->gdb_num_regs),
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 06/20] target/riscv: Relax debug check for pm write
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 5:57 ` LIU Zhiwei
-1 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, richard.henderson, bin.meng, Alistair.Francis, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/csr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9f41954894..74c0b788fd 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1445,6 +1445,9 @@ static bool check_pm_current_disabled(CPURISCVState *env, int csrno)
int csr_priv = get_field(csrno, 0x300);
int pm_current;
+ if (env->debugger) {
+ return false;
+ }
/*
* If priv lvls differ that means we're accessing csr from higher priv lvl,
* so allow the access
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 06/20] target/riscv: Relax debug check for pm write
@ 2021-11-11 5:57 ` LIU Zhiwei
0 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Alistair.Francis, palmer, bin.meng, richard.henderson, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/csr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9f41954894..74c0b788fd 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1445,6 +1445,9 @@ static bool check_pm_current_disabled(CPURISCVState *env, int csrno)
int csr_priv = get_field(csrno, 0x300);
int pm_current;
+ if (env->debugger) {
+ return false;
+ }
/*
* If priv lvls differ that means we're accessing csr from higher priv lvl,
* so allow the access
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 07/20] target/riscv: Adjust csr write mask with XLEN
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 5:57 ` LIU Zhiwei
-1 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, richard.henderson, bin.meng, Alistair.Francis, LIU Zhiwei
Write mask is representing the bits we care about.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
target/riscv/op_helper.c | 3 ++-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index e51dbc41c5..40c81421f2 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -486,7 +486,7 @@ static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
return do_csrw(ctx, a->csr, src);
}
- TCGv mask = tcg_constant_tl(-1);
+ TCGv mask = tcg_constant_tl(get_xl(ctx) == MXL_RV32 ? UINT32_MAX : -1);
return do_csrrw(ctx, a->rd, a->csr, src, mask);
}
@@ -537,7 +537,7 @@ static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
return do_csrw(ctx, a->csr, src);
}
- TCGv mask = tcg_constant_tl(-1);
+ TCGv mask = tcg_constant_tl(get_xl(ctx) == MXL_RV32 ? UINT32_MAX : -1);
return do_csrrw(ctx, a->rd, a->csr, src, mask);
}
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 095d39671b..561e156bec 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -50,7 +50,8 @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
void helper_csrw(CPURISCVState *env, int csr, target_ulong src)
{
- RISCVException ret = riscv_csrrw(env, csr, NULL, src, -1);
+ target_ulong mask = cpu_get_xl(env) == MXL_RV32 ? UINT32_MAX : -1;
+ RISCVException ret = riscv_csrrw(env, csr, NULL, src, mask);
if (ret != RISCV_EXCP_NONE) {
riscv_raise_exception(env, ret, GETPC());
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 07/20] target/riscv: Adjust csr write mask with XLEN
@ 2021-11-11 5:57 ` LIU Zhiwei
0 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Alistair.Francis, palmer, bin.meng, richard.henderson, LIU Zhiwei
Write mask is representing the bits we care about.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
target/riscv/op_helper.c | 3 ++-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index e51dbc41c5..40c81421f2 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -486,7 +486,7 @@ static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
return do_csrw(ctx, a->csr, src);
}
- TCGv mask = tcg_constant_tl(-1);
+ TCGv mask = tcg_constant_tl(get_xl(ctx) == MXL_RV32 ? UINT32_MAX : -1);
return do_csrrw(ctx, a->rd, a->csr, src, mask);
}
@@ -537,7 +537,7 @@ static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
return do_csrw(ctx, a->csr, src);
}
- TCGv mask = tcg_constant_tl(-1);
+ TCGv mask = tcg_constant_tl(get_xl(ctx) == MXL_RV32 ? UINT32_MAX : -1);
return do_csrrw(ctx, a->rd, a->csr, src, mask);
}
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 095d39671b..561e156bec 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -50,7 +50,8 @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
void helper_csrw(CPURISCVState *env, int csr, target_ulong src)
{
- RISCVException ret = riscv_csrrw(env, csr, NULL, src, -1);
+ target_ulong mask = cpu_get_xl(env) == MXL_RV32 ? UINT32_MAX : -1;
+ RISCVException ret = riscv_csrrw(env, csr, NULL, src, mask);
if (ret != RISCV_EXCP_NONE) {
riscv_raise_exception(env, ret, GETPC());
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 08/20] target/riscv: Create current pm fields in env
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 5:57 ` LIU Zhiwei
-1 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, richard.henderson, bin.meng, Alistair.Francis, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 4 ++++
target/riscv/cpu_helper.c | 43 +++++++++++++++++++++++++++++++++++++++
target/riscv/csr.c | 19 +++++++++++++++++
target/riscv/machine.c | 10 +++++++++
5 files changed, 77 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0d2d175fa2..886388f066 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -378,6 +378,7 @@ static void riscv_cpu_reset(DeviceState *dev)
#ifndef CONFIG_USER_ONLY
env->misa_mxl = env->misa_mxl_max;
env->priv = PRV_M;
+ riscv_cpu_update_mask(env);
env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
if (env->misa_mxl > MXL_RV32) {
/*
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 8befff0166..fa5a6ba1c8 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -250,6 +250,8 @@ struct CPURISCVState {
target_ulong upmmask;
target_ulong upmbase;
#endif
+ target_ulong cur_pmmask;
+ target_ulong cur_pmbase;
float_status fp_status;
@@ -441,6 +443,8 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *pflags);
+void riscv_cpu_update_mask(CPURISCVState *env);
+
RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 79aba9c880..8320f56d9f 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -133,6 +133,48 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
*pflags = flags;
}
+void riscv_cpu_update_mask(CPURISCVState *env)
+{
+ target_ulong mask = -1, base = 0;
+ /*
+ * TODO: Current RVJ spec does not specify
+ * how the extension interacts with XLEN.
+ */
+#ifndef CONFIG_USER_ONLY
+ if (riscv_has_ext(env, RVJ)) {
+ switch (env->priv) {
+ case PRV_M:
+ if (env->mmte & M_PM_ENABLE) {
+ mask = env->mpmmask;
+ base = env->mpmbase;
+ }
+ break;
+ case PRV_S:
+ if (env->mmte & S_PM_ENABLE) {
+ mask = env->spmmask;
+ base = env->spmbase;
+ }
+ break;
+ case PRV_U:
+ if (env->mmte & U_PM_ENABLE) {
+ mask = env->upmmask;
+ base = env->upmbase;
+ }
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ }
+#endif
+ if (cpu_get_xl(env) == MXL_RV32) {
+ env->cur_pmmask = mask & UINT32_MAX;
+ env->cur_pmbase = base & UINT32_MAX;
+ } else {
+ env->cur_pmmask = mask;
+ env->cur_pmbase = base;
+ }
+}
+
#ifndef CONFIG_USER_ONLY
static int riscv_cpu_local_irq_pending(CPURISCVState *env)
{
@@ -331,6 +373,7 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
}
/* tlb_flush is unnecessary as mode is contained in mmu_idx */
env->priv = newpriv;
+ riscv_cpu_update_mask(env);
/*
* Clear the load reservation - otherwise a reservation placed in one
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 74c0b788fd..6bb2d09519 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1496,6 +1496,7 @@ static RISCVException write_mmte(CPURISCVState *env, int csrno,
/* hardwiring pm.instruction bit to 0, since it's not supported yet */
wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
env->mmte = wpri_val | PM_EXT_DIRTY;
+ riscv_cpu_update_mask(env);
/* Set XS and SD bits, since PM CSRs are dirty */
mstatus = env->mstatus | MSTATUS_XS;
@@ -1571,6 +1572,9 @@ static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
uint64_t mstatus;
env->mpmmask = val;
+ if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
+ env->cur_pmmask = val;
+ }
env->mmte |= PM_EXT_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
@@ -1596,6 +1600,9 @@ static RISCVException write_spmmask(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
env->spmmask = val;
+ if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
+ env->cur_pmmask = val;
+ }
env->mmte |= PM_EXT_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
@@ -1621,6 +1628,9 @@ static RISCVException write_upmmask(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
env->upmmask = val;
+ if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
+ env->cur_pmmask = val;
+ }
env->mmte |= PM_EXT_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
@@ -1642,6 +1652,9 @@ static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
uint64_t mstatus;
env->mpmbase = val;
+ if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
+ env->cur_pmbase = val;
+ }
env->mmte |= PM_EXT_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
@@ -1667,6 +1680,9 @@ static RISCVException write_spmbase(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
env->spmbase = val;
+ if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
+ env->cur_pmbase = val;
+ }
env->mmte |= PM_EXT_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
@@ -1692,6 +1708,9 @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
env->upmbase = val;
+ if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
+ env->cur_pmbase = val;
+ }
env->mmte |= PM_EXT_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 7b4c739564..19e982d3f0 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -164,10 +164,20 @@ static const VMStateDescription vmstate_hyper = {
}
};
+static int riscv_cpu_post_load(void *opaque, int version_id)
+{
+ RISCVCPU *cpu = opaque;
+ CPURISCVState *env = &cpu->env;
+
+ riscv_cpu_update_mask(env);
+ return 0;
+}
+
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
.version_id = 3,
.minimum_version_id = 3,
+ .post_load = riscv_cpu_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 08/20] target/riscv: Create current pm fields in env
@ 2021-11-11 5:57 ` LIU Zhiwei
0 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Alistair.Francis, palmer, bin.meng, richard.henderson, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 4 ++++
target/riscv/cpu_helper.c | 43 +++++++++++++++++++++++++++++++++++++++
target/riscv/csr.c | 19 +++++++++++++++++
target/riscv/machine.c | 10 +++++++++
5 files changed, 77 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0d2d175fa2..886388f066 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -378,6 +378,7 @@ static void riscv_cpu_reset(DeviceState *dev)
#ifndef CONFIG_USER_ONLY
env->misa_mxl = env->misa_mxl_max;
env->priv = PRV_M;
+ riscv_cpu_update_mask(env);
env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
if (env->misa_mxl > MXL_RV32) {
/*
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 8befff0166..fa5a6ba1c8 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -250,6 +250,8 @@ struct CPURISCVState {
target_ulong upmmask;
target_ulong upmbase;
#endif
+ target_ulong cur_pmmask;
+ target_ulong cur_pmbase;
float_status fp_status;
@@ -441,6 +443,8 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *pflags);
+void riscv_cpu_update_mask(CPURISCVState *env);
+
RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 79aba9c880..8320f56d9f 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -133,6 +133,48 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
*pflags = flags;
}
+void riscv_cpu_update_mask(CPURISCVState *env)
+{
+ target_ulong mask = -1, base = 0;
+ /*
+ * TODO: Current RVJ spec does not specify
+ * how the extension interacts with XLEN.
+ */
+#ifndef CONFIG_USER_ONLY
+ if (riscv_has_ext(env, RVJ)) {
+ switch (env->priv) {
+ case PRV_M:
+ if (env->mmte & M_PM_ENABLE) {
+ mask = env->mpmmask;
+ base = env->mpmbase;
+ }
+ break;
+ case PRV_S:
+ if (env->mmte & S_PM_ENABLE) {
+ mask = env->spmmask;
+ base = env->spmbase;
+ }
+ break;
+ case PRV_U:
+ if (env->mmte & U_PM_ENABLE) {
+ mask = env->upmmask;
+ base = env->upmbase;
+ }
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ }
+#endif
+ if (cpu_get_xl(env) == MXL_RV32) {
+ env->cur_pmmask = mask & UINT32_MAX;
+ env->cur_pmbase = base & UINT32_MAX;
+ } else {
+ env->cur_pmmask = mask;
+ env->cur_pmbase = base;
+ }
+}
+
#ifndef CONFIG_USER_ONLY
static int riscv_cpu_local_irq_pending(CPURISCVState *env)
{
@@ -331,6 +373,7 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
}
/* tlb_flush is unnecessary as mode is contained in mmu_idx */
env->priv = newpriv;
+ riscv_cpu_update_mask(env);
/*
* Clear the load reservation - otherwise a reservation placed in one
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 74c0b788fd..6bb2d09519 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1496,6 +1496,7 @@ static RISCVException write_mmte(CPURISCVState *env, int csrno,
/* hardwiring pm.instruction bit to 0, since it's not supported yet */
wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
env->mmte = wpri_val | PM_EXT_DIRTY;
+ riscv_cpu_update_mask(env);
/* Set XS and SD bits, since PM CSRs are dirty */
mstatus = env->mstatus | MSTATUS_XS;
@@ -1571,6 +1572,9 @@ static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
uint64_t mstatus;
env->mpmmask = val;
+ if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
+ env->cur_pmmask = val;
+ }
env->mmte |= PM_EXT_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
@@ -1596,6 +1600,9 @@ static RISCVException write_spmmask(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
env->spmmask = val;
+ if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
+ env->cur_pmmask = val;
+ }
env->mmte |= PM_EXT_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
@@ -1621,6 +1628,9 @@ static RISCVException write_upmmask(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
env->upmmask = val;
+ if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
+ env->cur_pmmask = val;
+ }
env->mmte |= PM_EXT_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
@@ -1642,6 +1652,9 @@ static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
uint64_t mstatus;
env->mpmbase = val;
+ if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
+ env->cur_pmbase = val;
+ }
env->mmte |= PM_EXT_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
@@ -1667,6 +1680,9 @@ static RISCVException write_spmbase(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
env->spmbase = val;
+ if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
+ env->cur_pmbase = val;
+ }
env->mmte |= PM_EXT_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
@@ -1692,6 +1708,9 @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
env->upmbase = val;
+ if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
+ env->cur_pmbase = val;
+ }
env->mmte |= PM_EXT_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 7b4c739564..19e982d3f0 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -164,10 +164,20 @@ static const VMStateDescription vmstate_hyper = {
}
};
+static int riscv_cpu_post_load(void *opaque, int version_id)
+{
+ RISCVCPU *cpu = opaque;
+ CPURISCVState *env = &cpu->env;
+
+ riscv_cpu_update_mask(env);
+ return 0;
+}
+
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
.version_id = 3,
.minimum_version_id = 3,
+ .post_load = riscv_cpu_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 09/20] target/riscv: Alloc tcg global for cur_pm[mask|base]
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 5:57 ` LIU Zhiwei
-1 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, richard.henderson, bin.meng, Alistair.Francis, LIU Zhiwei
Replace the array of pm_mask/pm_base with scalar variables.
Remove the cached array value in DisasContext.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/translate.c | 32 ++++++++------------------------
1 file changed, 8 insertions(+), 24 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index a6a73ced9e..6cb74c6355 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -37,8 +37,8 @@ static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
static TCGv load_res;
static TCGv load_val;
/* globals for PM CSRs */
-static TCGv pm_mask[4];
-static TCGv pm_base[4];
+static TCGv pm_mask;
+static TCGv pm_base;
#include "exec/gen-icount.h"
@@ -88,8 +88,6 @@ typedef struct DisasContext {
TCGv temp[4];
/* PointerMasking extension */
bool pm_enabled;
- TCGv pm_mask;
- TCGv pm_base;
} DisasContext;
static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -297,8 +295,8 @@ static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src)
return src;
} else {
temp = temp_new(s);
- tcg_gen_andc_tl(temp, src, s->pm_mask);
- tcg_gen_or_tl(temp, temp, s->pm_base);
+ tcg_gen_andc_tl(temp, src, pm_mask);
+ tcg_gen_or_tl(temp, temp, pm_base);
return temp;
}
}
@@ -647,10 +645,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->ntemp = 0;
memset(ctx->temp, 0, sizeof(ctx->temp));
ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
- int priv = tb_flags & TB_FLAGS_PRIV_MMU_MASK;
- ctx->pm_mask = pm_mask[priv];
- ctx->pm_base = pm_base[priv];
-
ctx->zero = tcg_constant_tl(0);
}
@@ -763,19 +757,9 @@ void riscv_translate_init(void)
"load_res");
load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
"load_val");
-#ifndef CONFIG_USER_ONLY
/* Assign PM CSRs to tcg globals */
- pm_mask[PRV_U] =
- tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask");
- pm_base[PRV_U] =
- tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase");
- pm_mask[PRV_S] =
- tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask");
- pm_base[PRV_S] =
- tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase");
- pm_mask[PRV_M] =
- tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask");
- pm_base[PRV_M] =
- tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase");
-#endif
+ pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask),
+ "pmmask");
+ pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase),
+ "pmbase");
}
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 09/20] target/riscv: Alloc tcg global for cur_pm[mask|base]
@ 2021-11-11 5:57 ` LIU Zhiwei
0 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Alistair.Francis, palmer, bin.meng, richard.henderson, LIU Zhiwei
Replace the array of pm_mask/pm_base with scalar variables.
Remove the cached array value in DisasContext.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/translate.c | 32 ++++++++------------------------
1 file changed, 8 insertions(+), 24 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index a6a73ced9e..6cb74c6355 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -37,8 +37,8 @@ static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
static TCGv load_res;
static TCGv load_val;
/* globals for PM CSRs */
-static TCGv pm_mask[4];
-static TCGv pm_base[4];
+static TCGv pm_mask;
+static TCGv pm_base;
#include "exec/gen-icount.h"
@@ -88,8 +88,6 @@ typedef struct DisasContext {
TCGv temp[4];
/* PointerMasking extension */
bool pm_enabled;
- TCGv pm_mask;
- TCGv pm_base;
} DisasContext;
static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -297,8 +295,8 @@ static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src)
return src;
} else {
temp = temp_new(s);
- tcg_gen_andc_tl(temp, src, s->pm_mask);
- tcg_gen_or_tl(temp, temp, s->pm_base);
+ tcg_gen_andc_tl(temp, src, pm_mask);
+ tcg_gen_or_tl(temp, temp, pm_base);
return temp;
}
}
@@ -647,10 +645,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->ntemp = 0;
memset(ctx->temp, 0, sizeof(ctx->temp));
ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
- int priv = tb_flags & TB_FLAGS_PRIV_MMU_MASK;
- ctx->pm_mask = pm_mask[priv];
- ctx->pm_base = pm_base[priv];
-
ctx->zero = tcg_constant_tl(0);
}
@@ -763,19 +757,9 @@ void riscv_translate_init(void)
"load_res");
load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
"load_val");
-#ifndef CONFIG_USER_ONLY
/* Assign PM CSRs to tcg globals */
- pm_mask[PRV_U] =
- tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask");
- pm_base[PRV_U] =
- tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase");
- pm_mask[PRV_S] =
- tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask");
- pm_base[PRV_S] =
- tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase");
- pm_mask[PRV_M] =
- tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask");
- pm_base[PRV_M] =
- tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase");
-#endif
+ pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask),
+ "pmmask");
+ pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase),
+ "pmbase");
}
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 10/20] target/riscv: Calculate address according to XLEN
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 5:57 ` LIU Zhiwei
-1 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, richard.henderson, bin.meng, Alistair.Francis, LIU Zhiwei
Define one common function to compute a canonical address from a register
plus offset. Merge gen_pm_adjust_address into this function.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/insn_trans/trans_rva.c.inc | 9 +++------
target/riscv/insn_trans/trans_rvd.c.inc | 19 ++---------------
target/riscv/insn_trans/trans_rvf.c.inc | 19 ++---------------
target/riscv/insn_trans/trans_rvi.c.inc | 18 ++---------------
target/riscv/translate.c | 27 ++++++++++++-------------
5 files changed, 22 insertions(+), 70 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
index 40fe132b04..1f64b8d332 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -20,12 +20,11 @@
static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
{
- TCGv src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
+ TCGv src1 = get_address(ctx, a->rs1, 0);
if (a->rl) {
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
}
- src1 = gen_pm_adjust_address(ctx, src1);
tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
if (a->aq) {
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
@@ -44,8 +43,7 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
TCGLabel *l1 = gen_new_label();
TCGLabel *l2 = gen_new_label();
- src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
- src1 = gen_pm_adjust_address(ctx, src1);
+ src1 = get_address(ctx, a->rs1, 0);
tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
/*
@@ -83,10 +81,9 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
MemOp mop)
{
TCGv dest = dest_gpr(ctx, a->rd);
- TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src1 = get_address(ctx, a->rs1, 0);
TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
- src1 = gen_pm_adjust_address(ctx, src1);
func(dest, src1, src2, ctx->mem_idx, mop);
gen_set_gpr(ctx, a->rd, dest);
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
index 64fb0046f7..88a491375c 100644
--- a/target/riscv/insn_trans/trans_rvd.c.inc
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -25,14 +25,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
- addr = get_gpr(ctx, a->rs1, EXT_NONE);
- if (a->imm) {
- TCGv temp = temp_new(ctx);
- tcg_gen_addi_tl(temp, addr, a->imm);
- addr = temp;
- }
- addr = gen_pm_adjust_address(ctx, addr);
-
+ addr = get_address(ctx, a->rs1, a->imm);
tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEQ);
mark_fs_dirty(ctx);
@@ -46,16 +39,8 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
- addr = get_gpr(ctx, a->rs1, EXT_NONE);
- if (a->imm) {
- TCGv temp = temp_new(ctx);
- tcg_gen_addi_tl(temp, addr, a->imm);
- addr = temp;
- }
- addr = gen_pm_adjust_address(ctx, addr);
-
+ addr = get_address(ctx, a->rs1, a->imm);
tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEQ);
-
return true;
}
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
index b5459249c4..0aac87f7db 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -31,14 +31,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
- addr = get_gpr(ctx, a->rs1, EXT_NONE);
- if (a->imm) {
- TCGv temp = temp_new(ctx);
- tcg_gen_addi_tl(temp, addr, a->imm);
- addr = temp;
- }
- addr = gen_pm_adjust_address(ctx, addr);
-
+ addr = get_address(ctx, a->rs1, a->imm);
dest = cpu_fpr[a->rd];
tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL);
gen_nanbox_s(dest, dest);
@@ -54,16 +47,8 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
- addr = get_gpr(ctx, a->rs1, EXT_NONE);
- if (a->imm) {
- TCGv temp = tcg_temp_new();
- tcg_gen_addi_tl(temp, addr, a->imm);
- addr = temp;
- }
- addr = gen_pm_adjust_address(ctx, addr);
-
+ addr = get_address(ctx, a->rs1, a->imm);
tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL);
-
return true;
}
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 40c81421f2..cb73a2f1ee 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -137,14 +137,7 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
{
TCGv dest = dest_gpr(ctx, a->rd);
- TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
-
- if (a->imm) {
- TCGv temp = temp_new(ctx);
- tcg_gen_addi_tl(temp, addr, a->imm);
- addr = temp;
- }
- addr = gen_pm_adjust_address(ctx, addr);
+ TCGv addr = get_address(ctx, a->rs1, a->imm);
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
gen_set_gpr(ctx, a->rd, dest);
@@ -178,16 +171,9 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
{
- TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv addr = get_address(ctx, a->rs1, a->imm);
TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
- if (a->imm) {
- TCGv temp = temp_new(ctx);
- tcg_gen_addi_tl(temp, addr, a->imm);
- addr = temp;
- }
- addr = gen_pm_adjust_address(ctx, addr);
-
tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
return true;
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 6cb74c6355..fd75f7c4bc 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -284,21 +284,20 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
ctx->base.is_jmp = DISAS_NORETURN;
}
-/*
- * Generates address adjustment for PointerMasking
- */
-static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src)
-{
- TCGv temp;
- if (!s->pm_enabled) {
- /* Load unmodified address */
- return src;
- } else {
- temp = temp_new(s);
- tcg_gen_andc_tl(temp, src, pm_mask);
- tcg_gen_or_tl(temp, temp, pm_base);
- return temp;
+/* Compute a canonical address from a register plus offset. */
+static TCGv get_address(DisasContext *ctx, int rs1, int imm)
+{
+ TCGv addr = temp_new(ctx);
+ TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
+
+ tcg_gen_addi_tl(addr, src1, imm);
+ if (ctx->pm_enabled) {
+ tcg_gen_and_tl(addr, addr, pm_mask);
+ tcg_gen_or_tl(addr, addr, pm_base);
+ } else if (get_xl(ctx) == MXL_RV32) {
+ tcg_gen_ext32u_tl(addr, addr);
}
+ return addr;
}
#ifndef CONFIG_USER_ONLY
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 10/20] target/riscv: Calculate address according to XLEN
@ 2021-11-11 5:57 ` LIU Zhiwei
0 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Alistair.Francis, palmer, bin.meng, richard.henderson, LIU Zhiwei
Define one common function to compute a canonical address from a register
plus offset. Merge gen_pm_adjust_address into this function.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/insn_trans/trans_rva.c.inc | 9 +++------
target/riscv/insn_trans/trans_rvd.c.inc | 19 ++---------------
target/riscv/insn_trans/trans_rvf.c.inc | 19 ++---------------
target/riscv/insn_trans/trans_rvi.c.inc | 18 ++---------------
target/riscv/translate.c | 27 ++++++++++++-------------
5 files changed, 22 insertions(+), 70 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
index 40fe132b04..1f64b8d332 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -20,12 +20,11 @@
static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
{
- TCGv src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
+ TCGv src1 = get_address(ctx, a->rs1, 0);
if (a->rl) {
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
}
- src1 = gen_pm_adjust_address(ctx, src1);
tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
if (a->aq) {
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
@@ -44,8 +43,7 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
TCGLabel *l1 = gen_new_label();
TCGLabel *l2 = gen_new_label();
- src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
- src1 = gen_pm_adjust_address(ctx, src1);
+ src1 = get_address(ctx, a->rs1, 0);
tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
/*
@@ -83,10 +81,9 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
MemOp mop)
{
TCGv dest = dest_gpr(ctx, a->rd);
- TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src1 = get_address(ctx, a->rs1, 0);
TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
- src1 = gen_pm_adjust_address(ctx, src1);
func(dest, src1, src2, ctx->mem_idx, mop);
gen_set_gpr(ctx, a->rd, dest);
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
index 64fb0046f7..88a491375c 100644
--- a/target/riscv/insn_trans/trans_rvd.c.inc
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -25,14 +25,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
- addr = get_gpr(ctx, a->rs1, EXT_NONE);
- if (a->imm) {
- TCGv temp = temp_new(ctx);
- tcg_gen_addi_tl(temp, addr, a->imm);
- addr = temp;
- }
- addr = gen_pm_adjust_address(ctx, addr);
-
+ addr = get_address(ctx, a->rs1, a->imm);
tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEQ);
mark_fs_dirty(ctx);
@@ -46,16 +39,8 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
- addr = get_gpr(ctx, a->rs1, EXT_NONE);
- if (a->imm) {
- TCGv temp = temp_new(ctx);
- tcg_gen_addi_tl(temp, addr, a->imm);
- addr = temp;
- }
- addr = gen_pm_adjust_address(ctx, addr);
-
+ addr = get_address(ctx, a->rs1, a->imm);
tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEQ);
-
return true;
}
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
index b5459249c4..0aac87f7db 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -31,14 +31,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
- addr = get_gpr(ctx, a->rs1, EXT_NONE);
- if (a->imm) {
- TCGv temp = temp_new(ctx);
- tcg_gen_addi_tl(temp, addr, a->imm);
- addr = temp;
- }
- addr = gen_pm_adjust_address(ctx, addr);
-
+ addr = get_address(ctx, a->rs1, a->imm);
dest = cpu_fpr[a->rd];
tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL);
gen_nanbox_s(dest, dest);
@@ -54,16 +47,8 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
- addr = get_gpr(ctx, a->rs1, EXT_NONE);
- if (a->imm) {
- TCGv temp = tcg_temp_new();
- tcg_gen_addi_tl(temp, addr, a->imm);
- addr = temp;
- }
- addr = gen_pm_adjust_address(ctx, addr);
-
+ addr = get_address(ctx, a->rs1, a->imm);
tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL);
-
return true;
}
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 40c81421f2..cb73a2f1ee 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -137,14 +137,7 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
{
TCGv dest = dest_gpr(ctx, a->rd);
- TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
-
- if (a->imm) {
- TCGv temp = temp_new(ctx);
- tcg_gen_addi_tl(temp, addr, a->imm);
- addr = temp;
- }
- addr = gen_pm_adjust_address(ctx, addr);
+ TCGv addr = get_address(ctx, a->rs1, a->imm);
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
gen_set_gpr(ctx, a->rd, dest);
@@ -178,16 +171,9 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
{
- TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv addr = get_address(ctx, a->rs1, a->imm);
TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
- if (a->imm) {
- TCGv temp = temp_new(ctx);
- tcg_gen_addi_tl(temp, addr, a->imm);
- addr = temp;
- }
- addr = gen_pm_adjust_address(ctx, addr);
-
tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
return true;
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 6cb74c6355..fd75f7c4bc 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -284,21 +284,20 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
ctx->base.is_jmp = DISAS_NORETURN;
}
-/*
- * Generates address adjustment for PointerMasking
- */
-static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src)
-{
- TCGv temp;
- if (!s->pm_enabled) {
- /* Load unmodified address */
- return src;
- } else {
- temp = temp_new(s);
- tcg_gen_andc_tl(temp, src, pm_mask);
- tcg_gen_or_tl(temp, temp, pm_base);
- return temp;
+/* Compute a canonical address from a register plus offset. */
+static TCGv get_address(DisasContext *ctx, int rs1, int imm)
+{
+ TCGv addr = temp_new(ctx);
+ TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
+
+ tcg_gen_addi_tl(addr, src1, imm);
+ if (ctx->pm_enabled) {
+ tcg_gen_and_tl(addr, addr, pm_mask);
+ tcg_gen_or_tl(addr, addr, pm_base);
+ } else if (get_xl(ctx) == MXL_RV32) {
+ tcg_gen_ext32u_tl(addr, addr);
}
+ return addr;
}
#ifndef CONFIG_USER_ONLY
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 11/20] target/riscv: Split pm_enabled into mask and base
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 5:57 ` LIU Zhiwei
-1 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, richard.henderson, bin.meng, Alistair.Francis, LIU Zhiwei
Use cached cur_pmmask and cur_pmbase to infer the
current PM mode.
This may decrease the TCG IR by one when pm_enabled
is true and pm_base_enabled is false.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/cpu.h | 3 ++-
target/riscv/cpu_helper.c | 25 +++++++------------------
target/riscv/translate.c | 12 ++++++++----
3 files changed, 17 insertions(+), 23 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index fa5a6ba1c8..9fba876e08 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -411,7 +411,8 @@ FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2)
/* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
FIELD(TB_FLAGS, XL, 13, 2)
/* If PointerMasking should be applied */
-FIELD(TB_FLAGS, PM_ENABLED, 15, 1)
+FIELD(TB_FLAGS, PM_MASK_ENABLED, 15, 1)
+FIELD(TB_FLAGS, PM_BASE_ENABLED, 16, 1)
#ifdef TARGET_RISCV32
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 8320f56d9f..a40ed6d748 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -108,26 +108,15 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
get_field(env->mstatus_hs, MSTATUS_FS));
}
- if (riscv_has_ext(env, RVJ)) {
- int priv = flags & TB_FLAGS_PRIV_MMU_MASK;
- bool pm_enabled = false;
- switch (priv) {
- case PRV_U:
- pm_enabled = env->mmte & U_PM_ENABLE;
- break;
- case PRV_S:
- pm_enabled = env->mmte & S_PM_ENABLE;
- break;
- case PRV_M:
- pm_enabled = env->mmte & M_PM_ENABLE;
- break;
- default:
- g_assert_not_reached();
- }
- flags = FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled);
- }
#endif
+ if (env->cur_pmmask < (xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) {
+ flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
+ }
+ if (env->cur_pmbase != 0) {
+ flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1);
+ }
+
flags = FIELD_DP32(flags, TB_FLAGS, XL, xl);
*pflags = flags;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index fd75f7c4bc..10c16e759d 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -87,7 +87,8 @@ typedef struct DisasContext {
/* Space for 3 operands plus 1 extra for address computation. */
TCGv temp[4];
/* PointerMasking extension */
- bool pm_enabled;
+ bool pm_mask_enabled;
+ bool pm_base_enabled;
} DisasContext;
static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -291,12 +292,14 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm)
TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
tcg_gen_addi_tl(addr, src1, imm);
- if (ctx->pm_enabled) {
+ if (ctx->pm_mask_enabled) {
tcg_gen_and_tl(addr, addr, pm_mask);
- tcg_gen_or_tl(addr, addr, pm_base);
} else if (get_xl(ctx) == MXL_RV32) {
tcg_gen_ext32u_tl(addr, addr);
}
+ if (ctx->pm_base_enabled) {
+ tcg_gen_or_tl(addr, addr, pm_base);
+ }
return addr;
}
@@ -643,7 +646,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->cs = cs;
ctx->ntemp = 0;
memset(ctx->temp, 0, sizeof(ctx->temp));
- ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
+ ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
+ ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
ctx->zero = tcg_constant_tl(0);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 11/20] target/riscv: Split pm_enabled into mask and base
@ 2021-11-11 5:57 ` LIU Zhiwei
0 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Alistair.Francis, palmer, bin.meng, richard.henderson, LIU Zhiwei
Use cached cur_pmmask and cur_pmbase to infer the
current PM mode.
This may decrease the TCG IR by one when pm_enabled
is true and pm_base_enabled is false.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/cpu.h | 3 ++-
target/riscv/cpu_helper.c | 25 +++++++------------------
target/riscv/translate.c | 12 ++++++++----
3 files changed, 17 insertions(+), 23 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index fa5a6ba1c8..9fba876e08 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -411,7 +411,8 @@ FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2)
/* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
FIELD(TB_FLAGS, XL, 13, 2)
/* If PointerMasking should be applied */
-FIELD(TB_FLAGS, PM_ENABLED, 15, 1)
+FIELD(TB_FLAGS, PM_MASK_ENABLED, 15, 1)
+FIELD(TB_FLAGS, PM_BASE_ENABLED, 16, 1)
#ifdef TARGET_RISCV32
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 8320f56d9f..a40ed6d748 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -108,26 +108,15 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
get_field(env->mstatus_hs, MSTATUS_FS));
}
- if (riscv_has_ext(env, RVJ)) {
- int priv = flags & TB_FLAGS_PRIV_MMU_MASK;
- bool pm_enabled = false;
- switch (priv) {
- case PRV_U:
- pm_enabled = env->mmte & U_PM_ENABLE;
- break;
- case PRV_S:
- pm_enabled = env->mmte & S_PM_ENABLE;
- break;
- case PRV_M:
- pm_enabled = env->mmte & M_PM_ENABLE;
- break;
- default:
- g_assert_not_reached();
- }
- flags = FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled);
- }
#endif
+ if (env->cur_pmmask < (xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) {
+ flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
+ }
+ if (env->cur_pmbase != 0) {
+ flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1);
+ }
+
flags = FIELD_DP32(flags, TB_FLAGS, XL, xl);
*pflags = flags;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index fd75f7c4bc..10c16e759d 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -87,7 +87,8 @@ typedef struct DisasContext {
/* Space for 3 operands plus 1 extra for address computation. */
TCGv temp[4];
/* PointerMasking extension */
- bool pm_enabled;
+ bool pm_mask_enabled;
+ bool pm_base_enabled;
} DisasContext;
static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -291,12 +292,14 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm)
TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
tcg_gen_addi_tl(addr, src1, imm);
- if (ctx->pm_enabled) {
+ if (ctx->pm_mask_enabled) {
tcg_gen_and_tl(addr, addr, pm_mask);
- tcg_gen_or_tl(addr, addr, pm_base);
} else if (get_xl(ctx) == MXL_RV32) {
tcg_gen_ext32u_tl(addr, addr);
}
+ if (ctx->pm_base_enabled) {
+ tcg_gen_or_tl(addr, addr, pm_base);
+ }
return addr;
}
@@ -643,7 +646,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->cs = cs;
ctx->ntemp = 0;
memset(ctx->temp, 0, sizeof(ctx->temp));
- ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
+ ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
+ ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
ctx->zero = tcg_constant_tl(0);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 12/20] target/riscv: Split out the vill from vtype
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 5:57 ` LIU Zhiwei
-1 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, richard.henderson, bin.meng, Alistair.Francis, LIU Zhiwei
We need not specially process vtype when XLEN changes.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_helper.c | 3 +--
target/riscv/csr.c | 13 ++++++++++++-
target/riscv/machine.c | 1 +
target/riscv/vector_helper.c | 3 ++-
5 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 9fba876e08..52ce670cbe 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -119,6 +119,7 @@ struct CPURISCVState {
target_ulong vl;
target_ulong vstart;
target_ulong vtype;
+ bool vill;
target_ulong pc;
target_ulong load_res;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index a40ed6d748..9b9dc83ab9 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -78,8 +78,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
if (riscv_has_ext(env, RVV)) {
uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
- flags = FIELD_DP32(flags, TB_FLAGS, VILL,
- FIELD_EX64(env->vtype, VTYPE, VILL));
+ flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill);
flags = FIELD_DP32(flags, TB_FLAGS, SEW,
FIELD_EX64(env->vtype, VTYPE, VSEW));
flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6bb2d09519..8f8f170768 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -286,7 +286,18 @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno,
static RISCVException read_vtype(CPURISCVState *env, int csrno,
target_ulong *val)
{
- *val = env->vtype;
+ uint64_t vill;
+ switch (cpu_get_xl(env)) {
+ case MXL_RV32:
+ vill = (uint32_t)env->vill << 31;
+ break;
+ case MXL_RV64:
+ vill = (uint64_t)env->vill << 63;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ *val = (target_ulong)vill | env->vtype;
return RISCV_EXCP_NONE;
}
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 19e982d3f0..2161bc80ca 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -104,6 +104,7 @@ static const VMStateDescription vmstate_vector = {
VMSTATE_UINTTL(env.vl, RISCVCPU),
VMSTATE_UINTTL(env.vstart, RISCVCPU),
VMSTATE_UINTTL(env.vtype, RISCVCPU),
+ VMSTATE_BOOL(env.vill, RISCVCPU),
VMSTATE_END_OF_LIST()
}
};
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 12c31aa4b4..b02ccefa4d 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -38,7 +38,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {
/* only set vill bit. */
- env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
+ env->vill = 1;
+ env->vtype = 0;
env->vl = 0;
env->vstart = 0;
return 0;
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 12/20] target/riscv: Split out the vill from vtype
@ 2021-11-11 5:57 ` LIU Zhiwei
0 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Alistair.Francis, palmer, bin.meng, richard.henderson, LIU Zhiwei
We need not specially process vtype when XLEN changes.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_helper.c | 3 +--
target/riscv/csr.c | 13 ++++++++++++-
target/riscv/machine.c | 1 +
target/riscv/vector_helper.c | 3 ++-
5 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 9fba876e08..52ce670cbe 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -119,6 +119,7 @@ struct CPURISCVState {
target_ulong vl;
target_ulong vstart;
target_ulong vtype;
+ bool vill;
target_ulong pc;
target_ulong load_res;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index a40ed6d748..9b9dc83ab9 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -78,8 +78,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
if (riscv_has_ext(env, RVV)) {
uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
- flags = FIELD_DP32(flags, TB_FLAGS, VILL,
- FIELD_EX64(env->vtype, VTYPE, VILL));
+ flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill);
flags = FIELD_DP32(flags, TB_FLAGS, SEW,
FIELD_EX64(env->vtype, VTYPE, VSEW));
flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6bb2d09519..8f8f170768 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -286,7 +286,18 @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno,
static RISCVException read_vtype(CPURISCVState *env, int csrno,
target_ulong *val)
{
- *val = env->vtype;
+ uint64_t vill;
+ switch (cpu_get_xl(env)) {
+ case MXL_RV32:
+ vill = (uint32_t)env->vill << 31;
+ break;
+ case MXL_RV64:
+ vill = (uint64_t)env->vill << 63;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ *val = (target_ulong)vill | env->vtype;
return RISCV_EXCP_NONE;
}
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 19e982d3f0..2161bc80ca 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -104,6 +104,7 @@ static const VMStateDescription vmstate_vector = {
VMSTATE_UINTTL(env.vl, RISCVCPU),
VMSTATE_UINTTL(env.vstart, RISCVCPU),
VMSTATE_UINTTL(env.vtype, RISCVCPU),
+ VMSTATE_BOOL(env.vill, RISCVCPU),
VMSTATE_END_OF_LIST()
}
};
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 12c31aa4b4..b02ccefa4d 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -38,7 +38,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {
/* only set vill bit. */
- env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
+ env->vill = 1;
+ env->vtype = 0;
env->vl = 0;
env->vstart = 0;
return 0;
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 13/20] target/riscv: Fix RESERVED field length in VTYPE
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 5:57 ` LIU Zhiwei
-1 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, richard.henderson, bin.meng, Alistair.Francis, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 52ce670cbe..b48c7c346c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -105,7 +105,7 @@ typedef struct CPURISCVState CPURISCVState;
FIELD(VTYPE, VLMUL, 0, 2)
FIELD(VTYPE, VSEW, 2, 3)
FIELD(VTYPE, VEDIV, 5, 2)
-FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
+FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 8)
FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
struct CPURISCVState {
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 13/20] target/riscv: Fix RESERVED field length in VTYPE
@ 2021-11-11 5:57 ` LIU Zhiwei
0 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Alistair.Francis, palmer, bin.meng, richard.henderson, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 52ce670cbe..b48c7c346c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -105,7 +105,7 @@ typedef struct CPURISCVState CPURISCVState;
FIELD(VTYPE, VLMUL, 0, 2)
FIELD(VTYPE, VSEW, 2, 3)
FIELD(VTYPE, VEDIV, 5, 2)
-FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
+FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 8)
FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
struct CPURISCVState {
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 14/20] target/riscv: Adjust vsetvl according to XLEN
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 5:57 ` LIU Zhiwei
-1 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, richard.henderson, bin.meng, Alistair.Francis, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/helper.h | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
target/riscv/vector_helper.c | 8 +++++---
3 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index c5098380dd..a67965efe5 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -82,7 +82,7 @@ DEF_HELPER_2(hyp_hlvx_wu, tl, env, tl)
#endif
/* Vector functions */
-DEF_HELPER_3(vsetvl, tl, env, tl, tl)
+DEF_HELPER_4(vsetvl, tl, env, tl, tl, tl)
DEF_HELPER_5(vlb_v_b, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vlb_v_b_mask, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vlb_v_h, void, ptr, ptr, tl, env, i32)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 17ee3babef..f5aabd5263 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -37,7 +37,7 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
} else {
s1 = get_gpr(ctx, a->rs1, EXT_ZERO);
}
- gen_helper_vsetvl(dst, cpu_env, s1, s2);
+ gen_helper_vsetvl(dst, cpu_env, s1, s2, tcg_constant_tl(get_xlen(ctx)));
gen_set_gpr(ctx, a->rd, dst);
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
@@ -64,7 +64,7 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
} else {
s1 = get_gpr(ctx, a->rs1, EXT_ZERO);
}
- gen_helper_vsetvl(dst, cpu_env, s1, s2);
+ gen_helper_vsetvl(dst, cpu_env, s1, s2, tcg_constant_tl(get_xlen(ctx)));
gen_set_gpr(ctx, a->rd, dst);
gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index b02ccefa4d..1a7ee46d46 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -27,14 +27,16 @@
#include <math.h>
target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
- target_ulong s2)
+ target_ulong s2, target_ulong xlen)
{
int vlmax, vl;
RISCVCPU *cpu = env_archcpu(env);
uint16_t sew = 8 << FIELD_EX64(s2, VTYPE, VSEW);
uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);
- bool vill = FIELD_EX64(s2, VTYPE, VILL);
- target_ulong reserved = FIELD_EX64(s2, VTYPE, RESERVED);
+ bool vill = (s2 >> (xlen - 1)) & 0x1;
+ target_ulong reserved = s2 &
+ MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
+ xlen - 1 - R_VTYPE_RESERVED_SHIFT);
if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {
/* only set vill bit. */
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 14/20] target/riscv: Adjust vsetvl according to XLEN
@ 2021-11-11 5:57 ` LIU Zhiwei
0 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Alistair.Francis, palmer, bin.meng, richard.henderson, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/helper.h | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
target/riscv/vector_helper.c | 8 +++++---
3 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index c5098380dd..a67965efe5 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -82,7 +82,7 @@ DEF_HELPER_2(hyp_hlvx_wu, tl, env, tl)
#endif
/* Vector functions */
-DEF_HELPER_3(vsetvl, tl, env, tl, tl)
+DEF_HELPER_4(vsetvl, tl, env, tl, tl, tl)
DEF_HELPER_5(vlb_v_b, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vlb_v_b_mask, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vlb_v_h, void, ptr, ptr, tl, env, i32)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 17ee3babef..f5aabd5263 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -37,7 +37,7 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
} else {
s1 = get_gpr(ctx, a->rs1, EXT_ZERO);
}
- gen_helper_vsetvl(dst, cpu_env, s1, s2);
+ gen_helper_vsetvl(dst, cpu_env, s1, s2, tcg_constant_tl(get_xlen(ctx)));
gen_set_gpr(ctx, a->rd, dst);
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
@@ -64,7 +64,7 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
} else {
s1 = get_gpr(ctx, a->rs1, EXT_ZERO);
}
- gen_helper_vsetvl(dst, cpu_env, s1, s2);
+ gen_helper_vsetvl(dst, cpu_env, s1, s2, tcg_constant_tl(get_xlen(ctx)));
gen_set_gpr(ctx, a->rd, dst);
gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index b02ccefa4d..1a7ee46d46 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -27,14 +27,16 @@
#include <math.h>
target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
- target_ulong s2)
+ target_ulong s2, target_ulong xlen)
{
int vlmax, vl;
RISCVCPU *cpu = env_archcpu(env);
uint16_t sew = 8 << FIELD_EX64(s2, VTYPE, VSEW);
uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);
- bool vill = FIELD_EX64(s2, VTYPE, VILL);
- target_ulong reserved = FIELD_EX64(s2, VTYPE, RESERVED);
+ bool vill = (s2 >> (xlen - 1)) & 0x1;
+ target_ulong reserved = s2 &
+ MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
+ xlen - 1 - R_VTYPE_RESERVED_SHIFT);
if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {
/* only set vill bit. */
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 15/20] target/riscv: Remove VILL field in VTYPE
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 5:57 ` LIU Zhiwei
-1 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, richard.henderson, bin.meng, Alistair.Francis, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/cpu.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index b48c7c346c..5f35217f7d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -106,7 +106,6 @@ FIELD(VTYPE, VLMUL, 0, 2)
FIELD(VTYPE, VSEW, 2, 3)
FIELD(VTYPE, VEDIV, 5, 2)
FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 8)
-FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
struct CPURISCVState {
target_ulong gpr[32];
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 15/20] target/riscv: Remove VILL field in VTYPE
@ 2021-11-11 5:57 ` LIU Zhiwei
0 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Alistair.Francis, palmer, bin.meng, richard.henderson, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/cpu.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index b48c7c346c..5f35217f7d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -106,7 +106,6 @@ FIELD(VTYPE, VLMUL, 0, 2)
FIELD(VTYPE, VSEW, 2, 3)
FIELD(VTYPE, VEDIV, 5, 2)
FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 8)
-FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
struct CPURISCVState {
target_ulong gpr[32];
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 16/20] target/riscv: Ajdust vector atomic check with XLEN
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 5:57 ` LIU Zhiwei
-1 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, richard.henderson, bin.meng, Alistair.Francis, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index f5aabd5263..41c7c88904 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -739,7 +739,8 @@ static bool amo_check(DisasContext *s, arg_rwdvm* a)
(!a->wd || vext_check_overlap_mask(s, a->rd, a->vm, false)) &&
vext_check_reg(s, a->rd, false) &&
vext_check_reg(s, a->rs2, false) &&
- ((1 << s->sew) <= sizeof(target_ulong)) &&
+ /* TODO: RV128 could allow 128-bit atomics */
+ ((1 << s->sew) <= (get_xl(s) == MXL_RV32 ? 4 : 8)) &&
((1 << s->sew) >= 4));
}
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 16/20] target/riscv: Ajdust vector atomic check with XLEN
@ 2021-11-11 5:57 ` LIU Zhiwei
0 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Alistair.Francis, palmer, bin.meng, richard.henderson, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index f5aabd5263..41c7c88904 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -739,7 +739,8 @@ static bool amo_check(DisasContext *s, arg_rwdvm* a)
(!a->wd || vext_check_overlap_mask(s, a->rd, a->vm, false)) &&
vext_check_reg(s, a->rd, false) &&
vext_check_reg(s, a->rs2, false) &&
- ((1 << s->sew) <= sizeof(target_ulong)) &&
+ /* TODO: RV128 could allow 128-bit atomics */
+ ((1 << s->sew) <= (get_xl(s) == MXL_RV32 ? 4 : 8)) &&
((1 << s->sew) >= 4));
}
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 17/20] target/riscv: Fix check range for first fault only
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 5:57 ` LIU Zhiwei
-1 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, richard.henderson, bin.meng, Alistair.Francis, LIU Zhiwei
Only check the range that has passed the address translation.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/vector_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 1a7ee46d46..ee58187d26 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -630,12 +630,12 @@ vext_ldff(void *vd, void *v0, target_ulong base,
cpu_mmu_index(env, false));
if (host) {
#ifdef CONFIG_USER_ONLY
- if (page_check_range(addr, nf * msz, PAGE_READ) < 0) {
+ if (page_check_range(addr, offset, PAGE_READ) < 0) {
vl = i;
goto ProbeSuccess;
}
#else
- probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD);
+ probe_pages(env, addr, offset, ra, MMU_DATA_LOAD);
#endif
} else {
vl = i;
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 17/20] target/riscv: Fix check range for first fault only
@ 2021-11-11 5:57 ` LIU Zhiwei
0 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Alistair.Francis, palmer, bin.meng, richard.henderson, LIU Zhiwei
Only check the range that has passed the address translation.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/vector_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 1a7ee46d46..ee58187d26 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -630,12 +630,12 @@ vext_ldff(void *vd, void *v0, target_ulong base,
cpu_mmu_index(env, false));
if (host) {
#ifdef CONFIG_USER_ONLY
- if (page_check_range(addr, nf * msz, PAGE_READ) < 0) {
+ if (page_check_range(addr, offset, PAGE_READ) < 0) {
vl = i;
goto ProbeSuccess;
}
#else
- probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD);
+ probe_pages(env, addr, offset, ra, MMU_DATA_LOAD);
#endif
} else {
vl = i;
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 18/20] target/riscv: Adjust vector address with mask
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 5:57 ` LIU Zhiwei
-1 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, richard.henderson, bin.meng, Alistair.Francis, LIU Zhiwei
The mask comes from the pointer masking extension, or the max value
corresponding to XLEN bits.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/vector_helper.c | 23 ++++++++++++++---------
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index ee58187d26..2667cae63b 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -115,6 +115,11 @@ static inline uint32_t vext_maxsz(uint32_t desc)
return simd_maxsz(desc) << vext_lmul(desc);
}
+static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
+{
+ return (addr & env->cur_pmmask) | env->cur_pmbase;
+}
+
/*
* This function checks watchpoint before real load operation.
*
@@ -132,12 +137,12 @@ static void probe_pages(CPURISCVState *env, target_ulong addr,
target_ulong pagelen = -(addr | TARGET_PAGE_MASK);
target_ulong curlen = MIN(pagelen, len);
- probe_access(env, addr, curlen, access_type,
+ probe_access(env, adjust_addr(env, addr), curlen, access_type,
cpu_mmu_index(env, false), ra);
if (len > curlen) {
addr += curlen;
curlen = len - curlen;
- probe_access(env, addr, curlen, access_type,
+ probe_access(env, adjust_addr(env, addr), curlen, access_type,
cpu_mmu_index(env, false), ra);
}
}
@@ -298,7 +303,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
}
while (k < nf) {
target_ulong addr = base + stride * i + k * msz;
- ldst_elem(env, addr, i + k * vlmax, vd, ra);
+ ldst_elem(env, adjust_addr(env, addr), i + k * vlmax, vd, ra);
k++;
}
}
@@ -391,7 +396,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
k = 0;
while (k < nf) {
target_ulong addr = base + (i * nf + k) * msz;
- ldst_elem(env, addr, i + k * vlmax, vd, ra);
+ ldst_elem(env, adjust_addr(env, addr), i + k * vlmax, vd, ra);
k++;
}
}
@@ -528,7 +533,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
}
while (k < nf) {
abi_ptr addr = get_index_addr(base, i, vs2) + k * msz;
- ldst_elem(env, addr, i + k * vlmax, vd, ra);
+ ldst_elem(env, adjust_addr(env, addr), i + k * vlmax, vd, ra);
k++;
}
}
@@ -618,7 +623,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
if (!vm && !vext_elem_mask(v0, mlen, i)) {
continue;
}
- addr = base + nf * i * msz;
+ addr = adjust_addr(env, base + nf * i * msz);
if (i == 0) {
probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD);
} else {
@@ -645,7 +650,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
break;
}
remain -= offset;
- addr += offset;
+ addr = adjust_addr(env, addr + offset);
}
}
}
@@ -661,7 +666,7 @@ ProbeSuccess:
}
while (k < nf) {
target_ulong addr = base + (i * nf + k) * msz;
- ldst_elem(env, addr, i + k * vlmax, vd, ra);
+ ldst_elem(env, adjust_addr(env, addr), i + k * vlmax, vd, ra);
k++;
}
}
@@ -800,7 +805,7 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
continue;
}
addr = get_index_addr(base, i, vs2);
- noatomic_op(vs3, addr, wd, i, env, ra);
+ noatomic_op(vs3, adjust_addr(env, addr), wd, i, env, ra);
}
clear_elem(vs3, env->vl, env->vl * esz, vlmax * esz);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 18/20] target/riscv: Adjust vector address with mask
@ 2021-11-11 5:57 ` LIU Zhiwei
0 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Alistair.Francis, palmer, bin.meng, richard.henderson, LIU Zhiwei
The mask comes from the pointer masking extension, or the max value
corresponding to XLEN bits.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/vector_helper.c | 23 ++++++++++++++---------
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index ee58187d26..2667cae63b 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -115,6 +115,11 @@ static inline uint32_t vext_maxsz(uint32_t desc)
return simd_maxsz(desc) << vext_lmul(desc);
}
+static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
+{
+ return (addr & env->cur_pmmask) | env->cur_pmbase;
+}
+
/*
* This function checks watchpoint before real load operation.
*
@@ -132,12 +137,12 @@ static void probe_pages(CPURISCVState *env, target_ulong addr,
target_ulong pagelen = -(addr | TARGET_PAGE_MASK);
target_ulong curlen = MIN(pagelen, len);
- probe_access(env, addr, curlen, access_type,
+ probe_access(env, adjust_addr(env, addr), curlen, access_type,
cpu_mmu_index(env, false), ra);
if (len > curlen) {
addr += curlen;
curlen = len - curlen;
- probe_access(env, addr, curlen, access_type,
+ probe_access(env, adjust_addr(env, addr), curlen, access_type,
cpu_mmu_index(env, false), ra);
}
}
@@ -298,7 +303,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
}
while (k < nf) {
target_ulong addr = base + stride * i + k * msz;
- ldst_elem(env, addr, i + k * vlmax, vd, ra);
+ ldst_elem(env, adjust_addr(env, addr), i + k * vlmax, vd, ra);
k++;
}
}
@@ -391,7 +396,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
k = 0;
while (k < nf) {
target_ulong addr = base + (i * nf + k) * msz;
- ldst_elem(env, addr, i + k * vlmax, vd, ra);
+ ldst_elem(env, adjust_addr(env, addr), i + k * vlmax, vd, ra);
k++;
}
}
@@ -528,7 +533,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
}
while (k < nf) {
abi_ptr addr = get_index_addr(base, i, vs2) + k * msz;
- ldst_elem(env, addr, i + k * vlmax, vd, ra);
+ ldst_elem(env, adjust_addr(env, addr), i + k * vlmax, vd, ra);
k++;
}
}
@@ -618,7 +623,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
if (!vm && !vext_elem_mask(v0, mlen, i)) {
continue;
}
- addr = base + nf * i * msz;
+ addr = adjust_addr(env, base + nf * i * msz);
if (i == 0) {
probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD);
} else {
@@ -645,7 +650,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
break;
}
remain -= offset;
- addr += offset;
+ addr = adjust_addr(env, addr + offset);
}
}
}
@@ -661,7 +666,7 @@ ProbeSuccess:
}
while (k < nf) {
target_ulong addr = base + (i * nf + k) * msz;
- ldst_elem(env, addr, i + k * vlmax, vd, ra);
+ ldst_elem(env, adjust_addr(env, addr), i + k * vlmax, vd, ra);
k++;
}
}
@@ -800,7 +805,7 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
continue;
}
addr = get_index_addr(base, i, vs2);
- noatomic_op(vs3, addr, wd, i, env, ra);
+ noatomic_op(vs3, adjust_addr(env, addr), wd, i, env, ra);
}
clear_elem(vs3, env->vl, env->vl * esz, vlmax * esz);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 19/20] target/riscv: Adjust scalar reg in vector with XLEN
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 5:57 ` LIU Zhiwei
-1 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, richard.henderson, bin.meng, Alistair.Francis, LIU Zhiwei
When sew <= 32bits, not need to extend scalar reg.
When sew > 32bits, if xlen is less that sew, we should sign extend
the scalar register, except explicitly specified by the spec.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 44 ++++++++++++++++++-------
1 file changed, 32 insertions(+), 12 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 41c7c88904..7301992f82 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -833,7 +833,7 @@ typedef void gen_helper_opivx(TCGv_ptr, TCGv_ptr, TCGv, TCGv_ptr,
TCGv_env, TCGv_i32);
static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
- gen_helper_opivx *fn, DisasContext *s)
+ gen_helper_opivx *fn, DisasContext *s, DisasExtend ext)
{
TCGv_ptr dest, src2, mask;
TCGv src1;
@@ -846,7 +846,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
src2 = tcg_temp_new_ptr();
- src1 = get_gpr(s, rs1, EXT_NONE);
+ src1 = get_gpr(s, rs1, ext);
data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, vm);
@@ -895,7 +895,7 @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
tcg_temp_free_i64(src1);
return true;
}
- return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, EXT_SIGN);
}
/* OPIVX with GVEC IR */
@@ -1128,7 +1128,7 @@ static bool do_opivx_widen(DisasContext *s, arg_rmrr *a,
gen_helper_opivx *fn)
{
if (opivx_widen_check(s, a)) {
- return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, EXT_SIGN);
}
return false;
}
@@ -1213,7 +1213,7 @@ static bool do_opiwx_widen(DisasContext *s, arg_rmrr *a,
gen_helper_opivx *fn)
{
if (opiwx_widen_check(s, a)) {
- return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, EXT_SIGN);
}
return false;
}
@@ -1312,7 +1312,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
}; \
\
- return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, \
+ fns[s->sew], s, EXT_SIGN); \
} \
return false; \
}
@@ -1386,7 +1387,7 @@ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn,
tcg_temp_free_i32(src1);
return true;
}
- return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, EXT_SIGN);
}
#define GEN_OPIVX_GVEC_SHIFT_TRANS(NAME, SUF) \
@@ -1472,7 +1473,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_h, \
gen_helper_##NAME##_w, \
}; \
- return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, \
+ fns[s->sew], s, EXT_SIGN); \
} \
return false; \
}
@@ -2670,6 +2672,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
/* This instruction ignores LMUL and vector register groups */
int maxsz = s->vlen >> 3;
TCGv_i64 t1;
+ TCGv src1 = get_gpr(s, a->rs1, EXT_ZERO);
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
@@ -2679,7 +2682,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
}
t1 = tcg_temp_new_i64();
- tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
+ tcg_gen_extu_tl_i64(t1, src1);
vec_element_storei(s, a->rd, 0, t1);
tcg_temp_free_i64(t1);
done:
@@ -2748,12 +2751,28 @@ static bool slideup_check(DisasContext *s, arg_rmrr *a)
(a->rd != a->rs2));
}
+/* OPIVXU without GVEC IR */
+#define GEN_OPIVXU_TRANS(NAME, CHECK) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ if (CHECK(s, a)) { \
+ static gen_helper_opivx * const fns[4] = { \
+ gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
+ }; \
+ \
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, \
+ fns[s->sew], s, EXT_ZERO); \
+ } \
+ return false; \
+}
+
GEN_OPIVX_TRANS(vslideup_vx, slideup_check)
-GEN_OPIVX_TRANS(vslide1up_vx, slideup_check)
+GEN_OPIVXU_TRANS(vslide1up_vx, slideup_check)
GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx, slideup_check)
GEN_OPIVX_TRANS(vslidedown_vx, opivx_check)
-GEN_OPIVX_TRANS(vslide1down_vx, opivx_check)
+GEN_OPIVXU_TRANS(vslide1down_vx, opivx_check)
GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, opivx_check)
/* Vector Register Gather Instruction */
@@ -2803,7 +2822,8 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h,
gen_helper_vrgather_vx_w, gen_helper_vrgather_vx_d
};
- return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm,
+ fns[s->sew], s, EXT_SIGN);
}
return true;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 19/20] target/riscv: Adjust scalar reg in vector with XLEN
@ 2021-11-11 5:57 ` LIU Zhiwei
0 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Alistair.Francis, palmer, bin.meng, richard.henderson, LIU Zhiwei
When sew <= 32bits, not need to extend scalar reg.
When sew > 32bits, if xlen is less that sew, we should sign extend
the scalar register, except explicitly specified by the spec.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 44 ++++++++++++++++++-------
1 file changed, 32 insertions(+), 12 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 41c7c88904..7301992f82 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -833,7 +833,7 @@ typedef void gen_helper_opivx(TCGv_ptr, TCGv_ptr, TCGv, TCGv_ptr,
TCGv_env, TCGv_i32);
static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
- gen_helper_opivx *fn, DisasContext *s)
+ gen_helper_opivx *fn, DisasContext *s, DisasExtend ext)
{
TCGv_ptr dest, src2, mask;
TCGv src1;
@@ -846,7 +846,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
src2 = tcg_temp_new_ptr();
- src1 = get_gpr(s, rs1, EXT_NONE);
+ src1 = get_gpr(s, rs1, ext);
data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, vm);
@@ -895,7 +895,7 @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
tcg_temp_free_i64(src1);
return true;
}
- return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, EXT_SIGN);
}
/* OPIVX with GVEC IR */
@@ -1128,7 +1128,7 @@ static bool do_opivx_widen(DisasContext *s, arg_rmrr *a,
gen_helper_opivx *fn)
{
if (opivx_widen_check(s, a)) {
- return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, EXT_SIGN);
}
return false;
}
@@ -1213,7 +1213,7 @@ static bool do_opiwx_widen(DisasContext *s, arg_rmrr *a,
gen_helper_opivx *fn)
{
if (opiwx_widen_check(s, a)) {
- return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, EXT_SIGN);
}
return false;
}
@@ -1312,7 +1312,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
}; \
\
- return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, \
+ fns[s->sew], s, EXT_SIGN); \
} \
return false; \
}
@@ -1386,7 +1387,7 @@ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn,
tcg_temp_free_i32(src1);
return true;
}
- return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, EXT_SIGN);
}
#define GEN_OPIVX_GVEC_SHIFT_TRANS(NAME, SUF) \
@@ -1472,7 +1473,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_h, \
gen_helper_##NAME##_w, \
}; \
- return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, \
+ fns[s->sew], s, EXT_SIGN); \
} \
return false; \
}
@@ -2670,6 +2672,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
/* This instruction ignores LMUL and vector register groups */
int maxsz = s->vlen >> 3;
TCGv_i64 t1;
+ TCGv src1 = get_gpr(s, a->rs1, EXT_ZERO);
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
@@ -2679,7 +2682,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
}
t1 = tcg_temp_new_i64();
- tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
+ tcg_gen_extu_tl_i64(t1, src1);
vec_element_storei(s, a->rd, 0, t1);
tcg_temp_free_i64(t1);
done:
@@ -2748,12 +2751,28 @@ static bool slideup_check(DisasContext *s, arg_rmrr *a)
(a->rd != a->rs2));
}
+/* OPIVXU without GVEC IR */
+#define GEN_OPIVXU_TRANS(NAME, CHECK) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ if (CHECK(s, a)) { \
+ static gen_helper_opivx * const fns[4] = { \
+ gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
+ }; \
+ \
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, \
+ fns[s->sew], s, EXT_ZERO); \
+ } \
+ return false; \
+}
+
GEN_OPIVX_TRANS(vslideup_vx, slideup_check)
-GEN_OPIVX_TRANS(vslide1up_vx, slideup_check)
+GEN_OPIVXU_TRANS(vslide1up_vx, slideup_check)
GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx, slideup_check)
GEN_OPIVX_TRANS(vslidedown_vx, opivx_check)
-GEN_OPIVX_TRANS(vslide1down_vx, opivx_check)
+GEN_OPIVXU_TRANS(vslide1down_vx, opivx_check)
GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, opivx_check)
/* Vector Register Gather Instruction */
@@ -2803,7 +2822,8 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h,
gen_helper_vrgather_vx_w, gen_helper_vrgather_vx_d
};
- return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm,
+ fns[s->sew], s, EXT_SIGN);
}
return true;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 20/20] target/riscv: Enable uxl field write
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 5:58 ` LIU Zhiwei
-1 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:58 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, richard.henderson, bin.meng, Alistair.Francis, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/csr.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 8f8f170768..43eaa6c710 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -553,15 +553,14 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
* RV32: MPV and GVA are not in mstatus. The current plan is to
* add them to mstatush. For now, we just don't support it.
*/
- mask |= MSTATUS_MPV | MSTATUS_GVA;
+ mask |= MSTATUS_MPV | MSTATUS_GVA | MSTATUS64_UXL;
}
mstatus = (mstatus & ~mask) | (val & mask);
if (riscv_cpu_mxl(env) == MXL_RV64) {
- /* SXL and UXL fields are for now read only */
+ /* SXL fields are for now read only */
mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
- mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
}
env->mstatus = mstatus;
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3 20/20] target/riscv: Enable uxl field write
@ 2021-11-11 5:58 ` LIU Zhiwei
0 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 5:58 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Alistair.Francis, palmer, bin.meng, richard.henderson, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/csr.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 8f8f170768..43eaa6c710 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -553,15 +553,14 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
* RV32: MPV and GVA are not in mstatus. The current plan is to
* add them to mstatush. For now, we just don't support it.
*/
- mask |= MSTATUS_MPV | MSTATUS_GVA;
+ mask |= MSTATUS_MPV | MSTATUS_GVA | MSTATUS64_UXL;
}
mstatus = (mstatus & ~mask) | (val & mask);
if (riscv_cpu_mxl(env) == MXL_RV64) {
- /* SXL and UXL fields are for now read only */
+ /* SXL fields are for now read only */
mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
- mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
}
env->mstatus = mstatus;
--
2.25.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* Re: [PATCH v3 04/20] target/riscv: Extend pc for runtime pc write
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 11:19 ` Richard Henderson
-1 siblings, 0 replies; 72+ messages in thread
From: Richard Henderson @ 2021-11-11 11:19 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel, qemu-riscv; +Cc: palmer, bin.meng, Alistair.Francis
On 11/11/21 6:57 AM, LIU Zhiwei wrote:
> In some cases, we must restore the guest PC to the address of the start of
> the TB, such as when the instruction counter hits zero. So extend pc register
> according to current xlen for these cases.
>
> Signed-off-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
> ---
> target/riscv/cpu.c | 22 +++++++++++++++++++---
> target/riscv/cpu.h | 2 ++
> target/riscv/cpu_helper.c | 2 +-
> 3 files changed, 22 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3 04/20] target/riscv: Extend pc for runtime pc write
@ 2021-11-11 11:19 ` Richard Henderson
0 siblings, 0 replies; 72+ messages in thread
From: Richard Henderson @ 2021-11-11 11:19 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel, qemu-riscv; +Cc: Alistair.Francis, palmer, bin.meng
On 11/11/21 6:57 AM, LIU Zhiwei wrote:
> In some cases, we must restore the guest PC to the address of the start of
> the TB, such as when the instruction counter hits zero. So extend pc register
> according to current xlen for these cases.
>
> Signed-off-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
> ---
> target/riscv/cpu.c | 22 +++++++++++++++++++---
> target/riscv/cpu.h | 2 ++
> target/riscv/cpu_helper.c | 2 +-
> 3 files changed, 22 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3 07/20] target/riscv: Adjust csr write mask with XLEN
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 11:21 ` Richard Henderson
-1 siblings, 0 replies; 72+ messages in thread
From: Richard Henderson @ 2021-11-11 11:21 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel, qemu-riscv; +Cc: palmer, bin.meng, Alistair.Francis
On 11/11/21 6:57 AM, LIU Zhiwei wrote:
> Write mask is representing the bits we care about.
>
> Signed-off-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
> ---
> target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
> target/riscv/op_helper.c | 3 ++-
> 2 files changed, 4 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3 07/20] target/riscv: Adjust csr write mask with XLEN
@ 2021-11-11 11:21 ` Richard Henderson
0 siblings, 0 replies; 72+ messages in thread
From: Richard Henderson @ 2021-11-11 11:21 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel, qemu-riscv; +Cc: Alistair.Francis, palmer, bin.meng
On 11/11/21 6:57 AM, LIU Zhiwei wrote:
> Write mask is representing the bits we care about.
>
> Signed-off-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
> ---
> target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
> target/riscv/op_helper.c | 3 ++-
> 2 files changed, 4 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3 09/20] target/riscv: Alloc tcg global for cur_pm[mask|base]
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 11:26 ` Richard Henderson
-1 siblings, 0 replies; 72+ messages in thread
From: Richard Henderson @ 2021-11-11 11:26 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel, qemu-riscv; +Cc: palmer, bin.meng, Alistair.Francis
On 11/11/21 6:57 AM, LIU Zhiwei wrote:
> Replace the array of pm_mask/pm_base with scalar variables.
> Remove the cached array value in DisasContext.
>
> Signed-off-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
> ---
> target/riscv/translate.c | 32 ++++++++------------------------
> 1 file changed, 8 insertions(+), 24 deletions(-)
>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3 09/20] target/riscv: Alloc tcg global for cur_pm[mask|base]
@ 2021-11-11 11:26 ` Richard Henderson
0 siblings, 0 replies; 72+ messages in thread
From: Richard Henderson @ 2021-11-11 11:26 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel, qemu-riscv; +Cc: Alistair.Francis, palmer, bin.meng
On 11/11/21 6:57 AM, LIU Zhiwei wrote:
> Replace the array of pm_mask/pm_base with scalar variables.
> Remove the cached array value in DisasContext.
>
> Signed-off-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
> ---
> target/riscv/translate.c | 32 ++++++++------------------------
> 1 file changed, 8 insertions(+), 24 deletions(-)
>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3 10/20] target/riscv: Calculate address according to XLEN
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 11:28 ` Richard Henderson
-1 siblings, 0 replies; 72+ messages in thread
From: Richard Henderson @ 2021-11-11 11:28 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel, qemu-riscv; +Cc: palmer, bin.meng, Alistair.Francis
On 11/11/21 6:57 AM, LIU Zhiwei wrote:
> Define one common function to compute a canonical address from a register
> plus offset. Merge gen_pm_adjust_address into this function.
>
> Signed-off-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
> ---
> target/riscv/insn_trans/trans_rva.c.inc | 9 +++------
> target/riscv/insn_trans/trans_rvd.c.inc | 19 ++---------------
> target/riscv/insn_trans/trans_rvf.c.inc | 19 ++---------------
> target/riscv/insn_trans/trans_rvi.c.inc | 18 ++---------------
> target/riscv/translate.c | 27 ++++++++++++-------------
> 5 files changed, 22 insertions(+), 70 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3 10/20] target/riscv: Calculate address according to XLEN
@ 2021-11-11 11:28 ` Richard Henderson
0 siblings, 0 replies; 72+ messages in thread
From: Richard Henderson @ 2021-11-11 11:28 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel, qemu-riscv; +Cc: Alistair.Francis, palmer, bin.meng
On 11/11/21 6:57 AM, LIU Zhiwei wrote:
> Define one common function to compute a canonical address from a register
> plus offset. Merge gen_pm_adjust_address into this function.
>
> Signed-off-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
> ---
> target/riscv/insn_trans/trans_rva.c.inc | 9 +++------
> target/riscv/insn_trans/trans_rvd.c.inc | 19 ++---------------
> target/riscv/insn_trans/trans_rvf.c.inc | 19 ++---------------
> target/riscv/insn_trans/trans_rvi.c.inc | 18 ++---------------
> target/riscv/translate.c | 27 ++++++++++++-------------
> 5 files changed, 22 insertions(+), 70 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3 11/20] target/riscv: Split pm_enabled into mask and base
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 11:29 ` Richard Henderson
-1 siblings, 0 replies; 72+ messages in thread
From: Richard Henderson @ 2021-11-11 11:29 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel, qemu-riscv; +Cc: palmer, bin.meng, Alistair.Francis
On 11/11/21 6:57 AM, LIU Zhiwei wrote:
> Use cached cur_pmmask and cur_pmbase to infer the
> current PM mode.
>
> This may decrease the TCG IR by one when pm_enabled
> is true and pm_base_enabled is false.
>
> Signed-off-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
> ---
> target/riscv/cpu.h | 3 ++-
> target/riscv/cpu_helper.c | 25 +++++++------------------
> target/riscv/translate.c | 12 ++++++++----
> 3 files changed, 17 insertions(+), 23 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3 11/20] target/riscv: Split pm_enabled into mask and base
@ 2021-11-11 11:29 ` Richard Henderson
0 siblings, 0 replies; 72+ messages in thread
From: Richard Henderson @ 2021-11-11 11:29 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel, qemu-riscv; +Cc: Alistair.Francis, palmer, bin.meng
On 11/11/21 6:57 AM, LIU Zhiwei wrote:
> Use cached cur_pmmask and cur_pmbase to infer the
> current PM mode.
>
> This may decrease the TCG IR by one when pm_enabled
> is true and pm_base_enabled is false.
>
> Signed-off-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
> ---
> target/riscv/cpu.h | 3 ++-
> target/riscv/cpu_helper.c | 25 +++++++------------------
> target/riscv/translate.c | 12 ++++++++----
> 3 files changed, 17 insertions(+), 23 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3 12/20] target/riscv: Split out the vill from vtype
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 11:31 ` Richard Henderson
-1 siblings, 0 replies; 72+ messages in thread
From: Richard Henderson @ 2021-11-11 11:31 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel, qemu-riscv; +Cc: palmer, bin.meng, Alistair.Francis
On 11/11/21 6:57 AM, LIU Zhiwei wrote:
> We need not specially process vtype when XLEN changes.
>
> Signed-off-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
> ---
> target/riscv/cpu.h | 1 +
> target/riscv/cpu_helper.c | 3 +--
> target/riscv/csr.c | 13 ++++++++++++-
> target/riscv/machine.c | 1 +
> target/riscv/vector_helper.c | 3 ++-
> 5 files changed, 17 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> @@ -104,6 +104,7 @@ static const VMStateDescription vmstate_vector = {
> VMSTATE_UINTTL(env.vl, RISCVCPU),
> VMSTATE_UINTTL(env.vstart, RISCVCPU),
> VMSTATE_UINTTL(env.vtype, RISCVCPU),
> + VMSTATE_BOOL(env.vill, RISCVCPU),
> VMSTATE_END_OF_LIST()
Need to bump version.
r~
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3 12/20] target/riscv: Split out the vill from vtype
@ 2021-11-11 11:31 ` Richard Henderson
0 siblings, 0 replies; 72+ messages in thread
From: Richard Henderson @ 2021-11-11 11:31 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel, qemu-riscv; +Cc: Alistair.Francis, palmer, bin.meng
On 11/11/21 6:57 AM, LIU Zhiwei wrote:
> We need not specially process vtype when XLEN changes.
>
> Signed-off-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
> ---
> target/riscv/cpu.h | 1 +
> target/riscv/cpu_helper.c | 3 +--
> target/riscv/csr.c | 13 ++++++++++++-
> target/riscv/machine.c | 1 +
> target/riscv/vector_helper.c | 3 ++-
> 5 files changed, 17 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> @@ -104,6 +104,7 @@ static const VMStateDescription vmstate_vector = {
> VMSTATE_UINTTL(env.vl, RISCVCPU),
> VMSTATE_UINTTL(env.vstart, RISCVCPU),
> VMSTATE_UINTTL(env.vtype, RISCVCPU),
> + VMSTATE_BOOL(env.vill, RISCVCPU),
> VMSTATE_END_OF_LIST()
Need to bump version.
r~
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3 13/20] target/riscv: Fix RESERVED field length in VTYPE
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 11:33 ` Richard Henderson
-1 siblings, 0 replies; 72+ messages in thread
From: Richard Henderson @ 2021-11-11 11:33 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel, qemu-riscv; +Cc: palmer, bin.meng, Alistair.Francis
On 11/11/21 6:57 AM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> ---
> target/riscv/cpu.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 52ce670cbe..b48c7c346c 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -105,7 +105,7 @@ typedef struct CPURISCVState CPURISCVState;
> FIELD(VTYPE, VLMUL, 0, 2)
> FIELD(VTYPE, VSEW, 2, 3)
> FIELD(VTYPE, VEDIV, 5, 2)
> -FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
> +FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 8)
Or better, remove it in the next patch.
r~
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3 13/20] target/riscv: Fix RESERVED field length in VTYPE
@ 2021-11-11 11:33 ` Richard Henderson
0 siblings, 0 replies; 72+ messages in thread
From: Richard Henderson @ 2021-11-11 11:33 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel, qemu-riscv; +Cc: Alistair.Francis, palmer, bin.meng
On 11/11/21 6:57 AM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> ---
> target/riscv/cpu.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 52ce670cbe..b48c7c346c 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -105,7 +105,7 @@ typedef struct CPURISCVState CPURISCVState;
> FIELD(VTYPE, VLMUL, 0, 2)
> FIELD(VTYPE, VSEW, 2, 3)
> FIELD(VTYPE, VEDIV, 5, 2)
> -FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
> +FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 8)
Or better, remove it in the next patch.
r~
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3 13/20] target/riscv: Fix RESERVED field length in VTYPE
2021-11-11 11:33 ` Richard Henderson
@ 2021-11-11 11:33 ` Richard Henderson
-1 siblings, 0 replies; 72+ messages in thread
From: Richard Henderson @ 2021-11-11 11:33 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel, qemu-riscv; +Cc: palmer, bin.meng, Alistair.Francis
On 11/11/21 12:33 PM, Richard Henderson wrote:
> On 11/11/21 6:57 AM, LIU Zhiwei wrote:
>> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
>> ---
>> target/riscv/cpu.h | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index 52ce670cbe..b48c7c346c 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -105,7 +105,7 @@ typedef struct CPURISCVState CPURISCVState;
>> FIELD(VTYPE, VLMUL, 0, 2)
>> FIELD(VTYPE, VSEW, 2, 3)
>> FIELD(VTYPE, VEDIV, 5, 2)
>> -FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
>> +FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 8)
>
> Or better, remove it in the next patch.
Bah, nevermind.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3 13/20] target/riscv: Fix RESERVED field length in VTYPE
@ 2021-11-11 11:33 ` Richard Henderson
0 siblings, 0 replies; 72+ messages in thread
From: Richard Henderson @ 2021-11-11 11:33 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel, qemu-riscv; +Cc: Alistair.Francis, palmer, bin.meng
On 11/11/21 12:33 PM, Richard Henderson wrote:
> On 11/11/21 6:57 AM, LIU Zhiwei wrote:
>> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
>> ---
>> target/riscv/cpu.h | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index 52ce670cbe..b48c7c346c 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -105,7 +105,7 @@ typedef struct CPURISCVState CPURISCVState;
>> FIELD(VTYPE, VLMUL, 0, 2)
>> FIELD(VTYPE, VSEW, 2, 3)
>> FIELD(VTYPE, VEDIV, 5, 2)
>> -FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
>> +FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 8)
>
> Or better, remove it in the next patch.
Bah, nevermind.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3 14/20] target/riscv: Adjust vsetvl according to XLEN
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 11:35 ` Richard Henderson
-1 siblings, 0 replies; 72+ messages in thread
From: Richard Henderson @ 2021-11-11 11:35 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel, qemu-riscv; +Cc: palmer, bin.meng, Alistair.Francis
On 11/11/21 6:57 AM, LIU Zhiwei wrote:
> -DEF_HELPER_3(vsetvl, tl, env, tl, tl)
> +DEF_HELPER_4(vsetvl, tl, env, tl, tl, tl)
Might as well make the argument i32, or don't pass it at all and use cpu_get_xl().
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3 14/20] target/riscv: Adjust vsetvl according to XLEN
@ 2021-11-11 11:35 ` Richard Henderson
0 siblings, 0 replies; 72+ messages in thread
From: Richard Henderson @ 2021-11-11 11:35 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel, qemu-riscv; +Cc: Alistair.Francis, palmer, bin.meng
On 11/11/21 6:57 AM, LIU Zhiwei wrote:
> -DEF_HELPER_3(vsetvl, tl, env, tl, tl)
> +DEF_HELPER_4(vsetvl, tl, env, tl, tl, tl)
Might as well make the argument i32, or don't pass it at all and use cpu_get_xl().
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3 15/20] target/riscv: Remove VILL field in VTYPE
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 11:38 ` Richard Henderson
-1 siblings, 0 replies; 72+ messages in thread
From: Richard Henderson @ 2021-11-11 11:38 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel, qemu-riscv; +Cc: palmer, bin.meng, Alistair.Francis
On 11/11/21 6:57 AM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> ---
> target/riscv/cpu.h | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index b48c7c346c..5f35217f7d 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -106,7 +106,6 @@ FIELD(VTYPE, VLMUL, 0, 2)
> FIELD(VTYPE, VSEW, 2, 3)
> FIELD(VTYPE, VEDIV, 5, 2)
> FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 8)
> -FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
Hmm. It's sorta-kinda documentation. Otherwise we might as well remove RESERVED as well,
and just move the 7 constant into vsetvl.
Either way,
Acked-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3 15/20] target/riscv: Remove VILL field in VTYPE
@ 2021-11-11 11:38 ` Richard Henderson
0 siblings, 0 replies; 72+ messages in thread
From: Richard Henderson @ 2021-11-11 11:38 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel, qemu-riscv; +Cc: Alistair.Francis, palmer, bin.meng
On 11/11/21 6:57 AM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> ---
> target/riscv/cpu.h | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index b48c7c346c..5f35217f7d 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -106,7 +106,6 @@ FIELD(VTYPE, VLMUL, 0, 2)
> FIELD(VTYPE, VSEW, 2, 3)
> FIELD(VTYPE, VEDIV, 5, 2)
> FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 8)
> -FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
Hmm. It's sorta-kinda documentation. Otherwise we might as well remove RESERVED as well,
and just move the 7 constant into vsetvl.
Either way,
Acked-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3 19/20] target/riscv: Adjust scalar reg in vector with XLEN
2021-11-11 5:57 ` LIU Zhiwei
@ 2021-11-11 11:46 ` Richard Henderson
-1 siblings, 0 replies; 72+ messages in thread
From: Richard Henderson @ 2021-11-11 11:46 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel, qemu-riscv; +Cc: palmer, bin.meng, Alistair.Francis
On 11/11/21 6:57 AM, LIU Zhiwei wrote:
> @@ -2670,6 +2672,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
> /* This instruction ignores LMUL and vector register groups */
> int maxsz = s->vlen >> 3;
> TCGv_i64 t1;
> + TCGv src1 = get_gpr(s, a->rs1, EXT_ZERO);
A reminder that this is zero-extend for v0.7.1 and sign-extend for v1.0.0.
> @@ -2679,7 +2682,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
> }
>
> t1 = tcg_temp_new_i64();
> - tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
> + tcg_gen_extu_tl_i64(t1, src1);
Likewise.
> vec_element_storei(s, a->rd, 0, t1);
> tcg_temp_free_i64(t1);
> done:
> @@ -2748,12 +2751,28 @@ static bool slideup_check(DisasContext *s, arg_rmrr *a)
> (a->rd != a->rs2));
> }
>
> +/* OPIVXU without GVEC IR */
> +#define GEN_OPIVXU_TRANS(NAME, CHECK) \
> +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> +{ \
> + if (CHECK(s, a)) { \
> + static gen_helper_opivx * const fns[4] = { \
> + gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
> + gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
> + }; \
> + \
> + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, \
> + fns[s->sew], s, EXT_ZERO); \
> + } \
> + return false; \
> +}
> +
> GEN_OPIVX_TRANS(vslideup_vx, slideup_check)
> -GEN_OPIVX_TRANS(vslide1up_vx, slideup_check)
> +GEN_OPIVXU_TRANS(vslide1up_vx, slideup_check)
> GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx, slideup_check)
>
> GEN_OPIVX_TRANS(vslidedown_vx, opivx_check)
> -GEN_OPIVX_TRANS(vslide1down_vx, opivx_check)
> +GEN_OPIVXU_TRANS(vslide1down_vx, opivx_check)
> GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, opivx_check)
Likewise.
So if this patch set goes in after rvv 1.0, this whole patch may be dropped.
r~
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3 19/20] target/riscv: Adjust scalar reg in vector with XLEN
@ 2021-11-11 11:46 ` Richard Henderson
0 siblings, 0 replies; 72+ messages in thread
From: Richard Henderson @ 2021-11-11 11:46 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel, qemu-riscv; +Cc: Alistair.Francis, palmer, bin.meng
On 11/11/21 6:57 AM, LIU Zhiwei wrote:
> @@ -2670,6 +2672,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
> /* This instruction ignores LMUL and vector register groups */
> int maxsz = s->vlen >> 3;
> TCGv_i64 t1;
> + TCGv src1 = get_gpr(s, a->rs1, EXT_ZERO);
A reminder that this is zero-extend for v0.7.1 and sign-extend for v1.0.0.
> @@ -2679,7 +2682,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
> }
>
> t1 = tcg_temp_new_i64();
> - tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
> + tcg_gen_extu_tl_i64(t1, src1);
Likewise.
> vec_element_storei(s, a->rd, 0, t1);
> tcg_temp_free_i64(t1);
> done:
> @@ -2748,12 +2751,28 @@ static bool slideup_check(DisasContext *s, arg_rmrr *a)
> (a->rd != a->rs2));
> }
>
> +/* OPIVXU without GVEC IR */
> +#define GEN_OPIVXU_TRANS(NAME, CHECK) \
> +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> +{ \
> + if (CHECK(s, a)) { \
> + static gen_helper_opivx * const fns[4] = { \
> + gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
> + gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
> + }; \
> + \
> + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, \
> + fns[s->sew], s, EXT_ZERO); \
> + } \
> + return false; \
> +}
> +
> GEN_OPIVX_TRANS(vslideup_vx, slideup_check)
> -GEN_OPIVX_TRANS(vslide1up_vx, slideup_check)
> +GEN_OPIVXU_TRANS(vslide1up_vx, slideup_check)
> GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx, slideup_check)
>
> GEN_OPIVX_TRANS(vslidedown_vx, opivx_check)
> -GEN_OPIVX_TRANS(vslide1down_vx, opivx_check)
> +GEN_OPIVXU_TRANS(vslide1down_vx, opivx_check)
> GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, opivx_check)
Likewise.
So if this patch set goes in after rvv 1.0, this whole patch may be dropped.
r~
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3 20/20] target/riscv: Enable uxl field write
2021-11-11 5:58 ` LIU Zhiwei
@ 2021-11-11 11:49 ` Richard Henderson
-1 siblings, 0 replies; 72+ messages in thread
From: Richard Henderson @ 2021-11-11 11:49 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel, qemu-riscv; +Cc: palmer, bin.meng, Alistair.Francis
On 11/11/21 6:58 AM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> ---
> target/riscv/csr.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 8f8f170768..43eaa6c710 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -553,15 +553,14 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
> * RV32: MPV and GVA are not in mstatus. The current plan is to
> * add them to mstatush. For now, we just don't support it.
> */
> - mask |= MSTATUS_MPV | MSTATUS_GVA;
> + mask |= MSTATUS_MPV | MSTATUS_GVA | MSTATUS64_UXL;
> }
>
> mstatus = (mstatus & ~mask) | (val & mask);
>
> if (riscv_cpu_mxl(env) == MXL_RV64) {
> - /* SXL and UXL fields are for now read only */
> + /* SXL fields are for now read only */
> mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
> - mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
> }
> env->mstatus = mstatus;
Still missing the update for write_sstatus, which I think is simply an update to
sstatus_v1_10_mask.
r~
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3 20/20] target/riscv: Enable uxl field write
@ 2021-11-11 11:49 ` Richard Henderson
0 siblings, 0 replies; 72+ messages in thread
From: Richard Henderson @ 2021-11-11 11:49 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel, qemu-riscv; +Cc: Alistair.Francis, palmer, bin.meng
On 11/11/21 6:58 AM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> ---
> target/riscv/csr.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 8f8f170768..43eaa6c710 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -553,15 +553,14 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
> * RV32: MPV and GVA are not in mstatus. The current plan is to
> * add them to mstatush. For now, we just don't support it.
> */
> - mask |= MSTATUS_MPV | MSTATUS_GVA;
> + mask |= MSTATUS_MPV | MSTATUS_GVA | MSTATUS64_UXL;
> }
>
> mstatus = (mstatus & ~mask) | (val & mask);
>
> if (riscv_cpu_mxl(env) == MXL_RV64) {
> - /* SXL and UXL fields are for now read only */
> + /* SXL fields are for now read only */
> mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
> - mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
> }
> env->mstatus = mstatus;
Still missing the update for write_sstatus, which I think is simply an update to
sstatus_v1_10_mask.
r~
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3 19/20] target/riscv: Adjust scalar reg in vector with XLEN
2021-11-11 11:46 ` Richard Henderson
@ 2021-11-11 14:43 ` LIU Zhiwei
-1 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 14:43 UTC (permalink / raw)
To: Richard Henderson, qemu-devel, qemu-riscv
Cc: palmer, bin.meng, Alistair.Francis
On 2021/11/11 下午7:46, Richard Henderson wrote:
> On 11/11/21 6:57 AM, LIU Zhiwei wrote:
>> @@ -2670,6 +2672,7 @@ static bool trans_vmv_s_x(DisasContext *s,
>> arg_vmv_s_x *a)
>> /* This instruction ignores LMUL and vector register groups */
>> int maxsz = s->vlen >> 3;
>> TCGv_i64 t1;
>> + TCGv src1 = get_gpr(s, a->rs1, EXT_ZERO);
>
> A reminder that this is zero-extend for v0.7.1 and sign-extend for
> v1.0.0.
>
>> @@ -2679,7 +2682,7 @@ static bool trans_vmv_s_x(DisasContext *s,
>> arg_vmv_s_x *a)
>> }
>> t1 = tcg_temp_new_i64();
>> - tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
>> + tcg_gen_extu_tl_i64(t1, src1);
>
> Likewise.
>
>> vec_element_storei(s, a->rd, 0, t1);
>> tcg_temp_free_i64(t1);
>> done:
>> @@ -2748,12 +2751,28 @@ static bool slideup_check(DisasContext *s,
>> arg_rmrr *a)
>> (a->rd != a->rs2));
>> }
>> +/* OPIVXU without GVEC IR */
>> +#define GEN_OPIVXU_TRANS(NAME,
>> CHECK) \
>> +static bool trans_##NAME(DisasContext *s, arg_rmrr
>> *a) \
>> +{ \
>> + if (CHECK(s, a))
>> { \
>> + static gen_helper_opivx * const fns[4] =
>> { \
>> + gen_helper_##NAME##_b,
>> gen_helper_##NAME##_h, \
>> + gen_helper_##NAME##_w,
>> gen_helper_##NAME##_d, \
>> + }; \
>> + \
>> + return opivx_trans(a->rd, a->rs1, a->rs2,
>> a->vm, \
>> + fns[s->sew], s,
>> EXT_ZERO); \
>> + } \
>> + return
>> false; \
>> +}
>> +
>> GEN_OPIVX_TRANS(vslideup_vx, slideup_check)
>> -GEN_OPIVX_TRANS(vslide1up_vx, slideup_check)
>> +GEN_OPIVXU_TRANS(vslide1up_vx, slideup_check)
>> GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx, slideup_check)
>> GEN_OPIVX_TRANS(vslidedown_vx, opivx_check)
>> -GEN_OPIVX_TRANS(vslide1down_vx, opivx_check)
>> +GEN_OPIVXU_TRANS(vslide1down_vx, opivx_check)
>> GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, opivx_check)
>
> Likewise.
>
> So if this patch set goes in after rvv 1.0, this whole patch may be
> dropped.
>
Got it.
Thanks,
Zhiwei
>
> r~
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3 19/20] target/riscv: Adjust scalar reg in vector with XLEN
@ 2021-11-11 14:43 ` LIU Zhiwei
0 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11 14:43 UTC (permalink / raw)
To: Richard Henderson, qemu-devel, qemu-riscv
Cc: Alistair.Francis, palmer, bin.meng
On 2021/11/11 下午7:46, Richard Henderson wrote:
> On 11/11/21 6:57 AM, LIU Zhiwei wrote:
>> @@ -2670,6 +2672,7 @@ static bool trans_vmv_s_x(DisasContext *s,
>> arg_vmv_s_x *a)
>> /* This instruction ignores LMUL and vector register groups */
>> int maxsz = s->vlen >> 3;
>> TCGv_i64 t1;
>> + TCGv src1 = get_gpr(s, a->rs1, EXT_ZERO);
>
> A reminder that this is zero-extend for v0.7.1 and sign-extend for
> v1.0.0.
>
>> @@ -2679,7 +2682,7 @@ static bool trans_vmv_s_x(DisasContext *s,
>> arg_vmv_s_x *a)
>> }
>> t1 = tcg_temp_new_i64();
>> - tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
>> + tcg_gen_extu_tl_i64(t1, src1);
>
> Likewise.
>
>> vec_element_storei(s, a->rd, 0, t1);
>> tcg_temp_free_i64(t1);
>> done:
>> @@ -2748,12 +2751,28 @@ static bool slideup_check(DisasContext *s,
>> arg_rmrr *a)
>> (a->rd != a->rs2));
>> }
>> +/* OPIVXU without GVEC IR */
>> +#define GEN_OPIVXU_TRANS(NAME,
>> CHECK) \
>> +static bool trans_##NAME(DisasContext *s, arg_rmrr
>> *a) \
>> +{ \
>> + if (CHECK(s, a))
>> { \
>> + static gen_helper_opivx * const fns[4] =
>> { \
>> + gen_helper_##NAME##_b,
>> gen_helper_##NAME##_h, \
>> + gen_helper_##NAME##_w,
>> gen_helper_##NAME##_d, \
>> + }; \
>> + \
>> + return opivx_trans(a->rd, a->rs1, a->rs2,
>> a->vm, \
>> + fns[s->sew], s,
>> EXT_ZERO); \
>> + } \
>> + return
>> false; \
>> +}
>> +
>> GEN_OPIVX_TRANS(vslideup_vx, slideup_check)
>> -GEN_OPIVX_TRANS(vslide1up_vx, slideup_check)
>> +GEN_OPIVXU_TRANS(vslide1up_vx, slideup_check)
>> GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx, slideup_check)
>> GEN_OPIVX_TRANS(vslidedown_vx, opivx_check)
>> -GEN_OPIVX_TRANS(vslide1down_vx, opivx_check)
>> +GEN_OPIVXU_TRANS(vslide1down_vx, opivx_check)
>> GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, opivx_check)
>
> Likewise.
>
> So if this patch set goes in after rvv 1.0, this whole patch may be
> dropped.
>
Got it.
Thanks,
Zhiwei
>
> r~
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3 20/20] target/riscv: Enable uxl field write
2021-11-11 11:49 ` Richard Henderson
@ 2021-11-11 15:18 ` Frédéric Pétrot
-1 siblings, 0 replies; 72+ messages in thread
From: Frédéric Pétrot @ 2021-11-11 15:18 UTC (permalink / raw)
To: Richard Henderson, LIU Zhiwei, qemu-devel, qemu-riscv
Cc: Alistair.Francis, bin.meng, palmer
On 11/11/2021 12:49, Richard Henderson wrote:
> On 11/11/21 6:58 AM, LIU Zhiwei wrote:
>> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
>> ---
>> target/riscv/csr.c | 5 ++---
>> 1 file changed, 2 insertions(+), 3 deletions(-)
>>
>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
>> index 8f8f170768..43eaa6c710 100644
>> --- a/target/riscv/csr.c
>> +++ b/target/riscv/csr.c
>> @@ -553,15 +553,14 @@ static RISCVException write_mstatus(CPURISCVState *env,
>> int csrno,
>> * RV32: MPV and GVA are not in mstatus. The current plan is to
>> * add them to mstatush. For now, we just don't support it.
>> */
>> - mask |= MSTATUS_MPV | MSTATUS_GVA;
>> + mask |= MSTATUS_MPV | MSTATUS_GVA | MSTATUS64_UXL;
>> }
>> mstatus = (mstatus & ~mask) | (val & mask);
>> if (riscv_cpu_mxl(env) == MXL_RV64) {
>> - /* SXL and UXL fields are for now read only */
>> + /* SXL fields are for now read only */
>> mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
>> - mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
>> }
>> env->mstatus = mstatus;
>
> Still missing the update for write_sstatus, which I think is simply an update to
> sstatus_v1_10_mask.
I take the liberty to jump in as I face the issue of updating that mask in the
128-bit patches: sstatus_v1_10_mask is a target_ulong, and when compiling for
32-bit hosts, we can't just or it with MSTATUS64_S/UXL that lie above the
32-bit limits.
I am currently oring in write_sstatus using a uint64_t mask, but this is not
so nice.
What solution would be best in your opinion ?
Thanks,
Frédéric
>
>
> r~
>
>
--
+---------------------------------------------------------------------------+
| Frédéric Pétrot, Pr. Grenoble INP-Ensimag/TIMA, Ensimag deputy director |
| Mob/Pho: +33 6 74 57 99 65/+33 4 76 57 48 70 Ad augusta per angusta |
| http://tima.univ-grenoble-alpes.fr frederic.petrot@univ-grenoble-alpes.fr |
+---------------------------------------------------------------------------+
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3 20/20] target/riscv: Enable uxl field write
@ 2021-11-11 15:18 ` Frédéric Pétrot
0 siblings, 0 replies; 72+ messages in thread
From: Frédéric Pétrot @ 2021-11-11 15:18 UTC (permalink / raw)
To: Richard Henderson, LIU Zhiwei, qemu-devel, qemu-riscv
Cc: palmer, bin.meng, Alistair.Francis
On 11/11/2021 12:49, Richard Henderson wrote:
> On 11/11/21 6:58 AM, LIU Zhiwei wrote:
>> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
>> ---
>> target/riscv/csr.c | 5 ++---
>> 1 file changed, 2 insertions(+), 3 deletions(-)
>>
>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
>> index 8f8f170768..43eaa6c710 100644
>> --- a/target/riscv/csr.c
>> +++ b/target/riscv/csr.c
>> @@ -553,15 +553,14 @@ static RISCVException write_mstatus(CPURISCVState *env,
>> int csrno,
>> * RV32: MPV and GVA are not in mstatus. The current plan is to
>> * add them to mstatush. For now, we just don't support it.
>> */
>> - mask |= MSTATUS_MPV | MSTATUS_GVA;
>> + mask |= MSTATUS_MPV | MSTATUS_GVA | MSTATUS64_UXL;
>> }
>> mstatus = (mstatus & ~mask) | (val & mask);
>> if (riscv_cpu_mxl(env) == MXL_RV64) {
>> - /* SXL and UXL fields are for now read only */
>> + /* SXL fields are for now read only */
>> mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
>> - mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
>> }
>> env->mstatus = mstatus;
>
> Still missing the update for write_sstatus, which I think is simply an update to
> sstatus_v1_10_mask.
I take the liberty to jump in as I face the issue of updating that mask in the
128-bit patches: sstatus_v1_10_mask is a target_ulong, and when compiling for
32-bit hosts, we can't just or it with MSTATUS64_S/UXL that lie above the
32-bit limits.
I am currently oring in write_sstatus using a uint64_t mask, but this is not
so nice.
What solution would be best in your opinion ?
Thanks,
Frédéric
>
>
> r~
>
>
--
+---------------------------------------------------------------------------+
| Frédéric Pétrot, Pr. Grenoble INP-Ensimag/TIMA, Ensimag deputy director |
| Mob/Pho: +33 6 74 57 99 65/+33 4 76 57 48 70 Ad augusta per angusta |
| http://tima.univ-grenoble-alpes.fr frederic.petrot@univ-grenoble-alpes.fr |
+---------------------------------------------------------------------------+
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3 20/20] target/riscv: Enable uxl field write
2021-11-11 15:18 ` Frédéric Pétrot
@ 2021-11-11 18:20 ` Richard Henderson
-1 siblings, 0 replies; 72+ messages in thread
From: Richard Henderson @ 2021-11-11 18:20 UTC (permalink / raw)
To: Frédéric Pétrot, LIU Zhiwei, qemu-devel, qemu-riscv
Cc: Alistair.Francis, bin.meng, palmer
On 11/11/21 4:18 PM, Frédéric Pétrot wrote:
>> Still missing the update for write_sstatus, which I think is simply an update to
>> sstatus_v1_10_mask.
>
> I take the liberty to jump in as I face the issue of updating that mask in the
> 128-bit patches: sstatus_v1_10_mask is a target_ulong, and when compiling for
> 32-bit hosts, we can't just or it with MSTATUS64_S/UXL that lie above the
> 32-bit limits.
Surely (target_ulong)MSTATUS64_UXL will properly produce 0 when oring into
sstatus_v1_10_mask? Which is correct for an RV32-only build.
r~
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3 20/20] target/riscv: Enable uxl field write
@ 2021-11-11 18:20 ` Richard Henderson
0 siblings, 0 replies; 72+ messages in thread
From: Richard Henderson @ 2021-11-11 18:20 UTC (permalink / raw)
To: Frédéric Pétrot, LIU Zhiwei, qemu-devel, qemu-riscv
Cc: palmer, bin.meng, Alistair.Francis
On 11/11/21 4:18 PM, Frédéric Pétrot wrote:
>> Still missing the update for write_sstatus, which I think is simply an update to
>> sstatus_v1_10_mask.
>
> I take the liberty to jump in as I face the issue of updating that mask in the
> 128-bit patches: sstatus_v1_10_mask is a target_ulong, and when compiling for
> 32-bit hosts, we can't just or it with MSTATUS64_S/UXL that lie above the
> 32-bit limits.
Surely (target_ulong)MSTATUS64_UXL will properly produce 0 when oring into
sstatus_v1_10_mask? Which is correct for an RV32-only build.
r~
^ permalink raw reply [flat|nested] 72+ messages in thread
end of thread, other threads:[~2021-11-11 18:21 UTC | newest]
Thread overview: 72+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-11-11 5:57 [PATCH v3 00/20] Support UXL filed in xstatus LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 01/20] target/riscv: Don't save pc when exception return LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 02/20] target/riscv: Sign extend pc for different XLEN LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 03/20] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 04/20] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 11:19 ` Richard Henderson
2021-11-11 11:19 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 05/20] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 06/20] target/riscv: Relax debug check for pm write LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 07/20] target/riscv: Adjust csr write mask with XLEN LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 11:21 ` Richard Henderson
2021-11-11 11:21 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 08/20] target/riscv: Create current pm fields in env LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 09/20] target/riscv: Alloc tcg global for cur_pm[mask|base] LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 11:26 ` Richard Henderson
2021-11-11 11:26 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 10/20] target/riscv: Calculate address according to XLEN LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 11:28 ` Richard Henderson
2021-11-11 11:28 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 11/20] target/riscv: Split pm_enabled into mask and base LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 11:29 ` Richard Henderson
2021-11-11 11:29 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 12/20] target/riscv: Split out the vill from vtype LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 11:31 ` Richard Henderson
2021-11-11 11:31 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 13/20] target/riscv: Fix RESERVED field length in VTYPE LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 11:33 ` Richard Henderson
2021-11-11 11:33 ` Richard Henderson
2021-11-11 11:33 ` Richard Henderson
2021-11-11 11:33 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 14/20] target/riscv: Adjust vsetvl according to XLEN LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 11:35 ` Richard Henderson
2021-11-11 11:35 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 15/20] target/riscv: Remove VILL field in VTYPE LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 11:38 ` Richard Henderson
2021-11-11 11:38 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 16/20] target/riscv: Ajdust vector atomic check with XLEN LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 17/20] target/riscv: Fix check range for first fault only LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 18/20] target/riscv: Adjust vector address with mask LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 19/20] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 11:46 ` Richard Henderson
2021-11-11 11:46 ` Richard Henderson
2021-11-11 14:43 ` LIU Zhiwei
2021-11-11 14:43 ` LIU Zhiwei
2021-11-11 5:58 ` [PATCH v3 20/20] target/riscv: Enable uxl field write LIU Zhiwei
2021-11-11 5:58 ` LIU Zhiwei
2021-11-11 11:49 ` Richard Henderson
2021-11-11 11:49 ` Richard Henderson
2021-11-11 15:18 ` Frédéric Pétrot
2021-11-11 15:18 ` Frédéric Pétrot
2021-11-11 18:20 ` Richard Henderson
2021-11-11 18:20 ` Richard Henderson
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.