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[88.21.205.47]) by smtp.gmail.com with ESMTPSA id q5sm819266edw.34.2020.03.05.02.18.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Mar 2020 02:18:32 -0800 (PST) Subject: Re: [PATCH v1] mips/mips_malta: Allow more than 2G RAM To: Jiaxun Yang , qemu-devel@nongnu.org, Paul Burton References: <20200228032613.1049955-1-jiaxun.yang@flygoat.com> <20200303004137.1099502-1-jiaxun.yang@flygoat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <6b4a7564-eac6-7bd3-b1c0-e9c7ac4e0c80@redhat.com> Date: Thu, 5 Mar 2020 11:18:30 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20200303004137.1099502-1-jiaxun.yang@flygoat.com> Content-Language: en-US X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: imammedo@redhat.com, Paul Burton , Yunqiang Su , amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Please post new patches as v2, and do not post them as reply to v1. On 3/3/20 1:41 AM, Jiaxun Yang wrote: > When malta is coupled with MIPS64 cpu which have 64bit > address space, it is possible to have more than 2G RAM. >=20 > So we removed ram_size check and overwrite memory > layout for these targets. >=20 > Signed-off-by: Jiaxun Yang > Suggested-by: Yunqiang Su > -- > v1: Do not overwrite cmdline when we don't have highmem. > --- > hw/mips/mips_malta.c | 29 +++++++++++++++++++++++------ > 1 file changed, 23 insertions(+), 6 deletions(-) >=20 > diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c > index 6e7ba9235d..4267958f35 100644 > --- a/hw/mips/mips_malta.c > +++ b/hw/mips/mips_malta.c > @@ -98,7 +98,8 @@ typedef struct { > } MaltaState; > =20 > static struct _loaderparams { > - int ram_size, ram_low_size; > + unsigned int ram_low_size; > + ram_addr_t ram_size; > const char *kernel_filename; > const char *kernel_cmdline; > const char *initrd_filename; > @@ -1023,6 +1024,7 @@ static int64_t load_kernel(void) > { > int64_t kernel_entry, kernel_high, initrd_size; > long kernel_size; > + char mem_cmdline[128]; > ram_addr_t initrd_offset; > int big_endian; > uint32_t *prom_buf; > @@ -1099,20 +1101,33 @@ static int64_t load_kernel(void) > prom_buf =3D g_malloc(prom_size); > =20 > prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename= ); > + > + memset(&mem_cmdline[0], 0, sizeof(mem_cmdline)); > + if (loaderparams.ram_size > 0x10000000) { Please use 256 * MiB. > + /* > + * Always use cmdline to overwrite mem layout > + * as kernel may reject large emesize. > + */ > + sprintf(&mem_cmdline[0], > + "mem=3D0x10000000@0x00000000 mem=3D0x%" PRIx64 "@0x90000= 000", > + loaderparams.ram_size - 0x10000000); Ditto. Also please use g_strdup_printf("mem=3D0x%" PRIx64 "@...")/g_free. > + } > + > if (initrd_size > 0) { > prom_set(prom_buf, prom_index++, > - "rd_start=3D0x%" PRIx64 " rd_size=3D%" PRId64 " %s", > - xlate_to_kseg0(NULL, initrd_offset), > + "%s rd_start=3D0x%" PRIx64 " rd_size=3D%" PRId64 " %s", > + &mem_cmdline[0], xlate_to_kseg0(NULL, initrd_offset), > initrd_size, loaderparams.kernel_cmdline); > } else { > - prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdli= ne); > + prom_set(prom_buf, prom_index++, "%s %s", &mem_cmdline[0], > + loaderparams.kernel_cmdline); > } > =20 > prom_set(prom_buf, prom_index++, "memsize"); > prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_low_size); > =20 > prom_set(prom_buf, prom_index++, "ememsize"); > - prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_size); > + prom_set(prom_buf, prom_index++, "%lu", loaderparams.ram_size); > =20 > prom_set(prom_buf, prom_index++, "modetty0"); > prom_set(prom_buf, prom_index++, "38400n8r"); > @@ -1253,12 +1268,14 @@ void mips_malta_init(MachineState *machine) > /* create CPU */ > mips_create_cpu(machine, s, &cbus_irq, &i8259_irq); > =20 > - /* allocate RAM */ > +#ifdef TARGET_MIPS32 > + /* MIPS32 won't accept more than 2GiB RAM due to limited address spa= ce */ Cc'ing Paul Burton due to commit 94c2b6aff43. > if (ram_size > 2 * GiB) { > error_report("Too much memory for this machine: %" PRId64 "MB," > " maximum 2048MB", ram_size / MiB); This is annoying, because the CoreLV/CoreFPGA core cards only have 4=20 DIMM slots for PC-100 SDRAM, and the Memory Controller of the GT=E2=80=9364= 120A=20 north bridge accept at most 256 MiB per SCS for address decoding, so we=20 have a maximum of 1 GiB on 32-bit boards. In 64-bit emulation we use the a 20Kc core, provided by the Core20K core=20 card which doesn't use the GT=E2=80=9364120A but the Bonito64. So the model= is=20 incorrect... The Bonito64 indeed allow more memory. Maybe it is time to consider that for 64-bit targets, since we are not=20 modelling a Malta core board, we can name it the official 'virt' machine... > exit(1); > } > +#endif > =20 > /* register RAM at high address where it is undisturbed by IO */ > memory_region_add_subregion(system_memory, 0x80000000, machine->ram= ); >=20