* [PATCH v3 00/10] RISC-V: Steps towards running 32-bit guests on
@ 2021-04-24 3:28 ` Alistair Francis
0 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-24 3:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, bmeng.cn, palmer, alistair23
This is another step towards running 32-bit CPU code on the 64-bit
softmmu builds for RISC-V.
I have tested this and am able to run some 32-bit code, but eventually
hit some issue. This series doesn't allow users to use 32-bit CPUs with
64-bit softmmu builds as it doesn't work yet. This series instead just
gets us a little closer to being able to and removes more hardcoded
macros so hopefully others also stop using them for new code.
v3:
- Remove casts from the decoder
- Add a patch to fix a comment
- Rebase on the RISC-V tree
v2:
- Update the decode tree setup
- Address other review comments
Alistair Francis (10):
target/riscv: Remove the hardcoded RVXLEN macro
target/riscv: Remove the hardcoded SSTATUS_SD macro
target/riscv: Remove the hardcoded HGATP_MODE macro
target/riscv: Remove the hardcoded MSTATUS_SD macro
target/riscv: Remove the hardcoded SATP_MODE macro
target/riscv: Remove the unused HSTATUS_WPRI macro
target/riscv: Remove an unused CASE_OP_32_64 macro
target/riscv: Consolidate RV32/64 32-bit instructions
target/riscv: Consolidate RV32/64 16-bit instructions
target/riscv: Fix the RV64H decode comment
target/riscv/cpu.h | 6 --
target/riscv/cpu_bits.h | 44 -------------
target/riscv/helper.h | 18 +++--
target/riscv/insn16-32.decode | 28 --------
target/riscv/insn16-64.decode | 36 ----------
target/riscv/insn16.decode | 30 +++++++++
target/riscv/insn32-64.decode | 88 -------------------------
target/riscv/insn32.decode | 67 ++++++++++++++++++-
target/riscv/cpu.c | 6 +-
target/riscv/cpu_helper.c | 48 ++++++++++----
target/riscv/csr.c | 40 +++++++++--
target/riscv/fpu_helper.c | 16 ++---
target/riscv/monitor.c | 22 +++++--
target/riscv/translate.c | 32 +++++----
target/riscv/vector_helper.c | 4 --
target/riscv/insn_trans/trans_rva.c.inc | 14 +++-
target/riscv/insn_trans/trans_rvd.c.inc | 17 ++++-
target/riscv/insn_trans/trans_rvf.c.inc | 6 +-
target/riscv/insn_trans/trans_rvh.c.inc | 8 ++-
target/riscv/insn_trans/trans_rvi.c.inc | 22 +++++--
target/riscv/insn_trans/trans_rvm.c.inc | 12 +++-
target/riscv/insn_trans/trans_rvv.c.inc | 39 +++++------
target/riscv/meson.build | 13 ++--
23 files changed, 310 insertions(+), 306 deletions(-)
delete mode 100644 target/riscv/insn16-32.decode
delete mode 100644 target/riscv/insn16-64.decode
delete mode 100644 target/riscv/insn32-64.decode
--
2.31.1
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v3 00/10] RISC-V: Steps towards running 32-bit guests on
@ 2021-04-24 3:28 ` Alistair Francis
0 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-24 3:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
This is another step towards running 32-bit CPU code on the 64-bit
softmmu builds for RISC-V.
I have tested this and am able to run some 32-bit code, but eventually
hit some issue. This series doesn't allow users to use 32-bit CPUs with
64-bit softmmu builds as it doesn't work yet. This series instead just
gets us a little closer to being able to and removes more hardcoded
macros so hopefully others also stop using them for new code.
v3:
- Remove casts from the decoder
- Add a patch to fix a comment
- Rebase on the RISC-V tree
v2:
- Update the decode tree setup
- Address other review comments
Alistair Francis (10):
target/riscv: Remove the hardcoded RVXLEN macro
target/riscv: Remove the hardcoded SSTATUS_SD macro
target/riscv: Remove the hardcoded HGATP_MODE macro
target/riscv: Remove the hardcoded MSTATUS_SD macro
target/riscv: Remove the hardcoded SATP_MODE macro
target/riscv: Remove the unused HSTATUS_WPRI macro
target/riscv: Remove an unused CASE_OP_32_64 macro
target/riscv: Consolidate RV32/64 32-bit instructions
target/riscv: Consolidate RV32/64 16-bit instructions
target/riscv: Fix the RV64H decode comment
target/riscv/cpu.h | 6 --
target/riscv/cpu_bits.h | 44 -------------
target/riscv/helper.h | 18 +++--
target/riscv/insn16-32.decode | 28 --------
target/riscv/insn16-64.decode | 36 ----------
target/riscv/insn16.decode | 30 +++++++++
target/riscv/insn32-64.decode | 88 -------------------------
target/riscv/insn32.decode | 67 ++++++++++++++++++-
target/riscv/cpu.c | 6 +-
target/riscv/cpu_helper.c | 48 ++++++++++----
target/riscv/csr.c | 40 +++++++++--
target/riscv/fpu_helper.c | 16 ++---
target/riscv/monitor.c | 22 +++++--
target/riscv/translate.c | 32 +++++----
target/riscv/vector_helper.c | 4 --
target/riscv/insn_trans/trans_rva.c.inc | 14 +++-
target/riscv/insn_trans/trans_rvd.c.inc | 17 ++++-
target/riscv/insn_trans/trans_rvf.c.inc | 6 +-
target/riscv/insn_trans/trans_rvh.c.inc | 8 ++-
target/riscv/insn_trans/trans_rvi.c.inc | 22 +++++--
target/riscv/insn_trans/trans_rvm.c.inc | 12 +++-
target/riscv/insn_trans/trans_rvv.c.inc | 39 +++++------
target/riscv/meson.build | 13 ++--
23 files changed, 310 insertions(+), 306 deletions(-)
delete mode 100644 target/riscv/insn16-32.decode
delete mode 100644 target/riscv/insn16-64.decode
delete mode 100644 target/riscv/insn32-64.decode
--
2.31.1
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v3 01/10] target/riscv: Remove the hardcoded RVXLEN macro
2021-04-24 3:28 ` Alistair Francis
@ 2021-04-24 3:28 ` Alistair Francis
-1 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-24 3:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, bmeng.cn, palmer, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
target/riscv/cpu.h | 6 ------
target/riscv/cpu.c | 6 +++++-
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index add734bbbd..7e879fb9ca 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -54,12 +54,6 @@
#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
-#if defined(TARGET_RISCV32)
-#define RVXLEN RV32
-#elif defined(TARGET_RISCV64)
-#define RVXLEN RV64
-#endif
-
#define RV(x) ((target_ulong)1 << (x - 'A'))
#define RVI RV('I')
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 04ac03f8c9..3191fd0082 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -147,7 +147,11 @@ static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
static void riscv_any_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
- set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+#if defined(TARGET_RISCV32)
+ set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+#elif defined(TARGET_RISCV64)
+ set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+#endif
set_priv_version(env, PRIV_VERSION_1_11_0);
}
--
2.31.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 01/10] target/riscv: Remove the hardcoded RVXLEN macro
@ 2021-04-24 3:28 ` Alistair Francis
0 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-24 3:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
target/riscv/cpu.h | 6 ------
target/riscv/cpu.c | 6 +++++-
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index add734bbbd..7e879fb9ca 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -54,12 +54,6 @@
#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
-#if defined(TARGET_RISCV32)
-#define RVXLEN RV32
-#elif defined(TARGET_RISCV64)
-#define RVXLEN RV64
-#endif
-
#define RV(x) ((target_ulong)1 << (x - 'A'))
#define RVI RV('I')
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 04ac03f8c9..3191fd0082 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -147,7 +147,11 @@ static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
static void riscv_any_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
- set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+#if defined(TARGET_RISCV32)
+ set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+#elif defined(TARGET_RISCV64)
+ set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+#endif
set_priv_version(env, PRIV_VERSION_1_11_0);
}
--
2.31.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 02/10] target/riscv: Remove the hardcoded SSTATUS_SD macro
2021-04-24 3:28 ` Alistair Francis
@ 2021-04-24 3:29 ` Alistair Francis
-1 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-24 3:29 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, bmeng.cn, palmer, alistair23
This also ensures that the SD bit is not writable.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
target/riscv/cpu_bits.h | 6 ------
target/riscv/csr.c | 9 ++++++++-
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 24d89939a0..3a0e79e545 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -403,12 +403,6 @@
#define SSTATUS32_SD 0x80000000
#define SSTATUS64_SD 0x8000000000000000ULL
-#if defined(TARGET_RISCV32)
-#define SSTATUS_SD SSTATUS32_SD
-#elif defined(TARGET_RISCV64)
-#define SSTATUS_SD SSTATUS64_SD
-#endif
-
/* hstatus CSR bits */
#define HSTATUS_VSBE 0x00000020
#define HSTATUS_GVA 0x00000040
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 97ceff718f..41951a0a84 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -459,7 +459,7 @@ static const target_ulong delegable_excps =
(1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
- SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
+ SSTATUS_SUM | SSTATUS_MXR;
static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
static const target_ulong hip_writable_mask = MIP_VSSIP;
static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
@@ -788,6 +788,13 @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno,
target_ulong *val)
{
target_ulong mask = (sstatus_v1_10_mask);
+
+ if (riscv_cpu_is_32bit(env)) {
+ mask |= SSTATUS32_SD;
+ } else {
+ mask |= SSTATUS64_SD;
+ }
+
*val = env->mstatus & mask;
return RISCV_EXCP_NONE;
}
--
2.31.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 02/10] target/riscv: Remove the hardcoded SSTATUS_SD macro
@ 2021-04-24 3:29 ` Alistair Francis
0 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-24 3:29 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
This also ensures that the SD bit is not writable.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
target/riscv/cpu_bits.h | 6 ------
target/riscv/csr.c | 9 ++++++++-
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 24d89939a0..3a0e79e545 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -403,12 +403,6 @@
#define SSTATUS32_SD 0x80000000
#define SSTATUS64_SD 0x8000000000000000ULL
-#if defined(TARGET_RISCV32)
-#define SSTATUS_SD SSTATUS32_SD
-#elif defined(TARGET_RISCV64)
-#define SSTATUS_SD SSTATUS64_SD
-#endif
-
/* hstatus CSR bits */
#define HSTATUS_VSBE 0x00000020
#define HSTATUS_GVA 0x00000040
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 97ceff718f..41951a0a84 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -459,7 +459,7 @@ static const target_ulong delegable_excps =
(1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
- SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
+ SSTATUS_SUM | SSTATUS_MXR;
static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
static const target_ulong hip_writable_mask = MIP_VSSIP;
static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
@@ -788,6 +788,13 @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno,
target_ulong *val)
{
target_ulong mask = (sstatus_v1_10_mask);
+
+ if (riscv_cpu_is_32bit(env)) {
+ mask |= SSTATUS32_SD;
+ } else {
+ mask |= SSTATUS64_SD;
+ }
+
*val = env->mstatus & mask;
return RISCV_EXCP_NONE;
}
--
2.31.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 03/10] target/riscv: Remove the hardcoded HGATP_MODE macro
2021-04-24 3:28 ` Alistair Francis
@ 2021-04-24 3:31 ` Alistair Francis
-1 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-24 3:31 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, bmeng.cn, palmer, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
target/riscv/cpu_bits.h | 11 -----------
target/riscv/cpu_helper.c | 24 +++++++++++++++---------
2 files changed, 15 insertions(+), 20 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 3a0e79e545..d738e2fdbd 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -195,17 +195,6 @@
#define CSR_HTIMEDELTA 0x605
#define CSR_HTIMEDELTAH 0x615
-#if defined(TARGET_RISCV32)
-#define HGATP_MODE SATP32_MODE
-#define HGATP_VMID SATP32_ASID
-#define HGATP_PPN SATP32_PPN
-#endif
-#if defined(TARGET_RISCV64)
-#define HGATP_MODE SATP64_MODE
-#define HGATP_VMID SATP64_ASID
-#define HGATP_PPN SATP64_PPN
-#endif
-
/* Virtual CSRs */
#define CSR_VSSTATUS 0x200
#define CSR_VSIE 0x204
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 1018c0036d..d9defbdd34 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -413,8 +413,13 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
}
widened = 0;
} else {
- base = (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT;
- vm = get_field(env->hgatp, HGATP_MODE);
+ if (riscv_cpu_is_32bit(env)) {
+ base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT;
+ vm = get_field(env->hgatp, SATP32_MODE);
+ } else {
+ base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT;
+ vm = get_field(env->hgatp, SATP64_MODE);
+ }
widened = 2;
}
/* status.SUM will be ignored if execute on background */
@@ -618,16 +623,17 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
bool first_stage, bool two_stage)
{
CPUState *cs = env_cpu(env);
- int page_fault_exceptions;
+ int page_fault_exceptions, vm;
+
if (first_stage) {
- page_fault_exceptions =
- get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
- !pmp_violation;
+ vm = get_field(env->satp, SATP_MODE);
+ } else if (riscv_cpu_is_32bit(env)) {
+ vm = get_field(env->hgatp, SATP32_MODE);
} else {
- page_fault_exceptions =
- get_field(env->hgatp, HGATP_MODE) != VM_1_10_MBARE &&
- !pmp_violation;
+ vm = get_field(env->hgatp, SATP64_MODE);
}
+ page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation;
+
switch (access_type) {
case MMU_INST_FETCH:
if (riscv_cpu_virt_enabled(env) && !first_stage) {
--
2.31.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 03/10] target/riscv: Remove the hardcoded HGATP_MODE macro
@ 2021-04-24 3:31 ` Alistair Francis
0 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-24 3:31 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
target/riscv/cpu_bits.h | 11 -----------
target/riscv/cpu_helper.c | 24 +++++++++++++++---------
2 files changed, 15 insertions(+), 20 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 3a0e79e545..d738e2fdbd 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -195,17 +195,6 @@
#define CSR_HTIMEDELTA 0x605
#define CSR_HTIMEDELTAH 0x615
-#if defined(TARGET_RISCV32)
-#define HGATP_MODE SATP32_MODE
-#define HGATP_VMID SATP32_ASID
-#define HGATP_PPN SATP32_PPN
-#endif
-#if defined(TARGET_RISCV64)
-#define HGATP_MODE SATP64_MODE
-#define HGATP_VMID SATP64_ASID
-#define HGATP_PPN SATP64_PPN
-#endif
-
/* Virtual CSRs */
#define CSR_VSSTATUS 0x200
#define CSR_VSIE 0x204
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 1018c0036d..d9defbdd34 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -413,8 +413,13 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
}
widened = 0;
} else {
- base = (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT;
- vm = get_field(env->hgatp, HGATP_MODE);
+ if (riscv_cpu_is_32bit(env)) {
+ base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT;
+ vm = get_field(env->hgatp, SATP32_MODE);
+ } else {
+ base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT;
+ vm = get_field(env->hgatp, SATP64_MODE);
+ }
widened = 2;
}
/* status.SUM will be ignored if execute on background */
@@ -618,16 +623,17 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
bool first_stage, bool two_stage)
{
CPUState *cs = env_cpu(env);
- int page_fault_exceptions;
+ int page_fault_exceptions, vm;
+
if (first_stage) {
- page_fault_exceptions =
- get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
- !pmp_violation;
+ vm = get_field(env->satp, SATP_MODE);
+ } else if (riscv_cpu_is_32bit(env)) {
+ vm = get_field(env->hgatp, SATP32_MODE);
} else {
- page_fault_exceptions =
- get_field(env->hgatp, HGATP_MODE) != VM_1_10_MBARE &&
- !pmp_violation;
+ vm = get_field(env->hgatp, SATP64_MODE);
}
+ page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation;
+
switch (access_type) {
case MMU_INST_FETCH:
if (riscv_cpu_virt_enabled(env) && !first_stage) {
--
2.31.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 04/10] target/riscv: Remove the hardcoded MSTATUS_SD macro
2021-04-24 3:28 ` Alistair Francis
@ 2021-04-24 3:33 ` Alistair Francis
-1 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-24 3:33 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, bmeng.cn, palmer, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu_bits.h | 10 ----------
target/riscv/csr.c | 12 ++++++++++--
target/riscv/translate.c | 19 +++++++++++++++++--
3 files changed, 27 insertions(+), 14 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index d738e2fdbd..6e30b312f0 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -368,16 +368,6 @@
#define MXL_RV64 2
#define MXL_RV128 3
-#if defined(TARGET_RISCV32)
-#define MSTATUS_SD MSTATUS32_SD
-#define MISA_MXL MISA32_MXL
-#define MXL_VAL MXL_RV32
-#elif defined(TARGET_RISCV64)
-#define MSTATUS_SD MSTATUS64_SD
-#define MISA_MXL MISA64_MXL
-#define MXL_VAL MXL_RV64
-#endif
-
/* sstatus CSR bits */
#define SSTATUS_UIE 0x00000001
#define SSTATUS_SIE 0x00000002
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 41951a0a84..e955753441 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -538,7 +538,11 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
((mstatus & MSTATUS_XS) == MSTATUS_XS);
- mstatus = set_field(mstatus, MSTATUS_SD, dirty);
+ if (riscv_cpu_is_32bit(env)) {
+ mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
+ } else {
+ mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
+ }
env->mstatus = mstatus;
return RISCV_EXCP_NONE;
@@ -614,7 +618,11 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
}
/* misa.MXL writes are not supported by QEMU */
- val = (env->misa & MISA_MXL) | (val & ~MISA_MXL);
+ if (riscv_cpu_is_32bit(env)) {
+ val = (env->misa & MISA32_MXL) | (val & ~MISA32_MXL);
+ } else {
+ val = (env->misa & MISA64_MXL) | (val & ~MISA64_MXL);
+ }
/* flush translation cache */
if (val != env->misa) {
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 26eccc5eb1..a596f80f20 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -78,6 +78,17 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
return ctx->misa & ext;
}
+#ifdef TARGET_RISCV32
+# define is_32bit(ctx) true
+#elif defined(CONFIG_USER_ONLY)
+# define is_32bit(ctx) false
+#else
+static inline bool is_32bit(DisasContext *ctx)
+{
+ return (ctx->misa & RV32) == RV32;
+}
+#endif
+
/*
* RISC-V requires NaN-boxing of narrower width floating point values.
* This applies when a 32-bit value is assigned to a 64-bit FP register.
@@ -369,6 +380,8 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
static void mark_fs_dirty(DisasContext *ctx)
{
TCGv tmp;
+ target_ulong sd;
+
if (ctx->mstatus_fs == MSTATUS_FS) {
return;
}
@@ -376,13 +389,15 @@ static void mark_fs_dirty(DisasContext *ctx)
ctx->mstatus_fs = MSTATUS_FS;
tmp = tcg_temp_new();
+ sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
+
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
- tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
if (ctx->virt_enabled) {
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
- tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
}
tcg_temp_free(tmp);
--
2.31.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 04/10] target/riscv: Remove the hardcoded MSTATUS_SD macro
@ 2021-04-24 3:33 ` Alistair Francis
0 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-24 3:33 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu_bits.h | 10 ----------
target/riscv/csr.c | 12 ++++++++++--
target/riscv/translate.c | 19 +++++++++++++++++--
3 files changed, 27 insertions(+), 14 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index d738e2fdbd..6e30b312f0 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -368,16 +368,6 @@
#define MXL_RV64 2
#define MXL_RV128 3
-#if defined(TARGET_RISCV32)
-#define MSTATUS_SD MSTATUS32_SD
-#define MISA_MXL MISA32_MXL
-#define MXL_VAL MXL_RV32
-#elif defined(TARGET_RISCV64)
-#define MSTATUS_SD MSTATUS64_SD
-#define MISA_MXL MISA64_MXL
-#define MXL_VAL MXL_RV64
-#endif
-
/* sstatus CSR bits */
#define SSTATUS_UIE 0x00000001
#define SSTATUS_SIE 0x00000002
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 41951a0a84..e955753441 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -538,7 +538,11 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
((mstatus & MSTATUS_XS) == MSTATUS_XS);
- mstatus = set_field(mstatus, MSTATUS_SD, dirty);
+ if (riscv_cpu_is_32bit(env)) {
+ mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
+ } else {
+ mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
+ }
env->mstatus = mstatus;
return RISCV_EXCP_NONE;
@@ -614,7 +618,11 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
}
/* misa.MXL writes are not supported by QEMU */
- val = (env->misa & MISA_MXL) | (val & ~MISA_MXL);
+ if (riscv_cpu_is_32bit(env)) {
+ val = (env->misa & MISA32_MXL) | (val & ~MISA32_MXL);
+ } else {
+ val = (env->misa & MISA64_MXL) | (val & ~MISA64_MXL);
+ }
/* flush translation cache */
if (val != env->misa) {
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 26eccc5eb1..a596f80f20 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -78,6 +78,17 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
return ctx->misa & ext;
}
+#ifdef TARGET_RISCV32
+# define is_32bit(ctx) true
+#elif defined(CONFIG_USER_ONLY)
+# define is_32bit(ctx) false
+#else
+static inline bool is_32bit(DisasContext *ctx)
+{
+ return (ctx->misa & RV32) == RV32;
+}
+#endif
+
/*
* RISC-V requires NaN-boxing of narrower width floating point values.
* This applies when a 32-bit value is assigned to a 64-bit FP register.
@@ -369,6 +380,8 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
static void mark_fs_dirty(DisasContext *ctx)
{
TCGv tmp;
+ target_ulong sd;
+
if (ctx->mstatus_fs == MSTATUS_FS) {
return;
}
@@ -376,13 +389,15 @@ static void mark_fs_dirty(DisasContext *ctx)
ctx->mstatus_fs = MSTATUS_FS;
tmp = tcg_temp_new();
+ sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
+
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
- tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
if (ctx->virt_enabled) {
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
- tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
}
tcg_temp_free(tmp);
--
2.31.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 05/10] target/riscv: Remove the hardcoded SATP_MODE macro
2021-04-24 3:28 ` Alistair Francis
@ 2021-04-24 3:33 ` Alistair Francis
-1 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-24 3:33 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, bmeng.cn, palmer, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu_bits.h | 11 -----------
target/riscv/cpu_helper.c | 32 ++++++++++++++++++++++++--------
target/riscv/csr.c | 19 +++++++++++++++----
target/riscv/monitor.c | 22 +++++++++++++++++-----
4 files changed, 56 insertions(+), 28 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 6e30b312f0..d98f3bc8bc 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -432,17 +432,6 @@
#define SATP64_ASID 0x0FFFF00000000000ULL
#define SATP64_PPN 0x00000FFFFFFFFFFFULL
-#if defined(TARGET_RISCV32)
-#define SATP_MODE SATP32_MODE
-#define SATP_ASID SATP32_ASID
-#define SATP_PPN SATP32_PPN
-#endif
-#if defined(TARGET_RISCV64)
-#define SATP_MODE SATP64_MODE
-#define SATP_ASID SATP64_ASID
-#define SATP_PPN SATP64_PPN
-#endif
-
/* VM modes (mstatus.vm) privileged ISA 1.9.1 */
#define VM_1_09_MBARE 0
#define VM_1_09_MBB 1
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index d9defbdd34..968cb8046f 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -405,11 +405,21 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
if (first_stage == true) {
if (use_background) {
- base = (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT;
- vm = get_field(env->vsatp, SATP_MODE);
+ if (riscv_cpu_is_32bit(env)) {
+ base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT;
+ vm = get_field(env->vsatp, SATP32_MODE);
+ } else {
+ base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT;
+ vm = get_field(env->vsatp, SATP64_MODE);
+ }
} else {
- base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
- vm = get_field(env->satp, SATP_MODE);
+ if (riscv_cpu_is_32bit(env)) {
+ base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
+ vm = get_field(env->satp, SATP32_MODE);
+ } else {
+ base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
+ vm = get_field(env->satp, SATP64_MODE);
+ }
}
widened = 0;
} else {
@@ -624,14 +634,20 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
{
CPUState *cs = env_cpu(env);
int page_fault_exceptions, vm;
+ uint64_t stap_mode;
+
+ if (riscv_cpu_is_32bit(env)) {
+ stap_mode = SATP32_MODE;
+ } else {
+ stap_mode = SATP64_MODE;
+ }
if (first_stage) {
- vm = get_field(env->satp, SATP_MODE);
- } else if (riscv_cpu_is_32bit(env)) {
- vm = get_field(env->hgatp, SATP32_MODE);
+ vm = get_field(env->satp, stap_mode);
} else {
- vm = get_field(env->hgatp, SATP64_MODE);
+ vm = get_field(env->hgatp, stap_mode);
}
+
page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation;
switch (access_type) {
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index e955753441..fe5628fea6 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -997,16 +997,27 @@ static RISCVException read_satp(CPURISCVState *env, int csrno,
static RISCVException write_satp(CPURISCVState *env, int csrno,
target_ulong val)
{
+ int vm, mask, asid;
+
if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
return RISCV_EXCP_NONE;
}
- if (validate_vm(env, get_field(val, SATP_MODE)) &&
- ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
- {
+
+ if (riscv_cpu_is_32bit(env)) {
+ vm = validate_vm(env, get_field(val, SATP32_MODE));
+ mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
+ asid = (val ^ env->satp) & SATP32_ASID;
+ } else {
+ vm = validate_vm(env, get_field(val, SATP64_MODE));
+ mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN);
+ asid = (val ^ env->satp) & SATP64_ASID;
+ }
+
+ if (vm && mask) {
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
return RISCV_EXCP_ILLEGAL_INST;
} else {
- if ((val ^ env->satp) & SATP_ASID) {
+ if (asid) {
tlb_flush(env_cpu(env));
}
env->satp = val;
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
index e51188f919..f7e6ea72b3 100644
--- a/target/riscv/monitor.c
+++ b/target/riscv/monitor.c
@@ -150,9 +150,14 @@ static void mem_info_svxx(Monitor *mon, CPUArchState *env)
target_ulong last_size;
int last_attr;
- base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
+ if (riscv_cpu_is_32bit(env)) {
+ base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
+ vm = get_field(env->satp, SATP32_MODE);
+ } else {
+ base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
+ vm = get_field(env->satp, SATP64_MODE);
+ }
- vm = get_field(env->satp, SATP_MODE);
switch (vm) {
case VM_1_10_SV32:
levels = 2;
@@ -215,9 +220,16 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
return;
}
- if (!(env->satp & SATP_MODE)) {
- monitor_printf(mon, "No translation or protection\n");
- return;
+ if (riscv_cpu_is_32bit(env)) {
+ if (!(env->satp & SATP32_MODE)) {
+ monitor_printf(mon, "No translation or protection\n");
+ return;
+ }
+ } else {
+ if (!(env->satp & SATP64_MODE)) {
+ monitor_printf(mon, "No translation or protection\n");
+ return;
+ }
}
mem_info_svxx(mon, env);
--
2.31.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 05/10] target/riscv: Remove the hardcoded SATP_MODE macro
@ 2021-04-24 3:33 ` Alistair Francis
0 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-24 3:33 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu_bits.h | 11 -----------
target/riscv/cpu_helper.c | 32 ++++++++++++++++++++++++--------
target/riscv/csr.c | 19 +++++++++++++++----
target/riscv/monitor.c | 22 +++++++++++++++++-----
4 files changed, 56 insertions(+), 28 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 6e30b312f0..d98f3bc8bc 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -432,17 +432,6 @@
#define SATP64_ASID 0x0FFFF00000000000ULL
#define SATP64_PPN 0x00000FFFFFFFFFFFULL
-#if defined(TARGET_RISCV32)
-#define SATP_MODE SATP32_MODE
-#define SATP_ASID SATP32_ASID
-#define SATP_PPN SATP32_PPN
-#endif
-#if defined(TARGET_RISCV64)
-#define SATP_MODE SATP64_MODE
-#define SATP_ASID SATP64_ASID
-#define SATP_PPN SATP64_PPN
-#endif
-
/* VM modes (mstatus.vm) privileged ISA 1.9.1 */
#define VM_1_09_MBARE 0
#define VM_1_09_MBB 1
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index d9defbdd34..968cb8046f 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -405,11 +405,21 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
if (first_stage == true) {
if (use_background) {
- base = (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT;
- vm = get_field(env->vsatp, SATP_MODE);
+ if (riscv_cpu_is_32bit(env)) {
+ base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT;
+ vm = get_field(env->vsatp, SATP32_MODE);
+ } else {
+ base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT;
+ vm = get_field(env->vsatp, SATP64_MODE);
+ }
} else {
- base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
- vm = get_field(env->satp, SATP_MODE);
+ if (riscv_cpu_is_32bit(env)) {
+ base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
+ vm = get_field(env->satp, SATP32_MODE);
+ } else {
+ base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
+ vm = get_field(env->satp, SATP64_MODE);
+ }
}
widened = 0;
} else {
@@ -624,14 +634,20 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
{
CPUState *cs = env_cpu(env);
int page_fault_exceptions, vm;
+ uint64_t stap_mode;
+
+ if (riscv_cpu_is_32bit(env)) {
+ stap_mode = SATP32_MODE;
+ } else {
+ stap_mode = SATP64_MODE;
+ }
if (first_stage) {
- vm = get_field(env->satp, SATP_MODE);
- } else if (riscv_cpu_is_32bit(env)) {
- vm = get_field(env->hgatp, SATP32_MODE);
+ vm = get_field(env->satp, stap_mode);
} else {
- vm = get_field(env->hgatp, SATP64_MODE);
+ vm = get_field(env->hgatp, stap_mode);
}
+
page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation;
switch (access_type) {
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index e955753441..fe5628fea6 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -997,16 +997,27 @@ static RISCVException read_satp(CPURISCVState *env, int csrno,
static RISCVException write_satp(CPURISCVState *env, int csrno,
target_ulong val)
{
+ int vm, mask, asid;
+
if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
return RISCV_EXCP_NONE;
}
- if (validate_vm(env, get_field(val, SATP_MODE)) &&
- ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
- {
+
+ if (riscv_cpu_is_32bit(env)) {
+ vm = validate_vm(env, get_field(val, SATP32_MODE));
+ mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
+ asid = (val ^ env->satp) & SATP32_ASID;
+ } else {
+ vm = validate_vm(env, get_field(val, SATP64_MODE));
+ mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN);
+ asid = (val ^ env->satp) & SATP64_ASID;
+ }
+
+ if (vm && mask) {
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
return RISCV_EXCP_ILLEGAL_INST;
} else {
- if ((val ^ env->satp) & SATP_ASID) {
+ if (asid) {
tlb_flush(env_cpu(env));
}
env->satp = val;
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
index e51188f919..f7e6ea72b3 100644
--- a/target/riscv/monitor.c
+++ b/target/riscv/monitor.c
@@ -150,9 +150,14 @@ static void mem_info_svxx(Monitor *mon, CPUArchState *env)
target_ulong last_size;
int last_attr;
- base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
+ if (riscv_cpu_is_32bit(env)) {
+ base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
+ vm = get_field(env->satp, SATP32_MODE);
+ } else {
+ base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
+ vm = get_field(env->satp, SATP64_MODE);
+ }
- vm = get_field(env->satp, SATP_MODE);
switch (vm) {
case VM_1_10_SV32:
levels = 2;
@@ -215,9 +220,16 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
return;
}
- if (!(env->satp & SATP_MODE)) {
- monitor_printf(mon, "No translation or protection\n");
- return;
+ if (riscv_cpu_is_32bit(env)) {
+ if (!(env->satp & SATP32_MODE)) {
+ monitor_printf(mon, "No translation or protection\n");
+ return;
+ }
+ } else {
+ if (!(env->satp & SATP64_MODE)) {
+ monitor_printf(mon, "No translation or protection\n");
+ return;
+ }
}
mem_info_svxx(mon, env);
--
2.31.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 06/10] target/riscv: Remove the unused HSTATUS_WPRI macro
2021-04-24 3:28 ` Alistair Francis
@ 2021-04-24 3:33 ` Alistair Francis
-1 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-24 3:33 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, bmeng.cn, palmer, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
target/riscv/cpu_bits.h | 6 ------
1 file changed, 6 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index d98f3bc8bc..52640e6856 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -396,12 +396,6 @@
#define HSTATUS32_WPRI 0xFF8FF87E
#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
-#if defined(TARGET_RISCV32)
-#define HSTATUS_WPRI HSTATUS32_WPRI
-#elif defined(TARGET_RISCV64)
-#define HSTATUS_WPRI HSTATUS64_WPRI
-#endif
-
#define HCOUNTEREN_CY (1 << 0)
#define HCOUNTEREN_TM (1 << 1)
#define HCOUNTEREN_IR (1 << 2)
--
2.31.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 06/10] target/riscv: Remove the unused HSTATUS_WPRI macro
@ 2021-04-24 3:33 ` Alistair Francis
0 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-24 3:33 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
target/riscv/cpu_bits.h | 6 ------
1 file changed, 6 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index d98f3bc8bc..52640e6856 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -396,12 +396,6 @@
#define HSTATUS32_WPRI 0xFF8FF87E
#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
-#if defined(TARGET_RISCV32)
-#define HSTATUS_WPRI HSTATUS32_WPRI
-#elif defined(TARGET_RISCV64)
-#define HSTATUS_WPRI HSTATUS64_WPRI
-#endif
-
#define HCOUNTEREN_CY (1 << 0)
#define HCOUNTEREN_TM (1 << 1)
#define HCOUNTEREN_IR (1 << 2)
--
2.31.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 07/10] target/riscv: Remove an unused CASE_OP_32_64 macro
2021-04-24 3:28 ` Alistair Francis
@ 2021-04-24 3:34 ` Alistair Francis
-1 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-24 3:34 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, bmeng.cn, palmer, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
target/riscv/translate.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index a596f80f20..a1f794ffda 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -67,12 +67,6 @@ typedef struct DisasContext {
CPUState *cs;
} DisasContext;
-#ifdef TARGET_RISCV64
-#define CASE_OP_32_64(X) case X: case glue(X, W)
-#else
-#define CASE_OP_32_64(X) case X
-#endif
-
static inline bool has_ext(DisasContext *ctx, uint32_t ext)
{
return ctx->misa & ext;
--
2.31.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 07/10] target/riscv: Remove an unused CASE_OP_32_64 macro
@ 2021-04-24 3:34 ` Alistair Francis
0 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-24 3:34 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
target/riscv/translate.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index a596f80f20..a1f794ffda 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -67,12 +67,6 @@ typedef struct DisasContext {
CPUState *cs;
} DisasContext;
-#ifdef TARGET_RISCV64
-#define CASE_OP_32_64(X) case X: case glue(X, W)
-#else
-#define CASE_OP_32_64(X) case X
-#endif
-
static inline bool has_ext(DisasContext *ctx, uint32_t ext)
{
return ctx->misa & ext;
--
2.31.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 08/10] target/riscv: Consolidate RV32/64 32-bit instructions
2021-04-24 3:28 ` Alistair Francis
@ 2021-04-24 3:34 ` Alistair Francis
-1 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-24 3:34 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, bmeng.cn, palmer, alistair23
This patch removes the insn32-64.decode decode file and consolidates the
instructions into the general RISC-V insn32.decode decode tree.
This means that all of the instructions are avaliable in both the 32-bit
and 64-bit builds. This also means that we run a check to ensure we are
running a 64-bit softmmu before we execute the 64-bit only instructions.
This allows us to include the 32-bit instructions in the 64-bit build,
while also ensuring that 32-bit only software can not execute the
instructions.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/helper.h | 18 +++--
target/riscv/insn32-64.decode | 88 -------------------------
target/riscv/insn32.decode | 67 ++++++++++++++++++-
target/riscv/fpu_helper.c | 16 ++---
target/riscv/translate.c | 11 ++--
target/riscv/vector_helper.c | 4 --
target/riscv/insn_trans/trans_rva.c.inc | 14 +++-
target/riscv/insn_trans/trans_rvd.c.inc | 17 ++++-
target/riscv/insn_trans/trans_rvf.c.inc | 6 +-
target/riscv/insn_trans/trans_rvh.c.inc | 8 ++-
target/riscv/insn_trans/trans_rvi.c.inc | 16 +++--
target/riscv/insn_trans/trans_rvm.c.inc | 12 +++-
target/riscv/insn_trans/trans_rvv.c.inc | 39 +++++------
target/riscv/meson.build | 2 +-
14 files changed, 166 insertions(+), 152 deletions(-)
delete mode 100644 target/riscv/insn32-64.decode
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index e3f3f41e89..c7267593c3 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -27,12 +27,12 @@ DEF_HELPER_FLAGS_3(flt_s, TCG_CALL_NO_RWG, tl, env, i64, i64)
DEF_HELPER_FLAGS_3(feq_s, TCG_CALL_NO_RWG, tl, env, i64, i64)
DEF_HELPER_FLAGS_2(fcvt_w_s, TCG_CALL_NO_RWG, tl, env, i64)
DEF_HELPER_FLAGS_2(fcvt_wu_s, TCG_CALL_NO_RWG, tl, env, i64)
-DEF_HELPER_FLAGS_2(fcvt_l_s, TCG_CALL_NO_RWG, i64, env, i64)
-DEF_HELPER_FLAGS_2(fcvt_lu_s, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_l_s, TCG_CALL_NO_RWG, tl, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_lu_s, TCG_CALL_NO_RWG, tl, env, i64)
DEF_HELPER_FLAGS_2(fcvt_s_w, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_2(fcvt_s_wu, TCG_CALL_NO_RWG, i64, env, tl)
-DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, i64)
-DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, tl)
+DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_1(fclass_s, TCG_CALL_NO_RWG_SE, tl, i64)
/* Floating Point - Double Precision */
@@ -50,12 +50,12 @@ DEF_HELPER_FLAGS_3(flt_d, TCG_CALL_NO_RWG, tl, env, i64, i64)
DEF_HELPER_FLAGS_3(feq_d, TCG_CALL_NO_RWG, tl, env, i64, i64)
DEF_HELPER_FLAGS_2(fcvt_w_d, TCG_CALL_NO_RWG, tl, env, i64)
DEF_HELPER_FLAGS_2(fcvt_wu_d, TCG_CALL_NO_RWG, tl, env, i64)
-DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, i64, env, i64)
-DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, tl, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, tl, env, i64)
DEF_HELPER_FLAGS_2(fcvt_d_w, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_2(fcvt_d_wu, TCG_CALL_NO_RWG, i64, env, tl)
-DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, i64)
-DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, tl)
+DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
/* Special functions */
@@ -241,7 +241,6 @@ DEF_HELPER_5(vlhuff_v_w, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vlhuff_v_d, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vlwuff_v_w, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vlwuff_v_d, void, ptr, ptr, tl, env, i32)
-#ifdef TARGET_RISCV64
DEF_HELPER_6(vamoswapw_v_d, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vamoswapd_v_d, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vamoaddw_v_d, void, ptr, ptr, tl, ptr, env, i32)
@@ -260,7 +259,6 @@ DEF_HELPER_6(vamominuw_v_d, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vamominud_v_d, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vamomaxuw_v_d, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vamomaxud_v_d, void, ptr, ptr, tl, ptr, env, i32)
-#endif
DEF_HELPER_6(vamoswapw_v_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vamoaddw_v_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vamoxorw_v_w, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
deleted file mode 100644
index 8157dee8b7..0000000000
--- a/target/riscv/insn32-64.decode
+++ /dev/null
@@ -1,88 +0,0 @@
-#
-# RISC-V translation routines for the RV Instruction Set.
-#
-# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
-# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2 or later, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License along with
-# this program. If not, see <http://www.gnu.org/licenses/>.
-
-# This is concatenated with insn32.decode for risc64 targets.
-# Most of the fields and formats are there.
-
-%sh5 20:5
-
-@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
-
-# *** RV64I Base Instruction Set (in addition to RV32I) ***
-lwu ............ ..... 110 ..... 0000011 @i
-ld ............ ..... 011 ..... 0000011 @i
-sd ....... ..... ..... 011 ..... 0100011 @s
-addiw ............ ..... 000 ..... 0011011 @i
-slliw 0000000 ..... ..... 001 ..... 0011011 @sh5
-srliw 0000000 ..... ..... 101 ..... 0011011 @sh5
-sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5
-addw 0000000 ..... ..... 000 ..... 0111011 @r
-subw 0100000 ..... ..... 000 ..... 0111011 @r
-sllw 0000000 ..... ..... 001 ..... 0111011 @r
-srlw 0000000 ..... ..... 101 ..... 0111011 @r
-sraw 0100000 ..... ..... 101 ..... 0111011 @r
-
-# *** RV64M Standard Extension (in addition to RV32M) ***
-mulw 0000001 ..... ..... 000 ..... 0111011 @r
-divw 0000001 ..... ..... 100 ..... 0111011 @r
-divuw 0000001 ..... ..... 101 ..... 0111011 @r
-remw 0000001 ..... ..... 110 ..... 0111011 @r
-remuw 0000001 ..... ..... 111 ..... 0111011 @r
-
-# *** RV64A Standard Extension (in addition to RV32A) ***
-lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
-sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st
-amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st
-amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st
-amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st
-amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st
-amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st
-amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st
-amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st
-amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
-amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
-
-#*** Vector AMO operations (in addition to Zvamo) ***
-vamoswapd_v 00001 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamoaddd_v 00000 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamoxord_v 00100 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamoandd_v 01100 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamoord_v 01000 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamomind_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
-
-# *** RV64F Standard Extension (in addition to RV32F) ***
-fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
-fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
-fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
-fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
-
-# *** RV64D Standard Extension (in addition to RV32D) ***
-fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm
-fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm
-fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2
-fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm
-fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm
-fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
-
-# *** RV32H Base Instruction Set ***
-hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
-hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
-hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 84080dd18c..fecf0f15d5 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -21,6 +21,7 @@
%rs2 20:5
%rs1 15:5
%rd 7:5
+%sh5 20:5
%sh10 20:10
%csr 20:12
@@ -86,6 +87,8 @@
@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1
@sfence_vm ....... ..... ..... ... ..... ....... %rs1
+# Formats 64:
+@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
# *** Privileged Instructions ***
ecall 000000000000 00000 000 00000 1110011
@@ -144,6 +147,20 @@ csrrwi ............ ..... 101 ..... 1110011 @csr
csrrsi ............ ..... 110 ..... 1110011 @csr
csrrci ............ ..... 111 ..... 1110011 @csr
+# *** RV64I Base Instruction Set (in addition to RV32I) ***
+lwu ............ ..... 110 ..... 0000011 @i
+ld ............ ..... 011 ..... 0000011 @i
+sd ....... ..... ..... 011 ..... 0100011 @s
+addiw ............ ..... 000 ..... 0011011 @i
+slliw 0000000 ..... ..... 001 ..... 0011011 @sh5
+srliw 0000000 ..... ..... 101 ..... 0011011 @sh5
+sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5
+addw 0000000 ..... ..... 000 ..... 0111011 @r
+subw 0100000 ..... ..... 000 ..... 0111011 @r
+sllw 0000000 ..... ..... 001 ..... 0111011 @r
+srlw 0000000 ..... ..... 101 ..... 0111011 @r
+sraw 0100000 ..... ..... 101 ..... 0111011 @r
+
# *** RV32M Standard Extension ***
mul 0000001 ..... ..... 000 ..... 0110011 @r
mulh 0000001 ..... ..... 001 ..... 0110011 @r
@@ -154,6 +171,13 @@ divu 0000001 ..... ..... 101 ..... 0110011 @r
rem 0000001 ..... ..... 110 ..... 0110011 @r
remu 0000001 ..... ..... 111 ..... 0110011 @r
+# *** RV64M Standard Extension (in addition to RV32M) ***
+mulw 0000001 ..... ..... 000 ..... 0111011 @r
+divw 0000001 ..... ..... 100 ..... 0111011 @r
+divuw 0000001 ..... ..... 101 ..... 0111011 @r
+remw 0000001 ..... ..... 110 ..... 0111011 @r
+remuw 0000001 ..... ..... 111 ..... 0111011 @r
+
# *** RV32A Standard Extension ***
lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st
@@ -167,6 +191,19 @@ amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st
amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st
amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st
+# *** RV64A Standard Extension (in addition to RV32A) ***
+lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
+sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st
+amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st
+amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st
+amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st
+amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st
+amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st
+amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st
+amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st
+amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
+amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
+
# *** RV32F Standard Extension ***
flw ............ ..... 010 ..... 0000111 @i
fsw ....... ..... ..... 010 ..... 0100111 @s
@@ -195,6 +232,12 @@ fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm
fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm
fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2
+# *** RV64F Standard Extension (in addition to RV32F) ***
+fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
+fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
+
# *** RV32D Standard Extension ***
fld ............ ..... 011 ..... 0000111 @i
fsd ....... ..... ..... 011 ..... 0100111 @s
@@ -223,6 +266,14 @@ fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm
fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm
fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm
+# *** RV64D Standard Extension (in addition to RV32D) ***
+fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm
+fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2
+fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm
+fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
+
# *** RV32H Base Instruction Set ***
hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2
hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2
@@ -237,7 +288,10 @@ hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s
hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
-# *** RV32V Extension ***
+# *** RV32H Base Instruction Set ***
+hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
+hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
+hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
# *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
vlb_v ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm
@@ -592,3 +646,14 @@ vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
+
+#*** Vector AMO operations (in addition to Zvamo) ***
+vamoswapd_v 00001 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoaddd_v 00000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoxord_v 00100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoandd_v 01100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoord_v 01000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamomind_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index 7c4ab92ecb..8700516a14 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -223,13 +223,13 @@ target_ulong helper_fcvt_wu_s(CPURISCVState *env, uint64_t rs1)
return (int32_t)float32_to_uint32(frs1, &env->fp_status);
}
-uint64_t helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
+target_ulong helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
{
float32 frs1 = check_nanbox_s(rs1);
return float32_to_int64(frs1, &env->fp_status);
}
-uint64_t helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1)
+target_ulong helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1)
{
float32 frs1 = check_nanbox_s(rs1);
return float32_to_uint64(frs1, &env->fp_status);
@@ -245,12 +245,12 @@ uint64_t helper_fcvt_s_wu(CPURISCVState *env, target_ulong rs1)
return nanbox_s(uint32_to_float32((uint32_t)rs1, &env->fp_status));
}
-uint64_t helper_fcvt_s_l(CPURISCVState *env, uint64_t rs1)
+uint64_t helper_fcvt_s_l(CPURISCVState *env, target_ulong rs1)
{
return nanbox_s(int64_to_float32(rs1, &env->fp_status));
}
-uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1)
+uint64_t helper_fcvt_s_lu(CPURISCVState *env, target_ulong rs1)
{
return nanbox_s(uint64_to_float32(rs1, &env->fp_status));
}
@@ -332,12 +332,12 @@ target_ulong helper_fcvt_wu_d(CPURISCVState *env, uint64_t frs1)
return (int32_t)float64_to_uint32(frs1, &env->fp_status);
}
-uint64_t helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1)
+target_ulong helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1)
{
return float64_to_int64(frs1, &env->fp_status);
}
-uint64_t helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1)
+target_ulong helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1)
{
return float64_to_uint64(frs1, &env->fp_status);
}
@@ -352,12 +352,12 @@ uint64_t helper_fcvt_d_wu(CPURISCVState *env, target_ulong rs1)
return uint32_to_float64((uint32_t)rs1, &env->fp_status);
}
-uint64_t helper_fcvt_d_l(CPURISCVState *env, uint64_t rs1)
+uint64_t helper_fcvt_d_l(CPURISCVState *env, target_ulong rs1)
{
return int64_to_float64(rs1, &env->fp_status);
}
-uint64_t helper_fcvt_d_lu(CPURISCVState *env, uint64_t rs1)
+uint64_t helper_fcvt_d_lu(CPURISCVState *env, target_ulong rs1)
{
return uint64_to_float64(rs1, &env->fp_status);
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index a1f794ffda..669fd0d525 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -74,8 +74,6 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
#ifdef TARGET_RISCV32
# define is_32bit(ctx) true
-#elif defined(CONFIG_USER_ONLY)
-# define is_32bit(ctx) false
#else
static inline bool is_32bit(DisasContext *ctx)
{
@@ -435,6 +433,12 @@ EX_SH(12)
} \
} while (0)
+#define REQUIRE_64BIT(ctx) do { \
+ if (is_32bit(ctx)) { \
+ return false; \
+ } \
+} while (0)
+
static int ex_rvc_register(DisasContext *ctx, int reg)
{
return 8 + reg;
@@ -482,7 +486,6 @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a,
return true;
}
-#ifdef TARGET_RISCV64
static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
{
tcg_gen_add_tl(ret, arg1, arg2);
@@ -543,8 +546,6 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
return true;
}
-#endif
-
static bool gen_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 4651a1e224..12c31aa4b4 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -751,7 +751,6 @@ GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_w, 32, 32, H4, DO_MIN, l)
GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_w, 32, 32, H4, DO_MAX, l)
GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_w, 32, 32, H4, DO_MINU, l)
GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_w, 32, 32, H4, DO_MAXU, l)
-#ifdef TARGET_RISCV64
GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_d, 64, 32, H8, DO_SWAP, l)
GEN_VEXT_AMO_NOATOMIC_OP(vamoswapd_v_d, 64, 64, H8, DO_SWAP, q)
GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_d, 64, 32, H8, DO_ADD, l)
@@ -770,7 +769,6 @@ GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_d, 64, 32, H8, DO_MINU, l)
GEN_VEXT_AMO_NOATOMIC_OP(vamominud_v_d, 64, 64, H8, DO_MINU, q)
GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_d, 64, 32, H8, DO_MAXU, l)
GEN_VEXT_AMO_NOATOMIC_OP(vamomaxud_v_d, 64, 64, H8, DO_MAXU, q)
-#endif
static inline void
vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
@@ -814,7 +812,6 @@ void HELPER(NAME)(void *vs3, void *v0, target_ulong base, \
GETPC()); \
}
-#ifdef TARGET_RISCV64
GEN_VEXT_AMO(vamoswapw_v_d, int32_t, int64_t, idx_d, clearq)
GEN_VEXT_AMO(vamoswapd_v_d, int64_t, int64_t, idx_d, clearq)
GEN_VEXT_AMO(vamoaddw_v_d, int32_t, int64_t, idx_d, clearq)
@@ -833,7 +830,6 @@ GEN_VEXT_AMO(vamominuw_v_d, uint32_t, uint64_t, idx_d, clearq)
GEN_VEXT_AMO(vamominud_v_d, uint64_t, uint64_t, idx_d, clearq)
GEN_VEXT_AMO(vamomaxuw_v_d, uint32_t, uint64_t, idx_d, clearq)
GEN_VEXT_AMO(vamomaxud_v_d, uint64_t, uint64_t, idx_d, clearq)
-#endif
GEN_VEXT_AMO(vamoswapw_v_w, int32_t, int32_t, idx_w, clearl)
GEN_VEXT_AMO(vamoaddw_v_w, int32_t, int32_t, idx_w, clearl)
GEN_VEXT_AMO(vamoxorw_v_w, int32_t, int32_t, idx_w, clearl)
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
index be8a9f06dd..ab2ec4f0a5 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -165,60 +165,68 @@ static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a)
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL));
}
-#ifdef TARGET_RISCV64
-
static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a)
{
+ REQUIRE_64BIT(ctx);
return gen_lr(ctx, a, MO_ALIGN | MO_TEQ);
}
static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a)
{
+ REQUIRE_64BIT(ctx);
return gen_sc(ctx, a, (MO_ALIGN | MO_TEQ));
}
static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a)
{
+ REQUIRE_64BIT(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEQ));
}
static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a)
{
+ REQUIRE_64BIT(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TEQ));
}
static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a)
{
+ REQUIRE_64BIT(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TEQ));
}
static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a)
{
+ REQUIRE_64BIT(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TEQ));
}
static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a)
{
+ REQUIRE_64BIT(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEQ));
}
static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a)
{
+ REQUIRE_64BIT(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TEQ));
}
static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a)
{
+ REQUIRE_64BIT(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TEQ));
}
static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a)
{
+ REQUIRE_64BIT(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TEQ));
}
static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a)
{
+ REQUIRE_64BIT(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TEQ));
}
-#endif
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
index 4f832637fa..7e45538ae0 100644
--- a/target/riscv/insn_trans/trans_rvd.c.inc
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -358,10 +358,9 @@ static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a)
return true;
}
-#ifdef TARGET_RISCV64
-
static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
@@ -375,6 +374,7 @@ static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
@@ -388,15 +388,21 @@ static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
+#ifdef TARGET_RISCV64
gen_set_gpr(a->rd, cpu_fpr[a->rs1]);
return true;
+#else
+ qemu_build_not_reached();
+#endif
}
static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
@@ -412,6 +418,7 @@ static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
@@ -427,9 +434,11 @@ static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
+#ifdef TARGET_RISCV64
TCGv t0 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
@@ -437,5 +446,7 @@ static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
tcg_temp_free(t0);
mark_fs_dirty(ctx);
return true;
-}
+#else
+ qemu_build_not_reached();
#endif
+}
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
index 3dfec8211d..db1c0c9974 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -415,9 +415,9 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
return true;
}
-#ifdef TARGET_RISCV64
static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
@@ -431,6 +431,7 @@ static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
@@ -444,6 +445,7 @@ static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
@@ -460,6 +462,7 @@ static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
@@ -473,4 +476,3 @@ static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
tcg_temp_free(t0);
return true;
}
-#endif
diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
index ce7ed5affb..6b5edf82b7 100644
--- a/target/riscv/insn_trans/trans_rvh.c.inc
+++ b/target/riscv/insn_trans/trans_rvh.c.inc
@@ -203,10 +203,11 @@ static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a)
#endif
}
-#ifdef TARGET_RISCV64
static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVH);
+
#ifndef CONFIG_USER_ONLY
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
@@ -228,7 +229,9 @@ static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a)
static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVH);
+
#ifndef CONFIG_USER_ONLY
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
@@ -250,7 +253,9 @@ static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a)
static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVH);
+
#ifndef CONFIG_USER_ONLY
TCGv t0 = tcg_temp_new();
TCGv dat = tcg_temp_new();
@@ -269,7 +274,6 @@ static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)
return false;
#endif
}
-#endif
static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a)
{
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index d04ca0394c..1340676209 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -204,22 +204,23 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a)
return gen_store(ctx, a, MO_TESL);
}
-#ifdef TARGET_RISCV64
static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
{
+ REQUIRE_64BIT(ctx);
return gen_load(ctx, a, MO_TEUL);
}
static bool trans_ld(DisasContext *ctx, arg_ld *a)
{
+ REQUIRE_64BIT(ctx);
return gen_load(ctx, a, MO_TEQ);
}
static bool trans_sd(DisasContext *ctx, arg_sd *a)
{
+ REQUIRE_64BIT(ctx);
return gen_store(ctx, a, MO_TEQ);
}
-#endif
static bool trans_addi(DisasContext *ctx, arg_addi *a)
{
@@ -361,14 +362,15 @@ static bool trans_and(DisasContext *ctx, arg_and *a)
return gen_arith(ctx, a, &tcg_gen_and_tl);
}
-#ifdef TARGET_RISCV64
static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
{
+ REQUIRE_64BIT(ctx);
return gen_arith_imm_tl(ctx, a, &gen_addw);
}
static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
{
+ REQUIRE_64BIT(ctx);
TCGv source1;
source1 = tcg_temp_new();
gen_get_gpr(source1, a->rs1);
@@ -383,6 +385,7 @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
{
+ REQUIRE_64BIT(ctx);
TCGv t = tcg_temp_new();
gen_get_gpr(t, a->rs1);
tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt);
@@ -395,6 +398,7 @@ static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
{
+ REQUIRE_64BIT(ctx);
TCGv t = tcg_temp_new();
gen_get_gpr(t, a->rs1);
tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt);
@@ -405,16 +409,19 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
static bool trans_addw(DisasContext *ctx, arg_addw *a)
{
+ REQUIRE_64BIT(ctx);
return gen_arith(ctx, a, &gen_addw);
}
static bool trans_subw(DisasContext *ctx, arg_subw *a)
{
+ REQUIRE_64BIT(ctx);
return gen_arith(ctx, a, &gen_subw);
}
static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
{
+ REQUIRE_64BIT(ctx);
TCGv source1 = tcg_temp_new();
TCGv source2 = tcg_temp_new();
@@ -433,6 +440,7 @@ static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
{
+ REQUIRE_64BIT(ctx);
TCGv source1 = tcg_temp_new();
TCGv source2 = tcg_temp_new();
@@ -453,6 +461,7 @@ static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
{
+ REQUIRE_64BIT(ctx);
TCGv source1 = tcg_temp_new();
TCGv source2 = tcg_temp_new();
@@ -473,7 +482,6 @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
return true;
}
-#endif
static bool trans_fence(DisasContext *ctx, arg_fence *a)
{
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
index 47cd6edc72..10ecc456fc 100644
--- a/target/riscv/insn_trans/trans_rvm.c.inc
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -87,34 +87,42 @@ static bool trans_remu(DisasContext *ctx, arg_remu *a)
return gen_arith(ctx, a, &gen_remu);
}
-#ifdef TARGET_RISCV64
static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM);
+
return gen_arith(ctx, a, &gen_mulw);
}
static bool trans_divw(DisasContext *ctx, arg_divw *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM);
+
return gen_arith_div_w(ctx, a, &gen_div);
}
static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM);
+
return gen_arith_div_uw(ctx, a, &gen_divu);
}
static bool trans_remw(DisasContext *ctx, arg_remw *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM);
+
return gen_arith_div_w(ctx, a, &gen_rem);
}
static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM);
+
return gen_arith_div_uw(ctx, a, &gen_remu);
}
-#endif
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 887c6b8883..47914a3b69 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -705,7 +705,6 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
gen_helper_vamominuw_v_w,
gen_helper_vamomaxuw_v_w
};
-#ifdef TARGET_RISCV64
static gen_helper_amo *const fnsd[18] = {
gen_helper_vamoswapw_v_d,
gen_helper_vamoaddw_v_d,
@@ -726,7 +725,6 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
gen_helper_vamominud_v_d,
gen_helper_vamomaxud_v_d
};
-#endif
if (tb_cflags(s->base.tb) & CF_PARALLEL) {
gen_helper_exit_atomic(cpu_env);
@@ -734,12 +732,12 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
return true;
} else {
if (s->sew == 3) {
-#ifdef TARGET_RISCV64
- fn = fnsd[seq];
-#else
- /* Check done in amo_check(). */
- g_assert_not_reached();
-#endif
+ if (!is_32bit(s)) {
+ fn = fnsd[seq];
+ } else {
+ /* Check done in amo_check(). */
+ g_assert_not_reached();
+ }
} else {
assert(seq < ARRAY_SIZE(fnsw));
fn = fnsw[seq];
@@ -769,6 +767,11 @@ static bool amo_check(DisasContext *s, arg_rwdvm* a)
((1 << s->sew) >= 4));
}
+static bool amo_check64(DisasContext *s, arg_rwdvm* a)
+{
+ return !is_32bit(s) && amo_check(s, a);
+}
+
GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check)
GEN_VEXT_TRANS(vamoaddw_v, 1, rwdvm, amo_op, amo_check)
GEN_VEXT_TRANS(vamoxorw_v, 2, rwdvm, amo_op, amo_check)
@@ -778,17 +781,15 @@ GEN_VEXT_TRANS(vamominw_v, 5, rwdvm, amo_op, amo_check)
GEN_VEXT_TRANS(vamomaxw_v, 6, rwdvm, amo_op, amo_check)
GEN_VEXT_TRANS(vamominuw_v, 7, rwdvm, amo_op, amo_check)
GEN_VEXT_TRANS(vamomaxuw_v, 8, rwdvm, amo_op, amo_check)
-#ifdef TARGET_RISCV64
-GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check)
-#endif
+GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check64)
/*
*** Vector Integer Arithmetic Instructions
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index 88ab850682..24bf049164 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -7,7 +7,7 @@ gen32 = [
gen64 = [
decodetree.process('insn16.decode', extra_args: [dir / 'insn16-64.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
- decodetree.process('insn32.decode', extra_args: [dir / 'insn32-64.decode', '--static-decode=decode_insn32']),
+ decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
]
riscv_ss = ss.source_set()
--
2.31.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 08/10] target/riscv: Consolidate RV32/64 32-bit instructions
@ 2021-04-24 3:34 ` Alistair Francis
0 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-24 3:34 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
This patch removes the insn32-64.decode decode file and consolidates the
instructions into the general RISC-V insn32.decode decode tree.
This means that all of the instructions are avaliable in both the 32-bit
and 64-bit builds. This also means that we run a check to ensure we are
running a 64-bit softmmu before we execute the 64-bit only instructions.
This allows us to include the 32-bit instructions in the 64-bit build,
while also ensuring that 32-bit only software can not execute the
instructions.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/helper.h | 18 +++--
target/riscv/insn32-64.decode | 88 -------------------------
target/riscv/insn32.decode | 67 ++++++++++++++++++-
target/riscv/fpu_helper.c | 16 ++---
target/riscv/translate.c | 11 ++--
target/riscv/vector_helper.c | 4 --
target/riscv/insn_trans/trans_rva.c.inc | 14 +++-
target/riscv/insn_trans/trans_rvd.c.inc | 17 ++++-
target/riscv/insn_trans/trans_rvf.c.inc | 6 +-
target/riscv/insn_trans/trans_rvh.c.inc | 8 ++-
target/riscv/insn_trans/trans_rvi.c.inc | 16 +++--
target/riscv/insn_trans/trans_rvm.c.inc | 12 +++-
target/riscv/insn_trans/trans_rvv.c.inc | 39 +++++------
target/riscv/meson.build | 2 +-
14 files changed, 166 insertions(+), 152 deletions(-)
delete mode 100644 target/riscv/insn32-64.decode
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index e3f3f41e89..c7267593c3 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -27,12 +27,12 @@ DEF_HELPER_FLAGS_3(flt_s, TCG_CALL_NO_RWG, tl, env, i64, i64)
DEF_HELPER_FLAGS_3(feq_s, TCG_CALL_NO_RWG, tl, env, i64, i64)
DEF_HELPER_FLAGS_2(fcvt_w_s, TCG_CALL_NO_RWG, tl, env, i64)
DEF_HELPER_FLAGS_2(fcvt_wu_s, TCG_CALL_NO_RWG, tl, env, i64)
-DEF_HELPER_FLAGS_2(fcvt_l_s, TCG_CALL_NO_RWG, i64, env, i64)
-DEF_HELPER_FLAGS_2(fcvt_lu_s, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_l_s, TCG_CALL_NO_RWG, tl, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_lu_s, TCG_CALL_NO_RWG, tl, env, i64)
DEF_HELPER_FLAGS_2(fcvt_s_w, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_2(fcvt_s_wu, TCG_CALL_NO_RWG, i64, env, tl)
-DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, i64)
-DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, tl)
+DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_1(fclass_s, TCG_CALL_NO_RWG_SE, tl, i64)
/* Floating Point - Double Precision */
@@ -50,12 +50,12 @@ DEF_HELPER_FLAGS_3(flt_d, TCG_CALL_NO_RWG, tl, env, i64, i64)
DEF_HELPER_FLAGS_3(feq_d, TCG_CALL_NO_RWG, tl, env, i64, i64)
DEF_HELPER_FLAGS_2(fcvt_w_d, TCG_CALL_NO_RWG, tl, env, i64)
DEF_HELPER_FLAGS_2(fcvt_wu_d, TCG_CALL_NO_RWG, tl, env, i64)
-DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, i64, env, i64)
-DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, tl, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, tl, env, i64)
DEF_HELPER_FLAGS_2(fcvt_d_w, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_2(fcvt_d_wu, TCG_CALL_NO_RWG, i64, env, tl)
-DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, i64)
-DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, tl)
+DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
/* Special functions */
@@ -241,7 +241,6 @@ DEF_HELPER_5(vlhuff_v_w, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vlhuff_v_d, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vlwuff_v_w, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vlwuff_v_d, void, ptr, ptr, tl, env, i32)
-#ifdef TARGET_RISCV64
DEF_HELPER_6(vamoswapw_v_d, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vamoswapd_v_d, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vamoaddw_v_d, void, ptr, ptr, tl, ptr, env, i32)
@@ -260,7 +259,6 @@ DEF_HELPER_6(vamominuw_v_d, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vamominud_v_d, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vamomaxuw_v_d, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vamomaxud_v_d, void, ptr, ptr, tl, ptr, env, i32)
-#endif
DEF_HELPER_6(vamoswapw_v_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vamoaddw_v_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vamoxorw_v_w, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
deleted file mode 100644
index 8157dee8b7..0000000000
--- a/target/riscv/insn32-64.decode
+++ /dev/null
@@ -1,88 +0,0 @@
-#
-# RISC-V translation routines for the RV Instruction Set.
-#
-# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
-# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2 or later, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License along with
-# this program. If not, see <http://www.gnu.org/licenses/>.
-
-# This is concatenated with insn32.decode for risc64 targets.
-# Most of the fields and formats are there.
-
-%sh5 20:5
-
-@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
-
-# *** RV64I Base Instruction Set (in addition to RV32I) ***
-lwu ............ ..... 110 ..... 0000011 @i
-ld ............ ..... 011 ..... 0000011 @i
-sd ....... ..... ..... 011 ..... 0100011 @s
-addiw ............ ..... 000 ..... 0011011 @i
-slliw 0000000 ..... ..... 001 ..... 0011011 @sh5
-srliw 0000000 ..... ..... 101 ..... 0011011 @sh5
-sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5
-addw 0000000 ..... ..... 000 ..... 0111011 @r
-subw 0100000 ..... ..... 000 ..... 0111011 @r
-sllw 0000000 ..... ..... 001 ..... 0111011 @r
-srlw 0000000 ..... ..... 101 ..... 0111011 @r
-sraw 0100000 ..... ..... 101 ..... 0111011 @r
-
-# *** RV64M Standard Extension (in addition to RV32M) ***
-mulw 0000001 ..... ..... 000 ..... 0111011 @r
-divw 0000001 ..... ..... 100 ..... 0111011 @r
-divuw 0000001 ..... ..... 101 ..... 0111011 @r
-remw 0000001 ..... ..... 110 ..... 0111011 @r
-remuw 0000001 ..... ..... 111 ..... 0111011 @r
-
-# *** RV64A Standard Extension (in addition to RV32A) ***
-lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
-sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st
-amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st
-amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st
-amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st
-amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st
-amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st
-amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st
-amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st
-amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
-amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
-
-#*** Vector AMO operations (in addition to Zvamo) ***
-vamoswapd_v 00001 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamoaddd_v 00000 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamoxord_v 00100 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamoandd_v 01100 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamoord_v 01000 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamomind_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
-
-# *** RV64F Standard Extension (in addition to RV32F) ***
-fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
-fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
-fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
-fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
-
-# *** RV64D Standard Extension (in addition to RV32D) ***
-fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm
-fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm
-fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2
-fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm
-fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm
-fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
-
-# *** RV32H Base Instruction Set ***
-hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
-hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
-hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 84080dd18c..fecf0f15d5 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -21,6 +21,7 @@
%rs2 20:5
%rs1 15:5
%rd 7:5
+%sh5 20:5
%sh10 20:10
%csr 20:12
@@ -86,6 +87,8 @@
@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1
@sfence_vm ....... ..... ..... ... ..... ....... %rs1
+# Formats 64:
+@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
# *** Privileged Instructions ***
ecall 000000000000 00000 000 00000 1110011
@@ -144,6 +147,20 @@ csrrwi ............ ..... 101 ..... 1110011 @csr
csrrsi ............ ..... 110 ..... 1110011 @csr
csrrci ............ ..... 111 ..... 1110011 @csr
+# *** RV64I Base Instruction Set (in addition to RV32I) ***
+lwu ............ ..... 110 ..... 0000011 @i
+ld ............ ..... 011 ..... 0000011 @i
+sd ....... ..... ..... 011 ..... 0100011 @s
+addiw ............ ..... 000 ..... 0011011 @i
+slliw 0000000 ..... ..... 001 ..... 0011011 @sh5
+srliw 0000000 ..... ..... 101 ..... 0011011 @sh5
+sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5
+addw 0000000 ..... ..... 000 ..... 0111011 @r
+subw 0100000 ..... ..... 000 ..... 0111011 @r
+sllw 0000000 ..... ..... 001 ..... 0111011 @r
+srlw 0000000 ..... ..... 101 ..... 0111011 @r
+sraw 0100000 ..... ..... 101 ..... 0111011 @r
+
# *** RV32M Standard Extension ***
mul 0000001 ..... ..... 000 ..... 0110011 @r
mulh 0000001 ..... ..... 001 ..... 0110011 @r
@@ -154,6 +171,13 @@ divu 0000001 ..... ..... 101 ..... 0110011 @r
rem 0000001 ..... ..... 110 ..... 0110011 @r
remu 0000001 ..... ..... 111 ..... 0110011 @r
+# *** RV64M Standard Extension (in addition to RV32M) ***
+mulw 0000001 ..... ..... 000 ..... 0111011 @r
+divw 0000001 ..... ..... 100 ..... 0111011 @r
+divuw 0000001 ..... ..... 101 ..... 0111011 @r
+remw 0000001 ..... ..... 110 ..... 0111011 @r
+remuw 0000001 ..... ..... 111 ..... 0111011 @r
+
# *** RV32A Standard Extension ***
lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st
@@ -167,6 +191,19 @@ amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st
amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st
amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st
+# *** RV64A Standard Extension (in addition to RV32A) ***
+lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
+sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st
+amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st
+amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st
+amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st
+amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st
+amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st
+amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st
+amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st
+amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
+amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
+
# *** RV32F Standard Extension ***
flw ............ ..... 010 ..... 0000111 @i
fsw ....... ..... ..... 010 ..... 0100111 @s
@@ -195,6 +232,12 @@ fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm
fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm
fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2
+# *** RV64F Standard Extension (in addition to RV32F) ***
+fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
+fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
+
# *** RV32D Standard Extension ***
fld ............ ..... 011 ..... 0000111 @i
fsd ....... ..... ..... 011 ..... 0100111 @s
@@ -223,6 +266,14 @@ fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm
fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm
fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm
+# *** RV64D Standard Extension (in addition to RV32D) ***
+fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm
+fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2
+fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm
+fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
+
# *** RV32H Base Instruction Set ***
hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2
hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2
@@ -237,7 +288,10 @@ hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s
hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
-# *** RV32V Extension ***
+# *** RV32H Base Instruction Set ***
+hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
+hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
+hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
# *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
vlb_v ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm
@@ -592,3 +646,14 @@ vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
+
+#*** Vector AMO operations (in addition to Zvamo) ***
+vamoswapd_v 00001 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoaddd_v 00000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoxord_v 00100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoandd_v 01100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoord_v 01000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamomind_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index 7c4ab92ecb..8700516a14 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -223,13 +223,13 @@ target_ulong helper_fcvt_wu_s(CPURISCVState *env, uint64_t rs1)
return (int32_t)float32_to_uint32(frs1, &env->fp_status);
}
-uint64_t helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
+target_ulong helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
{
float32 frs1 = check_nanbox_s(rs1);
return float32_to_int64(frs1, &env->fp_status);
}
-uint64_t helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1)
+target_ulong helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1)
{
float32 frs1 = check_nanbox_s(rs1);
return float32_to_uint64(frs1, &env->fp_status);
@@ -245,12 +245,12 @@ uint64_t helper_fcvt_s_wu(CPURISCVState *env, target_ulong rs1)
return nanbox_s(uint32_to_float32((uint32_t)rs1, &env->fp_status));
}
-uint64_t helper_fcvt_s_l(CPURISCVState *env, uint64_t rs1)
+uint64_t helper_fcvt_s_l(CPURISCVState *env, target_ulong rs1)
{
return nanbox_s(int64_to_float32(rs1, &env->fp_status));
}
-uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1)
+uint64_t helper_fcvt_s_lu(CPURISCVState *env, target_ulong rs1)
{
return nanbox_s(uint64_to_float32(rs1, &env->fp_status));
}
@@ -332,12 +332,12 @@ target_ulong helper_fcvt_wu_d(CPURISCVState *env, uint64_t frs1)
return (int32_t)float64_to_uint32(frs1, &env->fp_status);
}
-uint64_t helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1)
+target_ulong helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1)
{
return float64_to_int64(frs1, &env->fp_status);
}
-uint64_t helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1)
+target_ulong helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1)
{
return float64_to_uint64(frs1, &env->fp_status);
}
@@ -352,12 +352,12 @@ uint64_t helper_fcvt_d_wu(CPURISCVState *env, target_ulong rs1)
return uint32_to_float64((uint32_t)rs1, &env->fp_status);
}
-uint64_t helper_fcvt_d_l(CPURISCVState *env, uint64_t rs1)
+uint64_t helper_fcvt_d_l(CPURISCVState *env, target_ulong rs1)
{
return int64_to_float64(rs1, &env->fp_status);
}
-uint64_t helper_fcvt_d_lu(CPURISCVState *env, uint64_t rs1)
+uint64_t helper_fcvt_d_lu(CPURISCVState *env, target_ulong rs1)
{
return uint64_to_float64(rs1, &env->fp_status);
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index a1f794ffda..669fd0d525 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -74,8 +74,6 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
#ifdef TARGET_RISCV32
# define is_32bit(ctx) true
-#elif defined(CONFIG_USER_ONLY)
-# define is_32bit(ctx) false
#else
static inline bool is_32bit(DisasContext *ctx)
{
@@ -435,6 +433,12 @@ EX_SH(12)
} \
} while (0)
+#define REQUIRE_64BIT(ctx) do { \
+ if (is_32bit(ctx)) { \
+ return false; \
+ } \
+} while (0)
+
static int ex_rvc_register(DisasContext *ctx, int reg)
{
return 8 + reg;
@@ -482,7 +486,6 @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a,
return true;
}
-#ifdef TARGET_RISCV64
static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
{
tcg_gen_add_tl(ret, arg1, arg2);
@@ -543,8 +546,6 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
return true;
}
-#endif
-
static bool gen_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 4651a1e224..12c31aa4b4 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -751,7 +751,6 @@ GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_w, 32, 32, H4, DO_MIN, l)
GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_w, 32, 32, H4, DO_MAX, l)
GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_w, 32, 32, H4, DO_MINU, l)
GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_w, 32, 32, H4, DO_MAXU, l)
-#ifdef TARGET_RISCV64
GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_d, 64, 32, H8, DO_SWAP, l)
GEN_VEXT_AMO_NOATOMIC_OP(vamoswapd_v_d, 64, 64, H8, DO_SWAP, q)
GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_d, 64, 32, H8, DO_ADD, l)
@@ -770,7 +769,6 @@ GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_d, 64, 32, H8, DO_MINU, l)
GEN_VEXT_AMO_NOATOMIC_OP(vamominud_v_d, 64, 64, H8, DO_MINU, q)
GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_d, 64, 32, H8, DO_MAXU, l)
GEN_VEXT_AMO_NOATOMIC_OP(vamomaxud_v_d, 64, 64, H8, DO_MAXU, q)
-#endif
static inline void
vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
@@ -814,7 +812,6 @@ void HELPER(NAME)(void *vs3, void *v0, target_ulong base, \
GETPC()); \
}
-#ifdef TARGET_RISCV64
GEN_VEXT_AMO(vamoswapw_v_d, int32_t, int64_t, idx_d, clearq)
GEN_VEXT_AMO(vamoswapd_v_d, int64_t, int64_t, idx_d, clearq)
GEN_VEXT_AMO(vamoaddw_v_d, int32_t, int64_t, idx_d, clearq)
@@ -833,7 +830,6 @@ GEN_VEXT_AMO(vamominuw_v_d, uint32_t, uint64_t, idx_d, clearq)
GEN_VEXT_AMO(vamominud_v_d, uint64_t, uint64_t, idx_d, clearq)
GEN_VEXT_AMO(vamomaxuw_v_d, uint32_t, uint64_t, idx_d, clearq)
GEN_VEXT_AMO(vamomaxud_v_d, uint64_t, uint64_t, idx_d, clearq)
-#endif
GEN_VEXT_AMO(vamoswapw_v_w, int32_t, int32_t, idx_w, clearl)
GEN_VEXT_AMO(vamoaddw_v_w, int32_t, int32_t, idx_w, clearl)
GEN_VEXT_AMO(vamoxorw_v_w, int32_t, int32_t, idx_w, clearl)
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
index be8a9f06dd..ab2ec4f0a5 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -165,60 +165,68 @@ static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a)
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL));
}
-#ifdef TARGET_RISCV64
-
static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a)
{
+ REQUIRE_64BIT(ctx);
return gen_lr(ctx, a, MO_ALIGN | MO_TEQ);
}
static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a)
{
+ REQUIRE_64BIT(ctx);
return gen_sc(ctx, a, (MO_ALIGN | MO_TEQ));
}
static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a)
{
+ REQUIRE_64BIT(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEQ));
}
static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a)
{
+ REQUIRE_64BIT(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TEQ));
}
static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a)
{
+ REQUIRE_64BIT(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TEQ));
}
static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a)
{
+ REQUIRE_64BIT(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TEQ));
}
static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a)
{
+ REQUIRE_64BIT(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEQ));
}
static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a)
{
+ REQUIRE_64BIT(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TEQ));
}
static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a)
{
+ REQUIRE_64BIT(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TEQ));
}
static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a)
{
+ REQUIRE_64BIT(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TEQ));
}
static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a)
{
+ REQUIRE_64BIT(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TEQ));
}
-#endif
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
index 4f832637fa..7e45538ae0 100644
--- a/target/riscv/insn_trans/trans_rvd.c.inc
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -358,10 +358,9 @@ static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a)
return true;
}
-#ifdef TARGET_RISCV64
-
static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
@@ -375,6 +374,7 @@ static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
@@ -388,15 +388,21 @@ static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
+#ifdef TARGET_RISCV64
gen_set_gpr(a->rd, cpu_fpr[a->rs1]);
return true;
+#else
+ qemu_build_not_reached();
+#endif
}
static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
@@ -412,6 +418,7 @@ static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
@@ -427,9 +434,11 @@ static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
+#ifdef TARGET_RISCV64
TCGv t0 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
@@ -437,5 +446,7 @@ static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
tcg_temp_free(t0);
mark_fs_dirty(ctx);
return true;
-}
+#else
+ qemu_build_not_reached();
#endif
+}
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
index 3dfec8211d..db1c0c9974 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -415,9 +415,9 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
return true;
}
-#ifdef TARGET_RISCV64
static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
@@ -431,6 +431,7 @@ static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
@@ -444,6 +445,7 @@ static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
@@ -460,6 +462,7 @@ static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
@@ -473,4 +476,3 @@ static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
tcg_temp_free(t0);
return true;
}
-#endif
diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
index ce7ed5affb..6b5edf82b7 100644
--- a/target/riscv/insn_trans/trans_rvh.c.inc
+++ b/target/riscv/insn_trans/trans_rvh.c.inc
@@ -203,10 +203,11 @@ static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a)
#endif
}
-#ifdef TARGET_RISCV64
static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVH);
+
#ifndef CONFIG_USER_ONLY
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
@@ -228,7 +229,9 @@ static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a)
static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVH);
+
#ifndef CONFIG_USER_ONLY
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
@@ -250,7 +253,9 @@ static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a)
static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVH);
+
#ifndef CONFIG_USER_ONLY
TCGv t0 = tcg_temp_new();
TCGv dat = tcg_temp_new();
@@ -269,7 +274,6 @@ static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)
return false;
#endif
}
-#endif
static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a)
{
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index d04ca0394c..1340676209 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -204,22 +204,23 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a)
return gen_store(ctx, a, MO_TESL);
}
-#ifdef TARGET_RISCV64
static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
{
+ REQUIRE_64BIT(ctx);
return gen_load(ctx, a, MO_TEUL);
}
static bool trans_ld(DisasContext *ctx, arg_ld *a)
{
+ REQUIRE_64BIT(ctx);
return gen_load(ctx, a, MO_TEQ);
}
static bool trans_sd(DisasContext *ctx, arg_sd *a)
{
+ REQUIRE_64BIT(ctx);
return gen_store(ctx, a, MO_TEQ);
}
-#endif
static bool trans_addi(DisasContext *ctx, arg_addi *a)
{
@@ -361,14 +362,15 @@ static bool trans_and(DisasContext *ctx, arg_and *a)
return gen_arith(ctx, a, &tcg_gen_and_tl);
}
-#ifdef TARGET_RISCV64
static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
{
+ REQUIRE_64BIT(ctx);
return gen_arith_imm_tl(ctx, a, &gen_addw);
}
static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
{
+ REQUIRE_64BIT(ctx);
TCGv source1;
source1 = tcg_temp_new();
gen_get_gpr(source1, a->rs1);
@@ -383,6 +385,7 @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
{
+ REQUIRE_64BIT(ctx);
TCGv t = tcg_temp_new();
gen_get_gpr(t, a->rs1);
tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt);
@@ -395,6 +398,7 @@ static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
{
+ REQUIRE_64BIT(ctx);
TCGv t = tcg_temp_new();
gen_get_gpr(t, a->rs1);
tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt);
@@ -405,16 +409,19 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
static bool trans_addw(DisasContext *ctx, arg_addw *a)
{
+ REQUIRE_64BIT(ctx);
return gen_arith(ctx, a, &gen_addw);
}
static bool trans_subw(DisasContext *ctx, arg_subw *a)
{
+ REQUIRE_64BIT(ctx);
return gen_arith(ctx, a, &gen_subw);
}
static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
{
+ REQUIRE_64BIT(ctx);
TCGv source1 = tcg_temp_new();
TCGv source2 = tcg_temp_new();
@@ -433,6 +440,7 @@ static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
{
+ REQUIRE_64BIT(ctx);
TCGv source1 = tcg_temp_new();
TCGv source2 = tcg_temp_new();
@@ -453,6 +461,7 @@ static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
{
+ REQUIRE_64BIT(ctx);
TCGv source1 = tcg_temp_new();
TCGv source2 = tcg_temp_new();
@@ -473,7 +482,6 @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
return true;
}
-#endif
static bool trans_fence(DisasContext *ctx, arg_fence *a)
{
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
index 47cd6edc72..10ecc456fc 100644
--- a/target/riscv/insn_trans/trans_rvm.c.inc
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -87,34 +87,42 @@ static bool trans_remu(DisasContext *ctx, arg_remu *a)
return gen_arith(ctx, a, &gen_remu);
}
-#ifdef TARGET_RISCV64
static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM);
+
return gen_arith(ctx, a, &gen_mulw);
}
static bool trans_divw(DisasContext *ctx, arg_divw *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM);
+
return gen_arith_div_w(ctx, a, &gen_div);
}
static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM);
+
return gen_arith_div_uw(ctx, a, &gen_divu);
}
static bool trans_remw(DisasContext *ctx, arg_remw *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM);
+
return gen_arith_div_w(ctx, a, &gen_rem);
}
static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
{
+ REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM);
+
return gen_arith_div_uw(ctx, a, &gen_remu);
}
-#endif
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 887c6b8883..47914a3b69 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -705,7 +705,6 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
gen_helper_vamominuw_v_w,
gen_helper_vamomaxuw_v_w
};
-#ifdef TARGET_RISCV64
static gen_helper_amo *const fnsd[18] = {
gen_helper_vamoswapw_v_d,
gen_helper_vamoaddw_v_d,
@@ -726,7 +725,6 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
gen_helper_vamominud_v_d,
gen_helper_vamomaxud_v_d
};
-#endif
if (tb_cflags(s->base.tb) & CF_PARALLEL) {
gen_helper_exit_atomic(cpu_env);
@@ -734,12 +732,12 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
return true;
} else {
if (s->sew == 3) {
-#ifdef TARGET_RISCV64
- fn = fnsd[seq];
-#else
- /* Check done in amo_check(). */
- g_assert_not_reached();
-#endif
+ if (!is_32bit(s)) {
+ fn = fnsd[seq];
+ } else {
+ /* Check done in amo_check(). */
+ g_assert_not_reached();
+ }
} else {
assert(seq < ARRAY_SIZE(fnsw));
fn = fnsw[seq];
@@ -769,6 +767,11 @@ static bool amo_check(DisasContext *s, arg_rwdvm* a)
((1 << s->sew) >= 4));
}
+static bool amo_check64(DisasContext *s, arg_rwdvm* a)
+{
+ return !is_32bit(s) && amo_check(s, a);
+}
+
GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check)
GEN_VEXT_TRANS(vamoaddw_v, 1, rwdvm, amo_op, amo_check)
GEN_VEXT_TRANS(vamoxorw_v, 2, rwdvm, amo_op, amo_check)
@@ -778,17 +781,15 @@ GEN_VEXT_TRANS(vamominw_v, 5, rwdvm, amo_op, amo_check)
GEN_VEXT_TRANS(vamomaxw_v, 6, rwdvm, amo_op, amo_check)
GEN_VEXT_TRANS(vamominuw_v, 7, rwdvm, amo_op, amo_check)
GEN_VEXT_TRANS(vamomaxuw_v, 8, rwdvm, amo_op, amo_check)
-#ifdef TARGET_RISCV64
-GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check)
-#endif
+GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check64)
/*
*** Vector Integer Arithmetic Instructions
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index 88ab850682..24bf049164 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -7,7 +7,7 @@ gen32 = [
gen64 = [
decodetree.process('insn16.decode', extra_args: [dir / 'insn16-64.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
- decodetree.process('insn32.decode', extra_args: [dir / 'insn32-64.decode', '--static-decode=decode_insn32']),
+ decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
]
riscv_ss = ss.source_set()
--
2.31.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 09/10] target/riscv: Consolidate RV32/64 16-bit instructions
2021-04-24 3:28 ` Alistair Francis
@ 2021-04-24 3:34 ` Alistair Francis
-1 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-24 3:34 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, bmeng.cn, palmer, alistair23
This patch removes the insn16-32.decode and insn16-64.decode decode
files and consolidates the instructions into the general RISC-V
insn16.decode decode tree.
This means that all of the instructions are avaliable in both the 32-bit
and 64-bit builds. This also means that we run a check to ensure we are
running a 64-bit softmmu before we execute the 64-bit only instructions.
This allows us to include the 32-bit instructions in the 64-bit build,
while also ensuring that 32-bit only software can not execute the
instructions.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn16-32.decode | 28 -------------------
target/riscv/insn16-64.decode | 36 -------------------------
target/riscv/insn16.decode | 30 +++++++++++++++++++++
target/riscv/insn_trans/trans_rvi.c.inc | 6 +++++
target/riscv/meson.build | 11 +++-----
5 files changed, 39 insertions(+), 72 deletions(-)
delete mode 100644 target/riscv/insn16-32.decode
delete mode 100644 target/riscv/insn16-64.decode
diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode
deleted file mode 100644
index 0819b17028..0000000000
--- a/target/riscv/insn16-32.decode
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# RISC-V translation routines for the RVXI Base Integer Instruction Set.
-#
-# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
-# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2 or later, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License along with
-# this program. If not, see <http://www.gnu.org/licenses/>.
-
-# *** RV32C Standard Extension (Quadrant 0) ***
-flw 011 ... ... .. ... 00 @cl_w
-fsw 111 ... ... .. ... 00 @cs_w
-
-# *** RV32C Standard Extension (Quadrant 1) ***
-jal 001 ........... 01 @cj rd=1 # C.JAL
-
-# *** RV32C Standard Extension (Quadrant 2) ***
-flw 011 . ..... ..... 10 @c_lwsp
-fsw 111 . ..... ..... 10 @c_swsp
diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode
deleted file mode 100644
index 672e1e916f..0000000000
--- a/target/riscv/insn16-64.decode
+++ /dev/null
@@ -1,36 +0,0 @@
-#
-# RISC-V translation routines for the RVXI Base Integer Instruction Set.
-#
-# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
-# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2 or later, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License along with
-# this program. If not, see <http://www.gnu.org/licenses/>.
-
-# *** RV64C Standard Extension (Quadrant 0) ***
-ld 011 ... ... .. ... 00 @cl_d
-sd 111 ... ... .. ... 00 @cs_d
-
-# *** RV64C Standard Extension (Quadrant 1) ***
-{
- illegal 001 - 00000 ----- 01 # c.addiw, RES rd=0
- addiw 001 . ..... ..... 01 @ci
-}
-subw 100 1 11 ... 00 ... 01 @cs_2
-addw 100 1 11 ... 01 ... 01 @cs_2
-
-# *** RV64C Standard Extension (Quadrant 2) ***
-{
- illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=0
- ld 011 . ..... ..... 10 @c_ldsp
-}
-sd 111 . ..... ..... 10 @c_sdsp
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 1cb93876fe..2e9212663c 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -92,6 +92,16 @@ lw 010 ... ... .. ... 00 @cl_w
fsd 101 ... ... .. ... 00 @cs_d
sw 110 ... ... .. ... 00 @cs_w
+# *** RV32C and RV64C specific Standard Extension (Quadrant 0) ***
+{
+ ld 011 ... ... .. ... 00 @cl_d
+ flw 011 ... ... .. ... 00 @cl_w
+}
+{
+ sd 111 ... ... .. ... 00 @cs_d
+ fsw 111 ... ... .. ... 00 @cs_w
+}
+
# *** RV32/64C Standard Extension (Quadrant 1) ***
addi 000 . ..... ..... 01 @ci
addi 010 . ..... ..... 01 @c_li
@@ -111,6 +121,15 @@ jal 101 ........... 01 @cj rd=0 # C.J
beq 110 ... ... ..... 01 @cb_z
bne 111 ... ... ..... 01 @cb_z
+# *** RV64C and RV32C specific Standard Extension (Quadrant 1) ***
+{
+ c64_illegal 001 - 00000 ----- 01 # c.addiw, RES rd=0
+ addiw 001 . ..... ..... 01 @ci
+ jal 001 ........... 01 @cj rd=1 # C.JAL
+}
+subw 100 1 11 ... 00 ... 01 @cs_2
+addw 100 1 11 ... 01 ... 01 @cs_2
+
# *** RV32/64C Standard Extension (Quadrant 2) ***
slli 000 . ..... ..... 10 @c_shift2
fld 001 . ..... ..... 10 @c_ldsp
@@ -130,3 +149,14 @@ fld 001 . ..... ..... 10 @c_ldsp
}
fsd 101 ...... ..... 10 @c_sdsp
sw 110 . ..... ..... 10 @c_swsp
+
+# *** RV32C and RV64C specific Standard Extension (Quadrant 2) ***
+{
+ c64_illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=0
+ ld 011 . ..... ..... 10 @c_ldsp
+ flw 011 . ..... ..... 10 @c_lwsp
+}
+{
+ sd 111 . ..... ..... 10 @c_sdsp
+ fsw 111 . ..... ..... 10 @c_swsp
+}
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 1340676209..bd93f634cf 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -24,6 +24,12 @@ static bool trans_illegal(DisasContext *ctx, arg_empty *a)
return true;
}
+static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
+{
+ REQUIRE_64BIT(ctx);
+ return trans_illegal(ctx, a);
+}
+
static bool trans_lui(DisasContext *ctx, arg_lui *a)
{
if (a->rd != 0) {
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index 24bf049164..af6c3416b7 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -1,18 +1,13 @@
# FIXME extra_args should accept files()
dir = meson.current_source_dir()
-gen32 = [
- decodetree.process('insn16.decode', extra_args: [dir / 'insn16-32.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
- decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
-]
-gen64 = [
- decodetree.process('insn16.decode', extra_args: [dir / 'insn16-64.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
+gen = [
+ decodetree.process('insn16.decode', extra_args: ['--static-decode=decode_insn16', '--insnwidth=16']),
decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
]
riscv_ss = ss.source_set()
-riscv_ss.add(when: 'TARGET_RISCV32', if_true: gen32)
-riscv_ss.add(when: 'TARGET_RISCV64', if_true: gen64)
+riscv_ss.add(gen)
riscv_ss.add(files(
'cpu.c',
'cpu_helper.c',
--
2.31.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 09/10] target/riscv: Consolidate RV32/64 16-bit instructions
@ 2021-04-24 3:34 ` Alistair Francis
0 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-24 3:34 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
This patch removes the insn16-32.decode and insn16-64.decode decode
files and consolidates the instructions into the general RISC-V
insn16.decode decode tree.
This means that all of the instructions are avaliable in both the 32-bit
and 64-bit builds. This also means that we run a check to ensure we are
running a 64-bit softmmu before we execute the 64-bit only instructions.
This allows us to include the 32-bit instructions in the 64-bit build,
while also ensuring that 32-bit only software can not execute the
instructions.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn16-32.decode | 28 -------------------
target/riscv/insn16-64.decode | 36 -------------------------
target/riscv/insn16.decode | 30 +++++++++++++++++++++
target/riscv/insn_trans/trans_rvi.c.inc | 6 +++++
target/riscv/meson.build | 11 +++-----
5 files changed, 39 insertions(+), 72 deletions(-)
delete mode 100644 target/riscv/insn16-32.decode
delete mode 100644 target/riscv/insn16-64.decode
diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode
deleted file mode 100644
index 0819b17028..0000000000
--- a/target/riscv/insn16-32.decode
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# RISC-V translation routines for the RVXI Base Integer Instruction Set.
-#
-# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
-# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2 or later, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License along with
-# this program. If not, see <http://www.gnu.org/licenses/>.
-
-# *** RV32C Standard Extension (Quadrant 0) ***
-flw 011 ... ... .. ... 00 @cl_w
-fsw 111 ... ... .. ... 00 @cs_w
-
-# *** RV32C Standard Extension (Quadrant 1) ***
-jal 001 ........... 01 @cj rd=1 # C.JAL
-
-# *** RV32C Standard Extension (Quadrant 2) ***
-flw 011 . ..... ..... 10 @c_lwsp
-fsw 111 . ..... ..... 10 @c_swsp
diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode
deleted file mode 100644
index 672e1e916f..0000000000
--- a/target/riscv/insn16-64.decode
+++ /dev/null
@@ -1,36 +0,0 @@
-#
-# RISC-V translation routines for the RVXI Base Integer Instruction Set.
-#
-# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
-# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2 or later, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License along with
-# this program. If not, see <http://www.gnu.org/licenses/>.
-
-# *** RV64C Standard Extension (Quadrant 0) ***
-ld 011 ... ... .. ... 00 @cl_d
-sd 111 ... ... .. ... 00 @cs_d
-
-# *** RV64C Standard Extension (Quadrant 1) ***
-{
- illegal 001 - 00000 ----- 01 # c.addiw, RES rd=0
- addiw 001 . ..... ..... 01 @ci
-}
-subw 100 1 11 ... 00 ... 01 @cs_2
-addw 100 1 11 ... 01 ... 01 @cs_2
-
-# *** RV64C Standard Extension (Quadrant 2) ***
-{
- illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=0
- ld 011 . ..... ..... 10 @c_ldsp
-}
-sd 111 . ..... ..... 10 @c_sdsp
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 1cb93876fe..2e9212663c 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -92,6 +92,16 @@ lw 010 ... ... .. ... 00 @cl_w
fsd 101 ... ... .. ... 00 @cs_d
sw 110 ... ... .. ... 00 @cs_w
+# *** RV32C and RV64C specific Standard Extension (Quadrant 0) ***
+{
+ ld 011 ... ... .. ... 00 @cl_d
+ flw 011 ... ... .. ... 00 @cl_w
+}
+{
+ sd 111 ... ... .. ... 00 @cs_d
+ fsw 111 ... ... .. ... 00 @cs_w
+}
+
# *** RV32/64C Standard Extension (Quadrant 1) ***
addi 000 . ..... ..... 01 @ci
addi 010 . ..... ..... 01 @c_li
@@ -111,6 +121,15 @@ jal 101 ........... 01 @cj rd=0 # C.J
beq 110 ... ... ..... 01 @cb_z
bne 111 ... ... ..... 01 @cb_z
+# *** RV64C and RV32C specific Standard Extension (Quadrant 1) ***
+{
+ c64_illegal 001 - 00000 ----- 01 # c.addiw, RES rd=0
+ addiw 001 . ..... ..... 01 @ci
+ jal 001 ........... 01 @cj rd=1 # C.JAL
+}
+subw 100 1 11 ... 00 ... 01 @cs_2
+addw 100 1 11 ... 01 ... 01 @cs_2
+
# *** RV32/64C Standard Extension (Quadrant 2) ***
slli 000 . ..... ..... 10 @c_shift2
fld 001 . ..... ..... 10 @c_ldsp
@@ -130,3 +149,14 @@ fld 001 . ..... ..... 10 @c_ldsp
}
fsd 101 ...... ..... 10 @c_sdsp
sw 110 . ..... ..... 10 @c_swsp
+
+# *** RV32C and RV64C specific Standard Extension (Quadrant 2) ***
+{
+ c64_illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=0
+ ld 011 . ..... ..... 10 @c_ldsp
+ flw 011 . ..... ..... 10 @c_lwsp
+}
+{
+ sd 111 . ..... ..... 10 @c_sdsp
+ fsw 111 . ..... ..... 10 @c_swsp
+}
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 1340676209..bd93f634cf 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -24,6 +24,12 @@ static bool trans_illegal(DisasContext *ctx, arg_empty *a)
return true;
}
+static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
+{
+ REQUIRE_64BIT(ctx);
+ return trans_illegal(ctx, a);
+}
+
static bool trans_lui(DisasContext *ctx, arg_lui *a)
{
if (a->rd != 0) {
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index 24bf049164..af6c3416b7 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -1,18 +1,13 @@
# FIXME extra_args should accept files()
dir = meson.current_source_dir()
-gen32 = [
- decodetree.process('insn16.decode', extra_args: [dir / 'insn16-32.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
- decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
-]
-gen64 = [
- decodetree.process('insn16.decode', extra_args: [dir / 'insn16-64.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
+gen = [
+ decodetree.process('insn16.decode', extra_args: ['--static-decode=decode_insn16', '--insnwidth=16']),
decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
]
riscv_ss = ss.source_set()
-riscv_ss.add(when: 'TARGET_RISCV32', if_true: gen32)
-riscv_ss.add(when: 'TARGET_RISCV64', if_true: gen64)
+riscv_ss.add(gen)
riscv_ss.add(files(
'cpu.c',
'cpu_helper.c',
--
2.31.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 10/10] target/riscv: Fix the RV64H decode comment
2021-04-24 3:28 ` Alistair Francis
@ 2021-04-24 3:34 ` Alistair Francis
-1 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-24 3:34 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, bmeng.cn, palmer, alistair23
BugLink: https://gitlab.com/qemu-project/qemu/-/issues/6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index fecf0f15d5..8901ba1e1b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -288,7 +288,7 @@ hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s
hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
-# *** RV32H Base Instruction Set ***
+# *** RV64H Base Instruction Set ***
hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
--
2.31.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 10/10] target/riscv: Fix the RV64H decode comment
@ 2021-04-24 3:34 ` Alistair Francis
0 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-24 3:34 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
BugLink: https://gitlab.com/qemu-project/qemu/-/issues/6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index fecf0f15d5..8901ba1e1b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -288,7 +288,7 @@ hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s
hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
-# *** RV32H Base Instruction Set ***
+# *** RV64H Base Instruction Set ***
hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
--
2.31.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [PATCH v3 08/10] target/riscv: Consolidate RV32/64 32-bit instructions
2021-04-24 3:34 ` Alistair Francis
@ 2021-04-24 17:08 ` Richard Henderson
-1 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2021-04-24 17:08 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: alistair23, bmeng.cn, palmer
On 4/23/21 8:34 PM, Alistair Francis wrote:
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -74,8 +74,6 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
>
> #ifdef TARGET_RISCV32
> # define is_32bit(ctx) true
> -#elif defined(CONFIG_USER_ONLY)
> -# define is_32bit(ctx) false
> #else
> static inline bool is_32bit(DisasContext *ctx)
> {
Rebase error?
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v3 08/10] target/riscv: Consolidate RV32/64 32-bit instructions
@ 2021-04-24 17:08 ` Richard Henderson
0 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2021-04-24 17:08 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair23
On 4/23/21 8:34 PM, Alistair Francis wrote:
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -74,8 +74,6 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
>
> #ifdef TARGET_RISCV32
> # define is_32bit(ctx) true
> -#elif defined(CONFIG_USER_ONLY)
> -# define is_32bit(ctx) false
> #else
> static inline bool is_32bit(DisasContext *ctx)
> {
Rebase error?
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v3 10/10] target/riscv: Fix the RV64H decode comment
2021-04-24 3:34 ` Alistair Francis
@ 2021-04-24 17:14 ` Richard Henderson
-1 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2021-04-24 17:14 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: alistair23, bmeng.cn, palmer
On 4/23/21 8:34 PM, Alistair Francis wrote:
> BugLink: https://gitlab.com/qemu-project/qemu/-/issues/6
The issue got renumbered to 47, fwiw.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/insn32.decode | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index fecf0f15d5..8901ba1e1b 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -288,7 +288,7 @@ hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s
> hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
> hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
>
> -# *** RV32H Base Instruction Set ***
> +# *** RV64H Base Instruction Set ***
> hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
> hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
> hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v3 10/10] target/riscv: Fix the RV64H decode comment
@ 2021-04-24 17:14 ` Richard Henderson
0 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2021-04-24 17:14 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair23
On 4/23/21 8:34 PM, Alistair Francis wrote:
> BugLink: https://gitlab.com/qemu-project/qemu/-/issues/6
The issue got renumbered to 47, fwiw.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/insn32.decode | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index fecf0f15d5..8901ba1e1b 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -288,7 +288,7 @@ hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s
> hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
> hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
>
> -# *** RV32H Base Instruction Set ***
> +# *** RV64H Base Instruction Set ***
> hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
> hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
> hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v3 08/10] target/riscv: Consolidate RV32/64 32-bit instructions
2021-04-24 17:08 ` Richard Henderson
@ 2021-04-25 22:58 ` Alistair Francis
-1 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-25 22:58 UTC (permalink / raw)
To: Richard Henderson
Cc: open list:RISC-V, Palmer Dabbelt, Bin Meng, Alistair Francis,
qemu-devel@nongnu.org Developers
On Sun, Apr 25, 2021 at 3:08 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 4/23/21 8:34 PM, Alistair Francis wrote:
> > --- a/target/riscv/translate.c
> > +++ b/target/riscv/translate.c
> > @@ -74,8 +74,6 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
> >
> > #ifdef TARGET_RISCV32
> > # define is_32bit(ctx) true
> > -#elif defined(CONFIG_USER_ONLY)
> > -# define is_32bit(ctx) false
> > #else
> > static inline bool is_32bit(DisasContext *ctx)
> > {
>
> Rebase error?
This is required to avoid warnings/errors before this commit as
`is_32bit()` isn't called until this patch.
Alistair
>
> Otherwise,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
>
> r~
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v3 08/10] target/riscv: Consolidate RV32/64 32-bit instructions
@ 2021-04-25 22:58 ` Alistair Francis
0 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-25 22:58 UTC (permalink / raw)
To: Richard Henderson
Cc: Alistair Francis, qemu-devel@nongnu.org Developers,
open list:RISC-V, Bin Meng, Palmer Dabbelt
On Sun, Apr 25, 2021 at 3:08 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 4/23/21 8:34 PM, Alistair Francis wrote:
> > --- a/target/riscv/translate.c
> > +++ b/target/riscv/translate.c
> > @@ -74,8 +74,6 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
> >
> > #ifdef TARGET_RISCV32
> > # define is_32bit(ctx) true
> > -#elif defined(CONFIG_USER_ONLY)
> > -# define is_32bit(ctx) false
> > #else
> > static inline bool is_32bit(DisasContext *ctx)
> > {
>
> Rebase error?
This is required to avoid warnings/errors before this commit as
`is_32bit()` isn't called until this patch.
Alistair
>
> Otherwise,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
>
> r~
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v3 10/10] target/riscv: Fix the RV64H decode comment
2021-04-24 17:14 ` Richard Henderson
@ 2021-04-25 22:58 ` Alistair Francis
-1 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-25 22:58 UTC (permalink / raw)
To: Richard Henderson
Cc: open list:RISC-V, Palmer Dabbelt, Bin Meng, Alistair Francis,
qemu-devel@nongnu.org Developers
On Sun, Apr 25, 2021 at 3:14 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 4/23/21 8:34 PM, Alistair Francis wrote:
> > BugLink: https://gitlab.com/qemu-project/qemu/-/issues/6
>
> The issue got renumbered to 47, fwiw.
Thanks!
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> r~
>
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > target/riscv/insn32.decode | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> > index fecf0f15d5..8901ba1e1b 100644
> > --- a/target/riscv/insn32.decode
> > +++ b/target/riscv/insn32.decode
> > @@ -288,7 +288,7 @@ hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s
> > hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
> > hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
> >
> > -# *** RV32H Base Instruction Set ***
> > +# *** RV64H Base Instruction Set ***
> > hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
> > hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
> > hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
> >
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v3 10/10] target/riscv: Fix the RV64H decode comment
@ 2021-04-25 22:58 ` Alistair Francis
0 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-25 22:58 UTC (permalink / raw)
To: Richard Henderson
Cc: Alistair Francis, qemu-devel@nongnu.org Developers,
open list:RISC-V, Bin Meng, Palmer Dabbelt
On Sun, Apr 25, 2021 at 3:14 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 4/23/21 8:34 PM, Alistair Francis wrote:
> > BugLink: https://gitlab.com/qemu-project/qemu/-/issues/6
>
> The issue got renumbered to 47, fwiw.
Thanks!
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> r~
>
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > target/riscv/insn32.decode | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> > index fecf0f15d5..8901ba1e1b 100644
> > --- a/target/riscv/insn32.decode
> > +++ b/target/riscv/insn32.decode
> > @@ -288,7 +288,7 @@ hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s
> > hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
> > hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
> >
> > -# *** RV32H Base Instruction Set ***
> > +# *** RV64H Base Instruction Set ***
> > hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
> > hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
> > hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
> >
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v3 00/10] RISC-V: Steps towards running 32-bit guests on
2021-04-24 3:28 ` Alistair Francis
@ 2021-04-25 22:58 ` Alistair Francis
-1 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-25 22:58 UTC (permalink / raw)
To: Alistair Francis
Cc: Palmer Dabbelt, Bin Meng, open list:RISC-V,
qemu-devel@nongnu.org Developers
On Sat, Apr 24, 2021 at 1:28 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> This is another step towards running 32-bit CPU code on the 64-bit
> softmmu builds for RISC-V.
>
> I have tested this and am able to run some 32-bit code, but eventually
> hit some issue. This series doesn't allow users to use 32-bit CPUs with
> 64-bit softmmu builds as it doesn't work yet. This series instead just
> gets us a little closer to being able to and removes more hardcoded
> macros so hopefully others also stop using them for new code.
>
> v3:
> - Remove casts from the decoder
> - Add a patch to fix a comment
> - Rebase on the RISC-V tree
> v2:
> - Update the decode tree setup
> - Address other review comments
>
> Alistair Francis (10):
> target/riscv: Remove the hardcoded RVXLEN macro
> target/riscv: Remove the hardcoded SSTATUS_SD macro
> target/riscv: Remove the hardcoded HGATP_MODE macro
> target/riscv: Remove the hardcoded MSTATUS_SD macro
> target/riscv: Remove the hardcoded SATP_MODE macro
> target/riscv: Remove the unused HSTATUS_WPRI macro
> target/riscv: Remove an unused CASE_OP_32_64 macro
> target/riscv: Consolidate RV32/64 32-bit instructions
> target/riscv: Consolidate RV32/64 16-bit instructions
> target/riscv: Fix the RV64H decode comment
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> target/riscv/cpu.h | 6 --
> target/riscv/cpu_bits.h | 44 -------------
> target/riscv/helper.h | 18 +++--
> target/riscv/insn16-32.decode | 28 --------
> target/riscv/insn16-64.decode | 36 ----------
> target/riscv/insn16.decode | 30 +++++++++
> target/riscv/insn32-64.decode | 88 -------------------------
> target/riscv/insn32.decode | 67 ++++++++++++++++++-
> target/riscv/cpu.c | 6 +-
> target/riscv/cpu_helper.c | 48 ++++++++++----
> target/riscv/csr.c | 40 +++++++++--
> target/riscv/fpu_helper.c | 16 ++---
> target/riscv/monitor.c | 22 +++++--
> target/riscv/translate.c | 32 +++++----
> target/riscv/vector_helper.c | 4 --
> target/riscv/insn_trans/trans_rva.c.inc | 14 +++-
> target/riscv/insn_trans/trans_rvd.c.inc | 17 ++++-
> target/riscv/insn_trans/trans_rvf.c.inc | 6 +-
> target/riscv/insn_trans/trans_rvh.c.inc | 8 ++-
> target/riscv/insn_trans/trans_rvi.c.inc | 22 +++++--
> target/riscv/insn_trans/trans_rvm.c.inc | 12 +++-
> target/riscv/insn_trans/trans_rvv.c.inc | 39 +++++------
> target/riscv/meson.build | 13 ++--
> 23 files changed, 310 insertions(+), 306 deletions(-)
> delete mode 100644 target/riscv/insn16-32.decode
> delete mode 100644 target/riscv/insn16-64.decode
> delete mode 100644 target/riscv/insn32-64.decode
>
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v3 00/10] RISC-V: Steps towards running 32-bit guests on
@ 2021-04-25 22:58 ` Alistair Francis
0 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-25 22:58 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Bin Meng,
Palmer Dabbelt
On Sat, Apr 24, 2021 at 1:28 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> This is another step towards running 32-bit CPU code on the 64-bit
> softmmu builds for RISC-V.
>
> I have tested this and am able to run some 32-bit code, but eventually
> hit some issue. This series doesn't allow users to use 32-bit CPUs with
> 64-bit softmmu builds as it doesn't work yet. This series instead just
> gets us a little closer to being able to and removes more hardcoded
> macros so hopefully others also stop using them for new code.
>
> v3:
> - Remove casts from the decoder
> - Add a patch to fix a comment
> - Rebase on the RISC-V tree
> v2:
> - Update the decode tree setup
> - Address other review comments
>
> Alistair Francis (10):
> target/riscv: Remove the hardcoded RVXLEN macro
> target/riscv: Remove the hardcoded SSTATUS_SD macro
> target/riscv: Remove the hardcoded HGATP_MODE macro
> target/riscv: Remove the hardcoded MSTATUS_SD macro
> target/riscv: Remove the hardcoded SATP_MODE macro
> target/riscv: Remove the unused HSTATUS_WPRI macro
> target/riscv: Remove an unused CASE_OP_32_64 macro
> target/riscv: Consolidate RV32/64 32-bit instructions
> target/riscv: Consolidate RV32/64 16-bit instructions
> target/riscv: Fix the RV64H decode comment
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> target/riscv/cpu.h | 6 --
> target/riscv/cpu_bits.h | 44 -------------
> target/riscv/helper.h | 18 +++--
> target/riscv/insn16-32.decode | 28 --------
> target/riscv/insn16-64.decode | 36 ----------
> target/riscv/insn16.decode | 30 +++++++++
> target/riscv/insn32-64.decode | 88 -------------------------
> target/riscv/insn32.decode | 67 ++++++++++++++++++-
> target/riscv/cpu.c | 6 +-
> target/riscv/cpu_helper.c | 48 ++++++++++----
> target/riscv/csr.c | 40 +++++++++--
> target/riscv/fpu_helper.c | 16 ++---
> target/riscv/monitor.c | 22 +++++--
> target/riscv/translate.c | 32 +++++----
> target/riscv/vector_helper.c | 4 --
> target/riscv/insn_trans/trans_rva.c.inc | 14 +++-
> target/riscv/insn_trans/trans_rvd.c.inc | 17 ++++-
> target/riscv/insn_trans/trans_rvf.c.inc | 6 +-
> target/riscv/insn_trans/trans_rvh.c.inc | 8 ++-
> target/riscv/insn_trans/trans_rvi.c.inc | 22 +++++--
> target/riscv/insn_trans/trans_rvm.c.inc | 12 +++-
> target/riscv/insn_trans/trans_rvv.c.inc | 39 +++++------
> target/riscv/meson.build | 13 ++--
> 23 files changed, 310 insertions(+), 306 deletions(-)
> delete mode 100644 target/riscv/insn16-32.decode
> delete mode 100644 target/riscv/insn16-64.decode
> delete mode 100644 target/riscv/insn32-64.decode
>
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v3 08/10] target/riscv: Consolidate RV32/64 32-bit instructions
2021-04-25 22:58 ` Alistair Francis
@ 2021-04-25 23:53 ` Richard Henderson
-1 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2021-04-25 23:53 UTC (permalink / raw)
To: Alistair Francis
Cc: open list:RISC-V, Palmer Dabbelt, Bin Meng, Alistair Francis,
qemu-devel@nongnu.org Developers
On 4/25/21 3:58 PM, Alistair Francis wrote:
> On Sun, Apr 25, 2021 at 3:08 AM Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> On 4/23/21 8:34 PM, Alistair Francis wrote:
>>> --- a/target/riscv/translate.c
>>> +++ b/target/riscv/translate.c
>>> @@ -74,8 +74,6 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
>>>
>>> #ifdef TARGET_RISCV32
>>> # define is_32bit(ctx) true
>>> -#elif defined(CONFIG_USER_ONLY)
>>> -# define is_32bit(ctx) false
>>> #else
>>> static inline bool is_32bit(DisasContext *ctx)
>>> {
>>
>> Rebase error?
>
> This is required to avoid warnings/errors before this commit as
> `is_32bit()` isn't called until this patch.
If !defined(TARGET_RISCV32) && defined(CONFIG_USER_ONLY), then is_32bit *is*
false. This isn't system mode and it can't be changed.
r~
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v3 08/10] target/riscv: Consolidate RV32/64 32-bit instructions
@ 2021-04-25 23:53 ` Richard Henderson
0 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2021-04-25 23:53 UTC (permalink / raw)
To: Alistair Francis
Cc: Alistair Francis, qemu-devel@nongnu.org Developers,
open list:RISC-V, Bin Meng, Palmer Dabbelt
On 4/25/21 3:58 PM, Alistair Francis wrote:
> On Sun, Apr 25, 2021 at 3:08 AM Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> On 4/23/21 8:34 PM, Alistair Francis wrote:
>>> --- a/target/riscv/translate.c
>>> +++ b/target/riscv/translate.c
>>> @@ -74,8 +74,6 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
>>>
>>> #ifdef TARGET_RISCV32
>>> # define is_32bit(ctx) true
>>> -#elif defined(CONFIG_USER_ONLY)
>>> -# define is_32bit(ctx) false
>>> #else
>>> static inline bool is_32bit(DisasContext *ctx)
>>> {
>>
>> Rebase error?
>
> This is required to avoid warnings/errors before this commit as
> `is_32bit()` isn't called until this patch.
If !defined(TARGET_RISCV32) && defined(CONFIG_USER_ONLY), then is_32bit *is*
false. This isn't system mode and it can't be changed.
r~
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v3 08/10] target/riscv: Consolidate RV32/64 32-bit instructions
2021-04-25 23:53 ` Richard Henderson
@ 2021-04-26 5:33 ` Alistair Francis
-1 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-26 5:33 UTC (permalink / raw)
To: Richard Henderson
Cc: open list:RISC-V, Palmer Dabbelt, Bin Meng, Alistair Francis,
qemu-devel@nongnu.org Developers
On Mon, Apr 26, 2021 at 9:53 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 4/25/21 3:58 PM, Alistair Francis wrote:
> > On Sun, Apr 25, 2021 at 3:08 AM Richard Henderson
> > <richard.henderson@linaro.org> wrote:
> >>
> >> On 4/23/21 8:34 PM, Alistair Francis wrote:
> >>> --- a/target/riscv/translate.c
> >>> +++ b/target/riscv/translate.c
> >>> @@ -74,8 +74,6 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
> >>>
> >>> #ifdef TARGET_RISCV32
> >>> # define is_32bit(ctx) true
> >>> -#elif defined(CONFIG_USER_ONLY)
> >>> -# define is_32bit(ctx) false
> >>> #else
> >>> static inline bool is_32bit(DisasContext *ctx)
> >>> {
> >>
> >> Rebase error?
> >
> > This is required to avoid warnings/errors before this commit as
> > `is_32bit()` isn't called until this patch.
>
> If !defined(TARGET_RISCV32) && defined(CONFIG_USER_ONLY), then is_32bit *is*
> false. This isn't system mode and it can't be changed.
Ah ok. I have reverted this removal then.
Alistair
>
>
> r~
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v3 08/10] target/riscv: Consolidate RV32/64 32-bit instructions
@ 2021-04-26 5:33 ` Alistair Francis
0 siblings, 0 replies; 36+ messages in thread
From: Alistair Francis @ 2021-04-26 5:33 UTC (permalink / raw)
To: Richard Henderson
Cc: Alistair Francis, qemu-devel@nongnu.org Developers,
open list:RISC-V, Bin Meng, Palmer Dabbelt
On Mon, Apr 26, 2021 at 9:53 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 4/25/21 3:58 PM, Alistair Francis wrote:
> > On Sun, Apr 25, 2021 at 3:08 AM Richard Henderson
> > <richard.henderson@linaro.org> wrote:
> >>
> >> On 4/23/21 8:34 PM, Alistair Francis wrote:
> >>> --- a/target/riscv/translate.c
> >>> +++ b/target/riscv/translate.c
> >>> @@ -74,8 +74,6 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
> >>>
> >>> #ifdef TARGET_RISCV32
> >>> # define is_32bit(ctx) true
> >>> -#elif defined(CONFIG_USER_ONLY)
> >>> -# define is_32bit(ctx) false
> >>> #else
> >>> static inline bool is_32bit(DisasContext *ctx)
> >>> {
> >>
> >> Rebase error?
> >
> > This is required to avoid warnings/errors before this commit as
> > `is_32bit()` isn't called until this patch.
>
> If !defined(TARGET_RISCV32) && defined(CONFIG_USER_ONLY), then is_32bit *is*
> false. This isn't system mode and it can't be changed.
Ah ok. I have reverted this removal then.
Alistair
>
>
> r~
^ permalink raw reply [flat|nested] 36+ messages in thread
end of thread, other threads:[~2021-04-26 5:35 UTC | newest]
Thread overview: 36+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-04-24 3:28 [PATCH v3 00/10] RISC-V: Steps towards running 32-bit guests on Alistair Francis
2021-04-24 3:28 ` Alistair Francis
2021-04-24 3:28 ` [PATCH v3 01/10] target/riscv: Remove the hardcoded RVXLEN macro Alistair Francis
2021-04-24 3:28 ` Alistair Francis
2021-04-24 3:29 ` [PATCH v3 02/10] target/riscv: Remove the hardcoded SSTATUS_SD macro Alistair Francis
2021-04-24 3:29 ` Alistair Francis
2021-04-24 3:31 ` [PATCH v3 03/10] target/riscv: Remove the hardcoded HGATP_MODE macro Alistair Francis
2021-04-24 3:31 ` Alistair Francis
2021-04-24 3:33 ` [PATCH v3 04/10] target/riscv: Remove the hardcoded MSTATUS_SD macro Alistair Francis
2021-04-24 3:33 ` Alistair Francis
2021-04-24 3:33 ` [PATCH v3 05/10] target/riscv: Remove the hardcoded SATP_MODE macro Alistair Francis
2021-04-24 3:33 ` Alistair Francis
2021-04-24 3:33 ` [PATCH v3 06/10] target/riscv: Remove the unused HSTATUS_WPRI macro Alistair Francis
2021-04-24 3:33 ` Alistair Francis
2021-04-24 3:34 ` [PATCH v3 07/10] target/riscv: Remove an unused CASE_OP_32_64 macro Alistair Francis
2021-04-24 3:34 ` Alistair Francis
2021-04-24 3:34 ` [PATCH v3 08/10] target/riscv: Consolidate RV32/64 32-bit instructions Alistair Francis
2021-04-24 3:34 ` Alistair Francis
2021-04-24 17:08 ` Richard Henderson
2021-04-24 17:08 ` Richard Henderson
2021-04-25 22:58 ` Alistair Francis
2021-04-25 22:58 ` Alistair Francis
2021-04-25 23:53 ` Richard Henderson
2021-04-25 23:53 ` Richard Henderson
2021-04-26 5:33 ` Alistair Francis
2021-04-26 5:33 ` Alistair Francis
2021-04-24 3:34 ` [PATCH v3 09/10] target/riscv: Consolidate RV32/64 16-bit instructions Alistair Francis
2021-04-24 3:34 ` Alistair Francis
2021-04-24 3:34 ` [PATCH v3 10/10] target/riscv: Fix the RV64H decode comment Alistair Francis
2021-04-24 3:34 ` Alistair Francis
2021-04-24 17:14 ` Richard Henderson
2021-04-24 17:14 ` Richard Henderson
2021-04-25 22:58 ` Alistair Francis
2021-04-25 22:58 ` Alistair Francis
2021-04-25 22:58 ` [PATCH v3 00/10] RISC-V: Steps towards running 32-bit guests on Alistair Francis
2021-04-25 22:58 ` Alistair Francis
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