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Thu, 02 Jun 2022 09:08:48 -0700 Message-ID: <6b87b48e-d030-9942-6204-bd5d645faf49@xilinx.com> Date: Thu, 2 Jun 2022 09:08:47 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [PATCH v6 1/6] dt-bindings: remoteproc: Add Xilinx RPU subsystem bindings Content-Language: en-US To: Rob Herring CC: , , , , , , , , , References: <20220531234308.3317795-1-tanmay.shah@xilinx.com> <20220531234308.3317795-2-tanmay.shah@xilinx.com> <20220601184240.GA188558-robh@kernel.org> <20220602151409.GA2333778-robh@kernel.org> From: Tanmay Shah In-Reply-To: <20220602151409.GA2333778-robh@kernel.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 37c50f37-848a-4886-7763-08da44b234ec X-MS-TrafficTypeDiagnostic: CY4PR02MB2327:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jun 2022 16:09:00.8188 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 37c50f37-848a-4886-7763-08da44b234ec X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT022.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR02MB2327 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org On 6/2/22 8:14 AM, Rob Herring wrote: > On Wed, Jun 01, 2022 at 12:05:09PM -0700, Tanmay Shah wrote: >> Hi Rob, >> >> Thanks for reviews. Please find my comments below: >> >> On 6/1/22 11:42 AM, Rob Herring wrote: >>> On Tue, May 31, 2022 at 04:43:05PM -0700, Tanmay Shah wrote: >>>> Xilinx ZynqMP platform has dual-core ARM Cortex R5 Realtime Processing >>>> Unit(RPU) subsystem. This patch adds dt-bindings for RPU subsystem >>>> (cluster). >>>> >>>> Signed-off-by: Tanmay Shah >>>> --- >>>> >>>> Changes in v6: >>>> - Add maxItems to sram and memory-region property >>>> >>>> Changes in v5: >>>> - Add constraints of the possible values of xlnx,cluster-mode property >>>> - fix description of power-domains property for r5 core >>>> - Remove reg, address-cells and size-cells properties as it is not required >>>> - Fix description of mboxes property >>>> - Add description of each memory-region and remove old .txt binding link >>>> reference in the description >>>> >>>> Changes in v4: >>>> - Add memory-region, mboxes and mbox-names properties in example >>>> >>>> Changes in v3: >>>> - None >>>> >>>> >>>> .../bindings/remoteproc/xlnx,r5f-rproc.yaml | 129 ++++++++++++++++++ >>>> include/dt-bindings/power/xlnx-zynqmp-power.h | 6 + >>>> 2 files changed, 135 insertions(+) >>>> create mode 100644 Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml >>>> >>>> diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml >>>> new file mode 100644 >>>> index 000000000000..cbff1c201a89 >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml >>>> @@ -0,0 +1,129 @@ >>>> +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) >>>> +%YAML 1.2 >>>> +--- >>>> +$id: http://devicetree.org/schemas/remoteproc/xlnx,r5f-rproc.yaml# >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>> + >>>> +title: Xilinx R5F processor subsystem >>>> + >>>> +maintainers: >>>> + - Ben Levinsky >>>> + - Tanmay Shah >>>> + >>>> +description: | >>>> + The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for >>>> + real-time processing based on the Cortex-R5F processor core from ARM. >>>> + The Cortex-R5F processor implements the Arm v7-R architecture and includes a >>>> + floating-point unit that implements the Arm VFPv3 instruction set. >>>> + >>>> +properties: >>>> + compatible: >>>> + const: xlnx,zynqmp-r5fss >>>> + >>>> + xlnx,cluster-mode: >>>> + $ref: /schemas/types.yaml#/definitions/uint32 >>>> + enum: [0, 1, 2] >>>> + description: | >>>> + The RPU MPCore can operate in split mode(Dual-processor performance), Safety >>>> + lock-step mode(Both RPU cores execute the same code in lock-step, >>>> + clock-for-clock) or Single CPU mode (RPU core 0 can be held in reset while >>>> + core 1 runs normally). The processor does not support dynamic configuration. >>>> + Switching between modes is only permitted immediately after a processor reset. >>>> + If set to 1 then lockstep mode and if 0 then split mode. >>>> + If set to 2 then single CPU mode. When not defined, default will be lockstep mode. >>>> + >>>> +patternProperties: >>>> + "^r5f-[a-f0-9]+$": >>>> + type: object >>>> + description: | >>>> + The RPU is located in the Low Power Domain of the Processor Subsystem. >>>> + Each processor includes separate L1 instruction and data caches and >>>> + tightly coupled memories (TCM). System memory is cacheable, but the TCM >>>> + memory space is non-cacheable. >>>> + >>>> + Each RPU contains one 64KB memory and two 32KB memories that >>>> + are accessed via the TCM A and B port interfaces, for a total of 128KB >>>> + per processor. In lock-step mode, the processor has access to 256KB of >>>> + TCM memory. >>>> + >>>> + properties: >>>> + compatible: >>>> + const: xlnx,zynqmp-r5f >>>> + >>>> + power-domains: >>>> + description: RPU core PM domain specifier >>>> + maxItems: 1 >>>> + >>>> + mboxes: >>>> + minItems: 1 >>>> + items: >>>> + - description: mailbox channel to send data to RPU >>>> + - description: mailbox channel to receive data from RPU >>>> + >>>> + mbox-names: >>>> + minItems: 1 >>>> + items: >>>> + - const: tx >>>> + - const: rx >>>> + >>>> + sram: >>>> + $ref: /schemas/types.yaml#/definitions/phandle-array >>>> + maxItems: 8 >>> minItems: 1 >>> maxItems: 8 >>> items: >>> maxItems: 1 >> I have posted v7 which adds "minItems: 1". >> >> However, I didn't get items: part. Is it required to have items: now? > Yes. >> Can I add items: part once TCM bindings are posted? > No. > >> I understand that minItems and maxItems under sram property decides how many >> phandles sram can have. >> >> However, maxItems: 1 under items: field what it describes? > 'phandle-array' is really a matrix type because we can have phandles > plus argument cells. So you have to define each of the 1-8 entries is a > single phandle cell (and no arg cells). Thanks for explanation. I will send new revision as suggested. > > Rob From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A6459C43334 for ; Thu, 2 Jun 2022 16:10:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:CC:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=BUDcs/xRnnhsB625YBrMrSGIsPOBYK4cE7hjuDHOeWE=; b=PFLXwBPuomPhGo z+m0HT+4KgP8uFy8E0JE9OsAgz7EkX/8CFwesZQFkRXlLhwQAYrtJNF3GIZtui+m/br7tVe+lKdy8 ravwBZWlYIuXrUubljgWONa7iR0gQ0mYTq1AneXNFrQa7LNdDDobdaV+dcivgqbug3C8IeD2aMM4N UUMQBco9QDy+1p2ZC9PIPGMAXHo7o1gBqAS4fT9gZ7XBHSYtAOC8vnPqwqj6fw5dW5lSihDMHUnMW ali+/qRxYrTKmka0xOu5G4t5gnn7mZrpoZm8fTBnmGSLPibLyjNMvHPa+6Qhf5N/jw5fQH7NQ0nUH uomqHBMMeo16wZm3/4kg==; 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charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 6/2/22 8:14 AM, Rob Herring wrote: > On Wed, Jun 01, 2022 at 12:05:09PM -0700, Tanmay Shah wrote: >> Hi Rob, >> >> Thanks for reviews. Please find my comments below: >> >> On 6/1/22 11:42 AM, Rob Herring wrote: >>> On Tue, May 31, 2022 at 04:43:05PM -0700, Tanmay Shah wrote: >>>> Xilinx ZynqMP platform has dual-core ARM Cortex R5 Realtime Processing >>>> Unit(RPU) subsystem. This patch adds dt-bindings for RPU subsystem >>>> (cluster). >>>> >>>> Signed-off-by: Tanmay Shah >>>> --- >>>> >>>> Changes in v6: >>>> - Add maxItems to sram and memory-region property >>>> >>>> Changes in v5: >>>> - Add constraints of the possible values of xlnx,cluster-mode property >>>> - fix description of power-domains property for r5 core >>>> - Remove reg, address-cells and size-cells properties as it is not required >>>> - Fix description of mboxes property >>>> - Add description of each memory-region and remove old .txt binding link >>>> reference in the description >>>> >>>> Changes in v4: >>>> - Add memory-region, mboxes and mbox-names properties in example >>>> >>>> Changes in v3: >>>> - None >>>> >>>> >>>> .../bindings/remoteproc/xlnx,r5f-rproc.yaml | 129 ++++++++++++++++++ >>>> include/dt-bindings/power/xlnx-zynqmp-power.h | 6 + >>>> 2 files changed, 135 insertions(+) >>>> create mode 100644 Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml >>>> >>>> diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml >>>> new file mode 100644 >>>> index 000000000000..cbff1c201a89 >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml >>>> @@ -0,0 +1,129 @@ >>>> +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) >>>> +%YAML 1.2 >>>> +--- >>>> +$id: http://devicetree.org/schemas/remoteproc/xlnx,r5f-rproc.yaml# >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>> + >>>> +title: Xilinx R5F processor subsystem >>>> + >>>> +maintainers: >>>> + - Ben Levinsky >>>> + - Tanmay Shah >>>> + >>>> +description: | >>>> + The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for >>>> + real-time processing based on the Cortex-R5F processor core from ARM. >>>> + The Cortex-R5F processor implements the Arm v7-R architecture and includes a >>>> + floating-point unit that implements the Arm VFPv3 instruction set. >>>> + >>>> +properties: >>>> + compatible: >>>> + const: xlnx,zynqmp-r5fss >>>> + >>>> + xlnx,cluster-mode: >>>> + $ref: /schemas/types.yaml#/definitions/uint32 >>>> + enum: [0, 1, 2] >>>> + description: | >>>> + The RPU MPCore can operate in split mode(Dual-processor performance), Safety >>>> + lock-step mode(Both RPU cores execute the same code in lock-step, >>>> + clock-for-clock) or Single CPU mode (RPU core 0 can be held in reset while >>>> + core 1 runs normally). The processor does not support dynamic configuration. >>>> + Switching between modes is only permitted immediately after a processor reset. >>>> + If set to 1 then lockstep mode and if 0 then split mode. >>>> + If set to 2 then single CPU mode. When not defined, default will be lockstep mode. >>>> + >>>> +patternProperties: >>>> + "^r5f-[a-f0-9]+$": >>>> + type: object >>>> + description: | >>>> + The RPU is located in the Low Power Domain of the Processor Subsystem. >>>> + Each processor includes separate L1 instruction and data caches and >>>> + tightly coupled memories (TCM). System memory is cacheable, but the TCM >>>> + memory space is non-cacheable. >>>> + >>>> + Each RPU contains one 64KB memory and two 32KB memories that >>>> + are accessed via the TCM A and B port interfaces, for a total of 128KB >>>> + per processor. In lock-step mode, the processor has access to 256KB of >>>> + TCM memory. >>>> + >>>> + properties: >>>> + compatible: >>>> + const: xlnx,zynqmp-r5f >>>> + >>>> + power-domains: >>>> + description: RPU core PM domain specifier >>>> + maxItems: 1 >>>> + >>>> + mboxes: >>>> + minItems: 1 >>>> + items: >>>> + - description: mailbox channel to send data to RPU >>>> + - description: mailbox channel to receive data from RPU >>>> + >>>> + mbox-names: >>>> + minItems: 1 >>>> + items: >>>> + - const: tx >>>> + - const: rx >>>> + >>>> + sram: >>>> + $ref: /schemas/types.yaml#/definitions/phandle-array >>>> + maxItems: 8 >>> minItems: 1 >>> maxItems: 8 >>> items: >>> maxItems: 1 >> I have posted v7 which adds "minItems: 1". >> >> However, I didn't get items: part. Is it required to have items: now? > Yes. >> Can I add items: part once TCM bindings are posted? > No. > >> I understand that minItems and maxItems under sram property decides how many >> phandles sram can have. >> >> However, maxItems: 1 under items: field what it describes? > 'phandle-array' is really a matrix type because we can have phandles > plus argument cells. So you have to define each of the 1-8 entries is a > single phandle cell (and no arg cells). Thanks for explanation. I will send new revision as suggested. > > Rob _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel