From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:36240) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hC1au-0007bR-Rh for qemu-devel@nongnu.org; Thu, 04 Apr 2019 08:35:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hC1at-00059P-HV for qemu-devel@nongnu.org; Thu, 04 Apr 2019 08:35:48 -0400 Message-ID: <6b9005b62d51d3a1f44da142936e3d2b4b4dead5.camel@hellion.org.uk> From: Ian Campbell Date: Thu, 04 Apr 2019 13:35:38 +0100 In-Reply-To: <99590ce3f3572a2b02216a5d99cec03ccc3f35a8.1553899050.git.alistair.francis@wdc.com> References: <99590ce3f3572a2b02216a5d99cec03ccc3f35a8.1553899050.git.alistair.francis@wdc.com> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH for 4.1 v2 2/6] target/riscv: Fall back to generating a RISC-V CPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alistair Francis , "qemu-devel@nongnu.org" , "qemu-riscv@nongnu.org" Cc: "alistair23@gmail.com" , "palmer@sifive.com" On Fri, 2019-03-29 at 22:39 +0000, Alistair Francis wrote: > + for (i = 0; i < strlen(riscv_cpu); i++) { > + if (i == 0 && riscv_cpu[i] == 'r' && > + riscv_cpu[i + 1] == 'v') { Dpes something somewhere else enforce a minimum length or can `riscv_cpu[i + 1]` be past the end of the string? Similarly some more times below and also for the `i += 2` bits. > + /* Starts with "rv" */ > + i += 2; > + if (riscv_cpu[i] == '3' && riscv_cpu[i + 1] == '2') { > + i += 2; > + valid = true; > + rvxlen = RV32; > + } > + if (riscv_cpu[i] == '6' && riscv_cpu[i + 1] == '4') { > + i += 2; > + valid = true; > + rvxlen = RV64; > + } > + } Ian. From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1hC1uz-0007Un-VV for mharc-qemu-riscv@gnu.org; Thu, 04 Apr 2019 08:56:33 -0400 Received: from eggs.gnu.org ([209.51.188.92]:36254) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hC1aw-0007cY-K0 for qemu-riscv@nongnu.org; Thu, 04 Apr 2019 08:35:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hC1av-0005DE-OU for qemu-riscv@nongnu.org; Thu, 04 Apr 2019 08:35:50 -0400 Received: from benson.default.arb33.uk0.bigv.io ([2001:41c9:1:41d::16]:53607) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hC1as-00050r-PP; Thu, 04 Apr 2019 08:35:47 -0400 Received: from [194.72.166.2] (helo=bokrug.cam.docker.com) by benson.default.arb33.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.84_2) (envelope-from ) id 1hC1al-00067G-82; Thu, 04 Apr 2019 13:35:39 +0100 Message-ID: <6b9005b62d51d3a1f44da142936e3d2b4b4dead5.camel@hellion.org.uk> From: Ian Campbell To: Alistair Francis , "qemu-devel@nongnu.org" , "qemu-riscv@nongnu.org" Cc: "alistair23@gmail.com" , "palmer@sifive.com" Date: Thu, 04 Apr 2019 13:35:38 +0100 In-Reply-To: <99590ce3f3572a2b02216a5d99cec03ccc3f35a8.1553899050.git.alistair.francis@wdc.com> References: <99590ce3f3572a2b02216a5d99cec03ccc3f35a8.1553899050.git.alistair.francis@wdc.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.30.4-1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:41c9:1:41d::16 X-Mailman-Approved-At: Thu, 04 Apr 2019 08:56:31 -0400 Subject: Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1 v2 2/6] target/riscv: Fall back to generating a RISC-V CPU X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 04 Apr 2019 12:35:51 -0000 On Fri, 2019-03-29 at 22:39 +0000, Alistair Francis wrote: > + for (i = 0; i < strlen(riscv_cpu); i++) { > + if (i == 0 && riscv_cpu[i] == 'r' && > + riscv_cpu[i + 1] == 'v') { Dpes something somewhere else enforce a minimum length or can `riscv_cpu[i + 1]` be past the end of the string? Similarly some more times below and also for the `i += 2` bits. > + /* Starts with "rv" */ > + i += 2; > + if (riscv_cpu[i] == '3' && riscv_cpu[i + 1] == '2') { > + i += 2; > + valid = true; > + rvxlen = RV32; > + } > + if (riscv_cpu[i] == '6' && riscv_cpu[i + 1] == '4') { > + i += 2; > + valid = true; > + rvxlen = RV64; > + } > + } Ian.