All of lore.kernel.org
 help / color / mirror / Atom feed
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
	Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	Jingoo Han <jingoohan1@gmail.com>,
	Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Stanimir Varbanov <svarbanov@mm-sol.com>,
	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Vinod Koul <vkoul@kernel.org>,
	linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org
Subject: Re: [PATCH v4 6/7] dt-bindings: pci/qcom,pcie: support additional MSI interrupts
Date: Thu, 28 Apr 2022 14:07:58 +0200	[thread overview]
Message-ID: <6bd8eb4e-81eb-7e87-155b-f48b487e16ae@linaro.org> (raw)
In-Reply-To: <20220428115934.3414641-7-dmitry.baryshkov@linaro.org>

On 28/04/2022 13:59, Dmitry Baryshkov wrote:
> On Qualcomm platforms each group of 32 MSI vectors is routed to the
> separate GIC interrupt. Document mapping of additional interrupts.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  .../devicetree/bindings/pci/qcom,pcie.yaml    | 51 ++++++++++++++++++-
>  1 file changed, 50 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> index 0b69b12b849e..a8f99bca389e 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> @@ -43,11 +43,20 @@ properties:
>      maxItems: 5
>  
>    interrupts:
> -    maxItems: 1
> +    minItems: 1
> +    maxItems: 8
>  
>    interrupt-names:
> +    minItems: 1
>      items:
>        - const: msi
> +      - const: msi2
> +      - const: msi3
> +      - const: msi4
> +      - const: msi5
> +      - const: msi6
> +      - const: msi7
> +      - const: msi8
>  
>    # Common definitions for clocks, clock-names and reset.
>    # Platform constraints are described later.
> @@ -623,6 +632,46 @@ allOf:
>          - resets
>          - reset-names
>  
> +    # On newer chipsets support either 1 or 8 msi interrupts
> +    # On older chipsets it's always 1 msi interrupt
> +  - if:
> +      properties:
> +        compatibles:
> +          contains:
> +            enum:
> +              - qcom,pcie-msm8996
> +              - qcom,pcie-sc7280
> +              - qcom,pcie-sc8180x
> +              - qcom,pcie-sdm845
> +              - qcom,pcie-sm8150
> +              - qcom,pcie-sm8250
> +              - qcom,pcie-sm8450-pcie0
> +              - qcom,pcie-sm8450-pcie1
> +    then:
> +      oneOf:
> +        - properties:
> +            interrupts:
> +              minItems: 1

minItems should not be needed here and in places below, because it is
equal to maxItems.

> +              maxItems: 1
> +            interrupt-names:
> +              minItems: 1
> +              maxItems: 1
> +        - properties:
> +            interrupts:
> +              minItems: 8
> +              maxItems: 8
> +            interrupt-names:
> +              minItems: 8
> +              maxItems: 8
> +    else:
> +      properties:
> +        interrupts:
> +          minItems: 1
> +          maxItems: 1
> +        interrupt-names:
> +          minItems: 1
> +          maxItems: 1
> +
>  unevaluatedProperties: false
>  
>  examples:


Best regards,
Krzysztof

  reply	other threads:[~2022-04-28 12:08 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-28 11:59 [PATCH v4 0/7] PCI: qcom: Fix higher MSI vectors handling Dmitry Baryshkov
2022-04-28 11:59 ` [PATCH v4 1/7] PCI: qcom: Revert "PCI: qcom: Add support for handling MSIs from 8 endpoints" Dmitry Baryshkov
2022-04-28 11:59 ` [PATCH v4 2/7] PCI: dwc: Correct msi_irq condition in dw_pcie_free_msi() Dmitry Baryshkov
2022-04-28 11:59 ` [PATCH v4 3/7] PCI: dwc: Add msi_host_deinit callback Dmitry Baryshkov
2022-04-28 11:59 ` [PATCH v4 4/7] PCI: dwc: Export several functions useful for MSI implentations Dmitry Baryshkov
2022-04-28 11:59 ` [PATCH v4 5/7] PCI: qcom: Handle MSI IRQs properly Dmitry Baryshkov
2022-04-28 11:59 ` [PATCH v4 6/7] dt-bindings: pci/qcom,pcie: support additional MSI interrupts Dmitry Baryshkov
2022-04-28 12:07   ` Krzysztof Kozlowski [this message]
2022-04-28 13:57     ` Dmitry Baryshkov
2022-04-28 14:06       ` Krzysztof Kozlowski
2022-04-28 14:45         ` Dmitry Baryshkov
2022-04-29  6:49           ` Krzysztof Kozlowski
2022-04-28 11:59 ` [PATCH v4 7/7] arm64: dts: qcom: sm8250: provide " Dmitry Baryshkov

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=6bd8eb4e-81eb-7e87-155b-f48b487e16ae@linaro.org \
    --to=krzysztof.kozlowski@linaro.org \
    --cc=agross@kernel.org \
    --cc=bhelgaas@google.com \
    --cc=bjorn.andersson@linaro.org \
    --cc=devicetree@vger.kernel.org \
    --cc=dmitry.baryshkov@linaro.org \
    --cc=gustavo.pimentel@synopsys.com \
    --cc=jingoohan1@gmail.com \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=lorenzo.pieralisi@arm.com \
    --cc=manivannan.sadhasivam@linaro.org \
    --cc=robh+dt@kernel.org \
    --cc=svarbanov@mm-sol.com \
    --cc=vkoul@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.